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dm: spi: Convert Freescale ESPI driver to driver model
Modify the Freescale ESPI driver to support the driver model. Also resolved the following problems: ===================== WARNING ====================== This board does not use CONFIG_DM_SPI. Please update the board before v2019.04 for no dm conversion and v2019.07 for partially dm converted drivers. Failure to update can lead to driver/board removal See doc/driver-model/MIGRATION.txt for more info. ==================================================== ===================== WARNING ====================== This board does not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ==================================================== Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Chuanhua Han
Jagan Teki
parent
47df4b5f2a
commit
8d50551dc7
2 changed files with 338 additions and 124 deletions
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@ -3,7 +3,9 @@
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* eSPI controller driver.
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*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* Copyright 2020 NXP
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* Author: Mingkai Hu (Mingkai.hu@freescale.com)
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* Chuanhua Han (chuanhua.han@nxp.com)
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*/
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#include <common.h>
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@ -14,10 +16,16 @@
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#include <malloc.h>
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#include <spi.h>
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#include <asm/immap_85xx.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <dm/platform_data/fsl_espi.h>
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struct fsl_spi_slave {
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struct spi_slave slave;
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ccsr_espi_t *espi;
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u32 speed_hz;
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unsigned int cs;
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unsigned int div16;
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unsigned int pm;
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int tx_timeout;
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@ -31,6 +39,9 @@ struct fsl_spi_slave {
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#define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
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#define US_PER_SECOND 1000000UL
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/* default SCK frequency, unit: HZ */
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#define FSL_ESPI_DEFAULT_SCK_FREQ 10000000
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#define ESPI_MAX_CS_NUM 4
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#define ESPI_FIFO_WIDTH_BIT 32
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@ -65,116 +76,27 @@ struct fsl_spi_slave {
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#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct fsl_spi_slave *fsl;
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sys_info_t sysinfo;
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unsigned long spibrg = 0;
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unsigned long spi_freq = 0;
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unsigned char pm = 0;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
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if (!fsl)
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return NULL;
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fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
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fsl->mode = mode;
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fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
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/* Set eSPI BRG clock source */
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get_sys_info(&sysinfo);
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spibrg = sysinfo.freq_systembus / 2;
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fsl->div16 = 0;
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if ((spibrg / max_hz) > 32) {
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fsl->div16 = ESPI_CSMODE_DIV16;
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pm = spibrg / (max_hz * 16 * 2);
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if (pm > 16) {
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pm = 16;
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debug("Requested speed is too low: %d Hz, %ld Hz "
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"is used.\n", max_hz, spibrg / (32 * 16));
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}
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} else
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pm = spibrg / (max_hz * 2);
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if (pm)
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pm--;
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fsl->pm = pm;
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if (fsl->div16)
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spi_freq = spibrg / ((pm + 1) * 2 * 16);
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else
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spi_freq = spibrg / ((pm + 1) * 2);
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/* set tx_timeout to 10 times of one espi FIFO entry go out */
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fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
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* 10), spi_freq);
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return &fsl->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
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free(fsl);
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}
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int spi_claim_bus(struct spi_slave *slave)
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void fsl_spi_cs_activate(struct spi_slave *slave, uint cs)
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{
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struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
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ccsr_espi_t *espi = fsl->espi;
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unsigned char pm = fsl->pm;
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unsigned int cs = slave->cs;
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unsigned int mode = fsl->mode;
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unsigned int div16 = fsl->div16;
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int i;
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unsigned int com = 0;
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size_t data_len = fsl->data_len;
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debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs);
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/* Enable eSPI interface */
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out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
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| ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
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out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
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out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */
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/* Init CS mode interface */
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for (i = 0; i < ESPI_MAX_CS_NUM; i++)
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out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);
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out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
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~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
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| ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK
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| ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF)));
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/* Set eSPI BRG clock source */
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out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
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| ESPI_CSMODE_PM(pm) | div16);
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/* Set eSPI mode */
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if (mode & SPI_CPHA)
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out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
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| ESPI_CSMODE_CP_BEGIN_EDGCLK);
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if (mode & SPI_CPOL)
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out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
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| ESPI_CSMODE_CI_INACTIVEHIGH);
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/* Character bit order: msb first */
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out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
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| ESPI_CSMODE_REV_MSB_FIRST);
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/* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
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out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
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| ESPI_CSMODE_LEN(7));
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return 0;
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com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));
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com |= ESPI_COM_CS(cs);
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com |= ESPI_COM_TRANLEN(data_len - 1);
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out_be32(&espi->com, com);
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}
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void spi_release_bus(struct spi_slave *slave)
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void fsl_spi_cs_deactivate(struct spi_slave *slave)
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{
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struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
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ccsr_espi_t *espi = fsl->espi;
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/* clear the RXCNT and TXCNT */
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out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));
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out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN);
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}
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static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout)
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@ -207,7 +129,8 @@ static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout)
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debug("***spi_xfer:...Tx timeout! event = %08x\n", event);
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}
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static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes)
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static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din,
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unsigned int bytes)
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{
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ccsr_espi_t *espi = fsl->espi;
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unsigned int tmpdin, rx_times;
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@ -239,10 +162,17 @@ static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes)
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return bytes;
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
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void *data_in, unsigned long flags)
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void espi_release_bus(struct fsl_spi_slave *fsl)
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{
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struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
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/* Disable the SPI hardware */
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out_be32(&fsl->espi->mode,
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in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN));
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}
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int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen,
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const void *data_out, void *data_in, unsigned long flags)
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{
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struct spi_slave *slave = &fsl->slave;
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ccsr_espi_t *espi = fsl->espi;
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unsigned int event, rx_bytes;
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const void *dout = NULL;
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@ -261,13 +191,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
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max_tran_len = fsl->max_transfer_length;
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switch (flags) {
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case SPI_XFER_BEGIN:
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cmd_len = fsl->cmd_len = data_len;
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cmd_len = data_len;
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fsl->cmd_len = cmd_len;
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memcpy(cmd_buf, data_out, cmd_len);
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return 0;
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case 0:
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case SPI_XFER_END:
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if (bitlen == 0) {
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spi_cs_deactivate(slave);
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fsl_spi_cs_deactivate(slave);
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return 0;
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}
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buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len);
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@ -307,7 +238,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
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num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4);
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num_bytes = (tran_len + cmd_len) % 4;
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fsl->data_len = tran_len + cmd_len;
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spi_cs_activate(slave);
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fsl_spi_cs_activate(slave, cs);
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/* Clear all eSPI events */
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out_be32(&espi->event , 0xffffffff);
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@ -350,37 +281,304 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
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*(int *)buffer += tran_len;
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}
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}
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spi_cs_deactivate(slave);
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fsl_spi_cs_deactivate(slave);
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}
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free(buffer);
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return 0;
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}
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void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs)
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{
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ccsr_espi_t *espi = fsl->espi;
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unsigned char pm = fsl->pm;
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unsigned int mode = fsl->mode;
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unsigned int div16 = fsl->div16;
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int i;
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/* Enable eSPI interface */
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out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
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| ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
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out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */
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out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */
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/* Init CS mode interface */
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for (i = 0; i < ESPI_MAX_CS_NUM; i++)
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out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);
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out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &
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~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16
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| ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK
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| ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF)));
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/* Set eSPI BRG clock source */
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out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
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| ESPI_CSMODE_PM(pm) | div16);
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/* Set eSPI mode */
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if (mode & SPI_CPHA)
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out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
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| ESPI_CSMODE_CP_BEGIN_EDGCLK);
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if (mode & SPI_CPOL)
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out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
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| ESPI_CSMODE_CI_INACTIVEHIGH);
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/* Character bit order: msb first */
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out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
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| ESPI_CSMODE_REV_MSB_FIRST);
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/* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
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out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])
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| ESPI_CSMODE_LEN(7));
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}
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void espi_setup_slave(struct fsl_spi_slave *fsl)
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{
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unsigned int max_hz;
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sys_info_t sysinfo;
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unsigned long spibrg = 0;
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unsigned long spi_freq = 0;
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unsigned char pm = 0;
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max_hz = fsl->speed_hz;
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get_sys_info(&sysinfo);
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spibrg = sysinfo.freq_systembus / 2;
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fsl->div16 = 0;
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if ((spibrg / max_hz) > 32) {
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fsl->div16 = ESPI_CSMODE_DIV16;
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pm = spibrg / (max_hz * 16 * 2);
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if (pm > 16) {
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pm = 16;
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debug("max_hz is too low: %d Hz, %ld Hz is used.\n",
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max_hz, spibrg / (32 * 16));
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}
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} else {
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pm = spibrg / (max_hz * 2);
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}
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if (pm)
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pm--;
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fsl->pm = pm;
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if (fsl->div16)
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spi_freq = spibrg / ((pm + 1) * 2 * 16);
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else
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spi_freq = spibrg / ((pm + 1) * 2);
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/* set tx_timeout to 10 times of one espi FIFO entry go out */
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fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
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* 10), spi_freq);/* Set eSPI BRG clock source */
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}
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#if !CONFIG_IS_ENABLED(DM_SPI)
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs < ESPI_MAX_CS_NUM;
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}
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void spi_cs_activate(struct spi_slave *slave)
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
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ccsr_espi_t *espi = fsl->espi;
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unsigned int com = 0;
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size_t data_len = fsl->data_len;
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struct fsl_spi_slave *fsl;
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com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));
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com |= ESPI_COM_CS(slave->cs);
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com |= ESPI_COM_TRANLEN(data_len - 1);
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out_be32(&espi->com, com);
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
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if (!fsl)
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return NULL;
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fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
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fsl->mode = mode;
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fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
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fsl->speed_hz = max_hz;
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espi_setup_slave(fsl);
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return &fsl->slave;
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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void spi_free_slave(struct spi_slave *slave)
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{
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struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
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ccsr_espi_t *espi = fsl->espi;
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/* clear the RXCNT and TXCNT */
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out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));
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out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN);
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free(fsl);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
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espi_claim_bus(fsl, slave->cs);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
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espi_release_bus(fsl);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave;
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return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags);
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}
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#else
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static void __espi_set_speed(struct fsl_spi_slave *fsl)
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{
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espi_setup_slave(fsl);
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/* Set eSPI BRG clock source */
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out_be32(&fsl->espi->csmode[fsl->cs],
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in_be32(&fsl->espi->csmode[fsl->cs])
|
||||
| ESPI_CSMODE_PM(fsl->pm) | fsl->div16);
|
||||
}
|
||||
|
||||
static void __espi_set_mode(struct fsl_spi_slave *fsl)
|
||||
{
|
||||
/* Set eSPI mode */
|
||||
if (fsl->mode & SPI_CPHA)
|
||||
out_be32(&fsl->espi->csmode[fsl->cs],
|
||||
in_be32(&fsl->espi->csmode[fsl->cs])
|
||||
| ESPI_CSMODE_CP_BEGIN_EDGCLK);
|
||||
if (fsl->mode & SPI_CPOL)
|
||||
out_be32(&fsl->espi->csmode[fsl->cs],
|
||||
in_be32(&fsl->espi->csmode[fsl->cs])
|
||||
| ESPI_CSMODE_CI_INACTIVEHIGH);
|
||||
}
|
||||
|
||||
static int fsl_espi_claim_bus(struct udevice *dev)
|
||||
{
|
||||
struct udevice *bus = dev->parent;
|
||||
struct fsl_spi_slave *fsl = dev_get_priv(bus);
|
||||
|
||||
espi_claim_bus(fsl, fsl->cs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_espi_release_bus(struct udevice *dev)
|
||||
{
|
||||
struct udevice *bus = dev->parent;
|
||||
struct fsl_spi_slave *fsl = dev_get_priv(bus);
|
||||
|
||||
espi_release_bus(fsl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen,
|
||||
const void *dout, void *din, unsigned long flags)
|
||||
{
|
||||
struct udevice *bus = dev->parent;
|
||||
struct fsl_spi_slave *fsl = dev_get_priv(bus);
|
||||
|
||||
return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags);
|
||||
}
|
||||
|
||||
static int fsl_espi_set_speed(struct udevice *bus, uint speed)
|
||||
{
|
||||
struct fsl_spi_slave *fsl = dev_get_priv(bus);
|
||||
|
||||
debug("%s speed %u\n", __func__, speed);
|
||||
fsl->speed_hz = speed;
|
||||
|
||||
__espi_set_speed(fsl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_espi_set_mode(struct udevice *bus, uint mode)
|
||||
{
|
||||
struct fsl_spi_slave *fsl = dev_get_priv(bus);
|
||||
|
||||
debug("%s mode %u\n", __func__, mode);
|
||||
fsl->mode = mode;
|
||||
|
||||
__espi_set_mode(fsl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_espi_child_pre_probe(struct udevice *dev)
|
||||
{
|
||||
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
|
||||
struct udevice *bus = dev->parent;
|
||||
struct fsl_spi_slave *fsl = dev_get_priv(bus);
|
||||
|
||||
debug("%s cs %u\n", __func__, slave_plat->cs);
|
||||
fsl->cs = slave_plat->cs;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_espi_probe(struct udevice *bus)
|
||||
{
|
||||
struct fsl_espi_platdata *plat = dev_get_platdata(bus);
|
||||
struct fsl_spi_slave *fsl = dev_get_priv(bus);
|
||||
|
||||
fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr);
|
||||
fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
|
||||
fsl->speed_hz = plat->speed_hz;
|
||||
|
||||
debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_spi_ops fsl_espi_ops = {
|
||||
.claim_bus = fsl_espi_claim_bus,
|
||||
.release_bus = fsl_espi_release_bus,
|
||||
.xfer = fsl_espi_xfer,
|
||||
.set_speed = fsl_espi_set_speed,
|
||||
.set_mode = fsl_espi_set_mode,
|
||||
};
|
||||
|
||||
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
static int fsl_espi_ofdata_to_platdata(struct udevice *bus)
|
||||
{
|
||||
fdt_addr_t addr;
|
||||
struct fsl_espi_platdata *plat = bus->platdata;
|
||||
const void *blob = gd->fdt_blob;
|
||||
int node = dev_of_offset(bus);
|
||||
|
||||
addr = dev_read_addr(bus);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
plat->regs_addr = lower_32_bits(addr);
|
||||
plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
|
||||
FSL_ESPI_DEFAULT_SCK_FREQ);
|
||||
|
||||
debug("ESPI: regs=%p, max-frequency=%d\n",
|
||||
&plat->regs_addr, plat->speed_hz);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id fsl_espi_ids[] = {
|
||||
{ .compatible = "fsl,mpc8536-espi" },
|
||||
{ }
|
||||
};
|
||||
#endif
|
||||
|
||||
U_BOOT_DRIVER(fsl_espi) = {
|
||||
.name = "fsl_espi",
|
||||
.id = UCLASS_SPI,
|
||||
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
.of_match = fsl_espi_ids,
|
||||
.ofdata_to_platdata = fsl_espi_ofdata_to_platdata,
|
||||
#endif
|
||||
.ops = &fsl_espi_ops,
|
||||
.platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata),
|
||||
.priv_auto_alloc_size = sizeof(struct fsl_spi_slave),
|
||||
.probe = fsl_espi_probe,
|
||||
.child_pre_probe = fsl_espi_child_pre_probe,
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
16
include/dm/platform_data/fsl_espi.h
Normal file
16
include/dm/platform_data/fsl_espi.h
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef __fsl_espi_h
|
||||
#define __fsl_espi_h
|
||||
|
||||
struct fsl_espi_platdata {
|
||||
uint flags;
|
||||
uint speed_hz;
|
||||
uint num_chipselect;
|
||||
fdt_addr_t regs_addr;
|
||||
};
|
||||
|
||||
#endif /* __fsl_espi_h */
|
||||
Loading…
Add table
Reference in a new issue