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https://github.com/AsahiLinux/u-boot
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i2c: i2c-cortina: added CAxxxx I2C support
Add I2C controller support for Cortina Access CAxxxx SoCs Signed-off-by: Arthur Li <arthur.li@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Heiko Schocher <hs@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de> hs: fixed build error, add include log.h
This commit is contained in:
parent
5c2c3e8b44
commit
7f5ea25062
6 changed files with 465 additions and 0 deletions
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@ -182,6 +182,8 @@ F: drivers/gpio/cortina_gpio.c
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F: drivers/watchdog/cortina_wdt.c
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F: drivers/serial/serial_cortina.c
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F: drivers/mmc/ca_dw_mmc.c
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F: drivers/i2c/i2c-cortina.c
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F: drivers/i2c/i2c-cortina.h
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ARM/CZ.NIC TURRIS MOX SUPPORT
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M: Marek Behun <marek.behun@nic.cz>
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@ -740,6 +742,8 @@ F: drivers/gpio/cortina_gpio.c
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F: drivers/watchdog/cortina_wdt.c
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F: drivers/serial/serial_cortina.c
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F: drivers/mmc/ca_dw_mmc.c
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F: drivers/i2c/i2c-cortina.c
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F: drivers/i2c/i2c-cortina.h
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MIPS MSCC
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M: Gregory CLEMENT <gregory.clement@bootlin.com>
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18
doc/device-tree-bindings/i2c/i2c-cortina.txt
Normal file
18
doc/device-tree-bindings/i2c/i2c-cortina.txt
Normal file
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@ -0,0 +1,18 @@
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* I2C for Cortina platforms
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Required properties :
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- compatible : Must be "cortina,ca-i2c"
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- reg : Offset and length of the register set for the device
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Recommended properties :
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- clock-frequency : desired I2C bus clock frequency in Hz. If not specified,
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default value is 100000. Possible values are 100000,
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400000 and 1000000.
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Examples :
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i2c: i2c@f4329120 {
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compatible = "cortina,ca-i2c";
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reg = <0x0 0xf4329120 0x28>;
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clock-frequency = <400000>;
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};
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@ -93,6 +93,14 @@ config SYS_I2C_CADENCE
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Say yes here to select Cadence I2C Host Controller. This controller is
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e.g. used by Xilinx Zynq.
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config SYS_I2C_CA
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tristate "Cortina-Access I2C Controller"
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depends on DM_I2C && CORTINA_PLATFORM
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default n
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help
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Add support for the Cortina Access I2C host controller.
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Say yes here to select Cortina-Access I2C Host Controller.
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config SYS_I2C_DAVINCI
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bool "Davinci I2C Controller"
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depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
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@ -12,6 +12,7 @@ obj-$(CONFIG_SYS_I2C) += i2c_core.o
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obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
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obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
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obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
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obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o
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obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
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obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
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ifdef CONFIG_DM_PCI
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347
drivers/i2c/i2c-cortina.c
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347
drivers/i2c/i2c-cortina.c
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@ -0,0 +1,347 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2020
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* Arthur Li, Cortina Access, arthur.li@cortina-access.com.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <log.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <mapmem.h>
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#include "i2c-cortina.h"
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static void set_speed(struct i2c_regs *regs, int i2c_spd)
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{
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union ca_biw_cfg i2c_cfg;
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i2c_cfg.wrd = readl(®s->i2c_cfg);
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i2c_cfg.bf.core_en = 0;
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writel(i2c_cfg.wrd, ®s->i2c_cfg);
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switch (i2c_spd) {
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case IC_SPEED_MODE_FAST_PLUS:
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i2c_cfg.bf.prer = CORTINA_PER_IO_FREQ /
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(5 * I2C_SPEED_FAST_PLUS_RATE) - 1;
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break;
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case IC_SPEED_MODE_STANDARD:
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i2c_cfg.bf.prer = CORTINA_PER_IO_FREQ /
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(5 * I2C_SPEED_STANDARD_RATE) - 1;
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break;
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case IC_SPEED_MODE_FAST:
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default:
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i2c_cfg.bf.prer = CORTINA_PER_IO_FREQ /
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(5 * I2C_SPEED_FAST_RATE) - 1;
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break;
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}
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i2c_cfg.bf.core_en = 1;
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writel(i2c_cfg.wrd, ®s->i2c_cfg);
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}
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static int ca_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
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{
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struct ca_i2c *priv = dev_get_priv(bus);
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int i2c_spd;
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if (speed >= I2C_SPEED_FAST_PLUS_RATE) {
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i2c_spd = IC_SPEED_MODE_FAST_PLUS;
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priv->speed = I2C_SPEED_FAST_PLUS_RATE;
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} else if (speed >= I2C_SPEED_FAST_RATE) {
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i2c_spd = IC_SPEED_MODE_FAST;
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priv->speed = I2C_SPEED_FAST_RATE;
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} else {
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i2c_spd = IC_SPEED_MODE_STANDARD;
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priv->speed = I2C_SPEED_STANDARD_RATE;
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}
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set_speed(priv->regs, i2c_spd);
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return 0;
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}
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static int ca_i2c_get_bus_speed(struct udevice *bus)
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{
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struct ca_i2c *priv = dev_get_priv(bus);
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return priv->speed;
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}
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static void ca_i2c_init(struct i2c_regs *regs)
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{
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union ca_biw_cfg i2c_cfg;
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i2c_cfg.wrd = readl(®s->i2c_cfg);
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i2c_cfg.bf.core_en = 0;
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i2c_cfg.bf.biw_soft_reset = 1;
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writel(i2c_cfg.wrd, ®s->i2c_cfg);
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mdelay(10);
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i2c_cfg.bf.biw_soft_reset = 0;
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writel(i2c_cfg.wrd, ®s->i2c_cfg);
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set_speed(regs, IC_SPEED_MODE_STANDARD);
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i2c_cfg.wrd = readl(®s->i2c_cfg);
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i2c_cfg.bf.core_en = 1;
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writel(i2c_cfg.wrd, ®s->i2c_cfg);
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}
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static int i2c_wait_complete(struct i2c_regs *regs)
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{
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union ca_biw_ctrl i2c_ctrl;
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unsigned long start_time_bb = get_timer(0);
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i2c_ctrl.wrd = readl(®s->i2c_ctrl);
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while (i2c_ctrl.bf.biwdone == 0) {
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i2c_ctrl.wrd = readl(®s->i2c_ctrl);
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if (get_timer(start_time_bb) >
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(unsigned long)(I2C_BYTE_TO_BB)) {
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printf("%s not done!!!\n", __func__);
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return -ETIMEDOUT;
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}
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}
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/* Clear done bit */
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writel(i2c_ctrl.wrd, ®s->i2c_ctrl);
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return 0;
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}
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static void i2c_setaddress(struct i2c_regs *regs, unsigned int i2c_addr,
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int write_read)
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{
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writel(i2c_addr | write_read, ®s->i2c_txr);
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writel(BIW_CTRL_START | BIW_CTRL_WRITE,
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®s->i2c_ctrl);
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i2c_wait_complete(regs);
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}
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static int i2c_wait_for_bus_busy(struct i2c_regs *regs)
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{
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union ca_biw_ack i2c_ack;
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unsigned long start_time_bb = get_timer(0);
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i2c_ack.wrd = readl(®s->i2c_ack);
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while (i2c_ack.bf.biw_busy) {
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i2c_ack.wrd = readl(®s->i2c_ack);
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if (get_timer(start_time_bb) >
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(unsigned long)(I2C_BYTE_TO_BB)) {
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printf("%s: timeout!\n", __func__);
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static int i2c_xfer_init(struct i2c_regs *regs, uint8_t chip, uint addr,
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int alen, int write_read)
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{
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int addr_len = alen;
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if (i2c_wait_for_bus_busy(regs))
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return 1;
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/* First cycle must write addr + offset */
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chip = ((chip & 0x7F) << 1);
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if (alen == 0 && write_read == I2C_CMD_RD)
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i2c_setaddress(regs, chip, I2C_CMD_RD);
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else
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i2c_setaddress(regs, chip, I2C_CMD_WT);
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while (alen) {
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alen--;
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writel(addr, ®s->i2c_txr);
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if (write_read == I2C_CMD_RD)
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writel(BIW_CTRL_WRITE | BIW_CTRL_STOP,
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®s->i2c_ctrl);
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else
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writel(BIW_CTRL_WRITE, ®s->i2c_ctrl);
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i2c_wait_complete(regs);
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}
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/* Send address again with Read flag if it's read command */
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if (write_read == I2C_CMD_RD && addr_len > 0)
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i2c_setaddress(regs, chip, I2C_CMD_RD);
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return 0;
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}
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static int i2c_xfer_finish(struct i2c_regs *regs)
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{
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/* Dummy read makes bus free */
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writel(BIW_CTRL_READ | BIW_CTRL_STOP, ®s->i2c_ctrl);
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i2c_wait_complete(regs);
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if (i2c_wait_for_bus_busy(regs)) {
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printf("Timed out waiting for bus\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int ca_i2c_read(struct i2c_regs *regs, uint8_t chip, uint addr,
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int alen, uint8_t *buffer, int len)
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{
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unsigned long start_time_rx;
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int rc = 0;
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rc = i2c_xfer_init(regs, chip, addr, alen, I2C_CMD_RD);
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if (rc)
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return rc;
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start_time_rx = get_timer(0);
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while (len) {
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/* ACK_IN is ack value to send during read.
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* ack high only on the very last byte!
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*/
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if (len == 1)
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writel(BIW_CTRL_READ | BIW_CTRL_ACK_IN | BIW_CTRL_STOP,
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®s->i2c_ctrl);
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else
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writel(BIW_CTRL_READ, ®s->i2c_ctrl);
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rc = i2c_wait_complete(regs);
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udelay(1);
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if (rc == 0) {
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*buffer++ =
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(uchar) readl(®s->i2c_rxr);
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len--;
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start_time_rx = get_timer(0);
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} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
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return -ETIMEDOUT;
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}
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}
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i2c_xfer_finish(regs);
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return rc;
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}
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static int ca_i2c_write(struct i2c_regs *regs, uint8_t chip, uint addr,
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int alen, uint8_t *buffer, int len)
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{
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int rc, nb = len;
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unsigned long start_time_tx;
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rc = i2c_xfer_init(regs, chip, addr, alen, I2C_CMD_WT);
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if (rc)
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return rc;
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start_time_tx = get_timer(0);
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while (len) {
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writel(*buffer, ®s->i2c_txr);
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if (len == 1)
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writel(BIW_CTRL_WRITE | BIW_CTRL_STOP,
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®s->i2c_ctrl);
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else
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writel(BIW_CTRL_WRITE, ®s->i2c_ctrl);
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rc = i2c_wait_complete(regs);
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if (rc == 0) {
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len--;
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buffer++;
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start_time_tx = get_timer(0);
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} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static int ca_i2c_probe_chip(struct udevice *bus, uint chip_addr,
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uint chip_flags)
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{
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struct ca_i2c *priv = dev_get_priv(bus);
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int ret;
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u32 tmp;
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/* Try to read the first location of the chip */
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ret = ca_i2c_read(priv->regs, chip_addr, 0, 1, (uchar *)&tmp, 1);
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if (ret)
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ca_i2c_init(priv->regs);
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return ret;
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}
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static int ca_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
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{
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struct ca_i2c *priv = dev_get_priv(bus);
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int ret;
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debug("i2c_xfer: %d messages\n", nmsgs);
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for (; nmsgs > 0; nmsgs--, msg++) {
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debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
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if (msg->flags & I2C_M_RD)
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ret = ca_i2c_read(priv->regs, msg->addr, 0, 0,
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msg->buf, msg->len);
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else
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ret = ca_i2c_write(priv->regs, msg->addr, 0, 0,
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msg->buf, msg->len);
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if (ret) {
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printf("i2c_xfer: %s error\n",
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msg->flags & I2C_M_RD ? "read" : "write");
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return ret;
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}
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}
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return 0;
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}
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static const struct dm_i2c_ops ca_i2c_ops = {
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.xfer = ca_i2c_xfer,
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.probe_chip = ca_i2c_probe_chip,
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.set_bus_speed = ca_i2c_set_bus_speed,
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.get_bus_speed = ca_i2c_get_bus_speed,
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};
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static const struct udevice_id ca_i2c_ids[] = {
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{ .compatible = "cortina,ca-i2c", },
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{ }
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};
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static int ca_i2c_probe(struct udevice *bus)
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{
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struct ca_i2c *priv = dev_get_priv(bus);
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ca_i2c_init(priv->regs);
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return 0;
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}
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static int ca_i2c_ofdata_to_platdata(struct udevice *bus)
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{
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struct ca_i2c *priv = dev_get_priv(bus);
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priv->regs = map_sysmem(dev_read_addr(bus), sizeof(struct i2c_regs));
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if (!priv->regs) {
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printf("I2C: base address is invalid\n");
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return -EINVAL;
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}
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return 0;
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}
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U_BOOT_DRIVER(i2c_cortina) = {
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.name = "i2c_cortina",
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.id = UCLASS_I2C,
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.of_match = ca_i2c_ids,
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.ofdata_to_platdata = ca_i2c_ofdata_to_platdata,
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.probe = ca_i2c_probe,
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.priv_auto_alloc_size = sizeof(struct ca_i2c),
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.ops = &ca_i2c_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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87
drivers/i2c/i2c-cortina.h
Normal file
87
drivers/i2c/i2c-cortina.h
Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2019
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* Cortina Access, <www.cortina-access.com>
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*/
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#ifndef __CA_I2C_H_
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#define __CA_I2C_H_
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)
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struct i2c_regs {
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u32 i2c_cfg;
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u32 i2c_ctrl;
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u32 i2c_txr;
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u32 i2c_rxr;
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u32 i2c_ack;
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u32 i2c_ie0;
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u32 i2c_int0;
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u32 i2c_ie1;
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u32 i2c_int1;
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u32 i2c_stat;
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};
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union ca_biw_cfg {
|
||||
struct biw_cfg {
|
||||
u32 core_en : 1;
|
||||
u32 biw_soft_reset : 1;
|
||||
u32 busywait_en : 1;
|
||||
u32 stretch_en : 1;
|
||||
u32 arb_en : 1;
|
||||
u32 clksync_en : 1;
|
||||
u32 rsrvd1 : 2;
|
||||
u32 spike_cnt : 4;
|
||||
u32 rsrvd2 : 4;
|
||||
u32 prer : 16;
|
||||
} bf;
|
||||
unsigned int wrd;
|
||||
};
|
||||
|
||||
union ca_biw_ctrl {
|
||||
struct biw_ctrl {
|
||||
u32 biwdone : 1;
|
||||
u32 rsrvd1 : 2;
|
||||
u32 ack_in : 1;
|
||||
u32 write : 1;
|
||||
u32 read : 1;
|
||||
u32 stop : 1;
|
||||
u32 start : 1;
|
||||
u32 rsrvd2 : 24;
|
||||
} bf;
|
||||
unsigned int wrd;
|
||||
};
|
||||
|
||||
union ca_biw_ack {
|
||||
struct biw_ack {
|
||||
u32 al :1;
|
||||
u32 biw_busy :1;
|
||||
u32 ack_out :1;
|
||||
u32 rsrvd1 :29;
|
||||
} bf;
|
||||
unsigned int wrd;
|
||||
};
|
||||
#endif /* !__ASSEMBLER__*/
|
||||
|
||||
struct ca_i2c {
|
||||
struct i2c_regs *regs;
|
||||
unsigned int speed;
|
||||
};
|
||||
|
||||
#define I2C_CMD_WT 0
|
||||
#define I2C_CMD_RD 1
|
||||
|
||||
#define BIW_CTRL_DONE BIT(0)
|
||||
#define BIW_CTRL_ACK_IN BIT(3)
|
||||
#define BIW_CTRL_WRITE BIT(4)
|
||||
#define BIW_CTRL_READ BIT(5)
|
||||
#define BIW_CTRL_STOP BIT(6)
|
||||
#define BIW_CTRL_START BIT(7)
|
||||
|
||||
#define I2C_BYTE_TO (CONFIG_SYS_HZ / 500)
|
||||
#define I2C_STOPDET_TO (CONFIG_SYS_HZ / 500)
|
||||
#define I2C_BYTE_TO_BB (10)
|
||||
|
||||
#endif /* __CA_I2C_H_ */
|
Loading…
Reference in a new issue