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spi: zynq_[q]spi: Convert config's to macro's

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Remove below config options and convert them to macros. They have never
been configured to different values than default one. And also it makes
sense to reduce the config_whitelist.
CONFIG_SYS_ZYNQ_SPI_WAIT
CONFIG_SYS_ZYNQ_QSPI_WAIT
CONFIG_XILINX_SPI_IDLE_VAL

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Ashok Reddy Soma 2020-05-18 01:11:00 -06:00 committed by Michal Simek
parent 26e62cc971
commit f44bd3bcfd
4 changed files with 6 additions and 15 deletions
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6
drivers/spi/xilinx_spi.c
View file

@ -76,9 +76,7 @@
SPICR_SPE)
#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
#ifndef CONFIG_XILINX_SPI_IDLE_VAL
#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
#endif
#define XILINX_SPI_IDLE_VAL GENMASK(7, 0)
#define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */
@ -176,7 +174,7 @@ static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) &&
i < priv->fifo_depth) {
d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
d = txp ? *txp++ : XILINX_SPI_IDLE_VAL;
debug("spi_xfer: tx:%x ", d);
/* write out and wait for processing (receive data) */
writel(d & SPIDTR_8BIT_MASK, &regs->spidtr);

6
drivers/spi/zynq_qspi.c
View file

@ -47,9 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
#define ZYNQ_QSPI_FIFO_DEPTH 63
#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
#define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
#define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
/* zynq qspi register set */
struct zynq_qspi_regs {
@ -350,7 +348,7 @@ static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
do {
status = readl(&regs->isr);
} while ((status == 0) &&
(get_timer(timeout) < CONFIG_SYS_ZYNQ_QSPI_WAIT));
(get_timer(timeout) < ZYNQ_QSPI_WAIT));
if (status == 0) {
printf("zynq_qspi_irq_poll: Timeout!\n");

6
drivers/spi/zynq_spi.c
View file

@ -36,9 +36,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
#define ZYNQ_SPI_FIFO_DEPTH 128
#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
#endif
#define ZYNQ_SPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
/* zynq spi register set */
struct zynq_spi_regs {
@ -251,7 +249,7 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
ts = get_timer(0);
status = readl(&regs->isr);
while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
if (get_timer(ts) > ZYNQ_SPI_WAIT) {
printf("spi_xfer: Timeout! TX FIFO not full\n");
return -1;
}

3
scripts/config_whitelist.txt
View file

@ -3984,8 +3984,6 @@ CONFIG_SYS_XHCI_USB1_ADDR
CONFIG_SYS_XHCI_USB2_ADDR
CONFIG_SYS_XHCI_USB3_ADDR
CONFIG_SYS_XIMG_LEN
CONFIG_SYS_ZYNQ_QSPI_WAIT
CONFIG_SYS_ZYNQ_SPI_WAIT
CONFIG_SYS_i2C_FSL
CONFIG_TAM3517_SETTINGS
CONFIG_TCA642X
@ -4211,7 +4209,6 @@ CONFIG_X86_MRC_ADDR
CONFIG_X86_REFCODE_ADDR
CONFIG_X86_REFCODE_RUN_ADDR
CONFIG_XGI_XG22_BASE
CONFIG_XILINX_SPI_IDLE_VAL
CONFIG_XSENGINE
CONFIG_XTFPGA
CONFIG_YAFFSFS_PROVIDE_VALUES