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net: pcnet: Wrap iobase into private data
Instead of using the non-DM-only iobase in struct eth_device, add one into the private data to make DM and non-DM operation possible. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Marek Vasut
Daniel Schwierzeck
parent
834d5cebe5
commit
deca773821
1 changed files with 46 additions and 57 deletions
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@ -83,6 +83,7 @@ struct pcnet_priv {
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unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
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struct pcnet_uncached_priv *uc;
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pci_dev_t dev;
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void __iomem *iobase;
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int cur_rx;
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int cur_tx;
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};
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@ -93,51 +94,39 @@ struct pcnet_priv {
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#define PCNET_RESET 0x14
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#define PCNET_BDP 0x16
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static u16 pcnet_read_csr(struct eth_device *dev, int index)
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static u16 pcnet_read_csr(struct pcnet_priv *lp, int index)
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{
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void __iomem *base = (void __iomem *)dev->iobase;
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writew(index, base + PCNET_RAP);
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return readw(base + PCNET_RDP);
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writew(index, lp->iobase + PCNET_RAP);
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return readw(lp->iobase + PCNET_RDP);
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}
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static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
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static void pcnet_write_csr(struct pcnet_priv *lp, int index, u16 val)
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{
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void __iomem *base = (void __iomem *)dev->iobase;
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writew(index, base + PCNET_RAP);
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writew(val, base + PCNET_RDP);
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writew(index, lp->iobase + PCNET_RAP);
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writew(val, lp->iobase + PCNET_RDP);
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}
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static u16 pcnet_read_bcr(struct eth_device *dev, int index)
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static u16 pcnet_read_bcr(struct pcnet_priv *lp, int index)
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{
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void __iomem *base = (void __iomem *)dev->iobase;
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writew(index, base + PCNET_RAP);
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return readw(base + PCNET_BDP);
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writew(index, lp->iobase + PCNET_RAP);
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return readw(lp->iobase + PCNET_BDP);
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}
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static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
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static void pcnet_write_bcr(struct pcnet_priv *lp, int index, u16 val)
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{
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void __iomem *base = (void __iomem *)dev->iobase;
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writew(index, base + PCNET_RAP);
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writew(val, base + PCNET_BDP);
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writew(index, lp->iobase + PCNET_RAP);
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writew(val, lp->iobase + PCNET_BDP);
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}
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static void pcnet_reset(struct eth_device *dev)
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static void pcnet_reset(struct pcnet_priv *lp)
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{
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void __iomem *base = (void __iomem *)dev->iobase;
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readw(base + PCNET_RESET);
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readw(lp->iobase + PCNET_RESET);
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}
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static int pcnet_check(struct eth_device *dev)
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static int pcnet_check(struct pcnet_priv *lp)
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{
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void __iomem *base = (void __iomem *)dev->iobase;
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writew(88, base + PCNET_RAP);
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return readw(base + PCNET_RAP) == 88;
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writew(88, lp->iobase + PCNET_RAP);
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return readw(lp->iobase + PCNET_RAP) == 88;
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}
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static inline pci_addr_t pcnet_virt_to_mem(struct pcnet_priv *lp, void *addr)
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@ -154,22 +143,22 @@ static struct pci_device_id supported[] = {
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static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
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{
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struct pcnet_priv *lp = dev->priv;
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int chip_version;
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char *chipname;
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int i;
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/* Reset the PCnet controller */
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pcnet_reset(dev);
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pcnet_reset(lp);
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/* Check if register access is working */
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if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
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if (pcnet_read_csr(lp, 0) != 4 || !pcnet_check(lp)) {
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printf("%s: CSR register access check failed\n", dev->name);
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return -1;
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}
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/* Identify the chip */
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chip_version =
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pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
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chip_version = pcnet_read_csr(lp, 88) | (pcnet_read_csr(lp, 89) << 16);
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if ((chip_version & 0xfff) != 0x003)
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return -1;
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chip_version = (chip_version >> 12) & 0xffff;
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@ -199,7 +188,7 @@ static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
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for (i = 0; i < 3; i++) {
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unsigned int val;
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val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
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val = pcnet_read_csr(lp, i + 12) & 0x0ffff;
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/* There may be endianness issues here. */
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dev->enetaddr[2 * i] = val & 0x0ff;
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dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
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@ -218,17 +207,17 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
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PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
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/* Switch pcnet to 32bit mode */
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pcnet_write_bcr(dev, 20, 2);
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pcnet_write_bcr(lp, 20, 2);
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/* Set/reset autoselect bit */
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val = pcnet_read_bcr(dev, 2) & ~2;
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val = pcnet_read_bcr(lp, 2) & ~2;
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val |= 2;
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pcnet_write_bcr(dev, 2, val);
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pcnet_write_bcr(lp, 2, val);
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/* Enable auto negotiate, setup, disable fd */
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val = pcnet_read_bcr(dev, 32) & ~0x98;
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val = pcnet_read_bcr(lp, 32) & ~0x98;
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val |= 0x20;
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pcnet_write_bcr(dev, 32, val);
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pcnet_write_bcr(lp, 32, val);
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/*
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* Enable NOUFLO on supported controllers, with the transmit
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@ -238,12 +227,12 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
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* slower devices. Controllers which do not support NOUFLO will
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* simply be left with a larger transmit FIFO threshold.
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*/
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val = pcnet_read_bcr(dev, 18);
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val = pcnet_read_bcr(lp, 18);
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val |= 1 << 11;
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pcnet_write_bcr(dev, 18, val);
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val = pcnet_read_csr(dev, 80);
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pcnet_write_bcr(lp, 18, val);
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val = pcnet_read_csr(lp, 80);
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val |= 0x3 << 10;
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pcnet_write_csr(dev, 80, val);
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pcnet_write_csr(lp, 80, val);
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uc = lp->uc;
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@ -302,28 +291,28 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
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*/
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barrier();
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addr = pcnet_virt_to_mem(lp, &lp->uc->init_block);
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pcnet_write_csr(dev, 1, addr & 0xffff);
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pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
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pcnet_write_csr(lp, 1, addr & 0xffff);
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pcnet_write_csr(lp, 2, (addr >> 16) & 0xffff);
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pcnet_write_csr(dev, 4, 0x0915);
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pcnet_write_csr(dev, 0, 0x0001); /* start */
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pcnet_write_csr(lp, 4, 0x0915);
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pcnet_write_csr(lp, 0, 0x0001); /* start */
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/* Wait for Init Done bit */
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for (i = 10000; i > 0; i--) {
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if (pcnet_read_csr(dev, 0) & 0x0100)
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if (pcnet_read_csr(lp, 0) & 0x0100)
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break;
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udelay(10);
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}
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if (i <= 0) {
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printf("%s: TIMEOUT: controller init failed\n", dev->name);
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pcnet_reset(dev);
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pcnet_reset(lp);
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return -1;
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}
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/*
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* Finally start network controller operation.
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*/
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pcnet_write_csr(dev, 0, 0x0002);
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pcnet_write_csr(lp, 0, 0x0002);
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return 0;
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}
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@ -367,7 +356,7 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
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writew(0x8300, &entry->status);
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/* Trigger an immediate send poll. */
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pcnet_write_csr(dev, 0, 0x0008);
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pcnet_write_csr(lp, 0, 0x0008);
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failure:
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if (++lp->cur_tx >= TX_RING_SIZE)
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@ -435,16 +424,17 @@ static int pcnet_recv (struct eth_device *dev)
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static void pcnet_halt(struct eth_device *dev)
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{
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struct pcnet_priv *lp = dev->priv;
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int i;
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PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
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/* Reset the PCnet controller */
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pcnet_reset(dev);
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pcnet_reset(lp);
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/* Wait for Stop bit */
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for (i = 1000; i > 0; i--) {
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if (pcnet_read_csr(dev, 0) & 0x4)
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if (pcnet_read_csr(lp, 0) & 0x4)
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break;
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udelay(10);
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}
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@ -498,11 +488,10 @@ int pcnet_initialize(bd_t *bis)
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* Setup the PCI device.
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*/
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
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dev->iobase = pci_mem_to_phys(devbusfn, bar);
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dev->iobase &= ~0xf;
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lp->iobase = (void *)(pci_mem_to_phys(devbusfn, bar) & ~0xf);
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PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
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dev->name, devbusfn, (unsigned long)dev->iobase);
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PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%p: ",
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dev->name, devbusfn, lp->iobase);
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command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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pci_write_config_word(devbusfn, PCI_COMMAND, command);
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