Commit graph

129 commits

Author SHA1 Message Date
Steve Kipisz
cd8845d7a4 am335x_evm: Add support for the NOR module on the memory cape
This patch adds support for the NOR module that attaches
to the memory cape for a Beaglebone board. This does not
add booting support; only support so that you can boot from
SD/MMC and see the NOR module so that it can be programmed.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
[trini: Clean up config changes slightly]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-30 09:21:41 -04:00
Tom Rini
392bba4ad0 am33xx: Correct gpmc_cfg->irqstatus/enable
Based on our usage of the GPMC, either with NOR or NAND we do not need
to be setting the irqstatus or irqenable bits and should clear them like
we have historically.

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-30 09:21:41 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Heiko Schocher
7ea7f689ca arm, am33xx: move uart soft reset code to common place
move uart soft reset code to common place and call
this function from board code, instead of copy and paste
this code for every board.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <mporter@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Tom Rini <trini@ti.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Tom Rini <trini@ti.com>
[trini: Fix igep0033 build, remove 'regval' on pcm051]
Signed-off-by: Tom Rini <trini@ti.com>
2013-06-18 10:40:06 -04:00
Heiko Schocher
7b9c5d0bfd arm, am335x: make mpu pll config configurable
upcoming support for siemens boards switches mpu pll clk in board
code. So make this configurable.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
2013-06-18 09:18:46 -04:00
Heiko Schocher
49f7836500 arm, am33xx: move rtc32k_enable() to common place
move rtc32k_enable() to common place so all am33xx boards can use it.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <mporter@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Tom Rini <trini@ti.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
2013-06-18 09:12:38 -04:00
Tom Rini
30bba01751 am33xx: Fix warning with CONFIG_DISPLAY_CPUINFO
The arm_freq and ddr_freq variables are unused, so remove.  Fixup
whitespace slightly while in here.

Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Tom Rini <trini@ti.com>
2013-05-10 08:25:56 -04:00
Matt Porter
035d563937 am33xx: add pll and clock support for TI814x CPSW
Enables required PLLs and clocks for CPSW on TI814x.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-10 08:25:54 -04:00
Andreas Bießmann
5bf299bc4f asm/omap_gpmc.h: consolidate common defines
arch/arm/include/asm/arch-am33xx/omap_gpmc.h and
arch/arm/include/asm/arch-omap3/omap_gpmc.h are almost the same, consolidate
the common parts into a new header.

Introduce a new asm/omap_gpmc.h which defines the command part and pulls in
the architecture specific one.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-08 11:29:05 -04:00
Tom Rini
5aa014d613 am335x: Enable MMC1 clock
We must not assume ROM has enabled the clock for MMC1.

Reported-by: Koen Kooi <koen@dominion.thruhere.net>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-04-08 11:29:05 -04:00
Matt Porter
4fab8d7bbd am33xx: add dmm support to emif4 library
Adds a config_dmm() routine to support TI814X DMM configuration.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Matt Porter
8b029f22a6 am33xx: add ti814x specific register definitions
Support the ti814x specific register definitions within
arch-am33xx.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Matt Porter
b43c17cba6 am33xx: refactor am33xx clocks and add ti814x support
Split clock.c for am335x and ti814x and add ti814x specific
clock support.

Signed-off-by: Matt Porter <mporter@ti.com>
2013-03-24 12:49:11 -04:00
Matt Porter
3ba65f97cb am33xx: refactor emif4/ddr to support multiple EMIF instances
The AM33xx emif4/ddr support closely matches what is need to support
TI814x except that TI814x has two EMIF instances. Refactor all the
emif4 helper calls and the config_ddr() init function to use an
additional instance number argument.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Matt Porter
81df2bab46 am33xx: convert defines from am33xx-specific to generic names
Eliminate AM33xx specific names to prepare for TI814x support
within AM33xx-land.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Enric Balletbo i Serra
244044e151 ARM: AM33XX: Fix typo that causes an AM duplication in CPU name.
Just fix a typo displaying the CPU info. With CONFIG_DISPLAY_INFO we see
something like AMAM335X-GP rev 0 instead of AM335X-GP rev 0.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
2013-03-24 12:49:10 -04:00
Steve Kipisz
1e7e374b35 am33xx:ddr:Fix config_sdram to work for all DDR
The original write to sdram_config is correct for DDR3 but incorrect
for DDR2 so SPL was hanging. For DDR2, the write to sdram_config
should be after the writes to ref_ctrl. This was working for DDR3
because there was a write of 0x2800 to ref_ctrl before a write
to sdram_config.

Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3),
           Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3)

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
2013-03-22 11:12:53 -04:00
Mark Jackson
296de3bbec Initialise correct GPMC WAITx irq for AM33xx
Currently WAIT0 irq is reset and then WAIT1 irq is enabled.
Fix it such that WAIT0 irq is enabled instead.

Signed-off-by: Mark Jackson <mpfj@newflow.co.uk>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-03-22 10:57:00 -04:00
Tom Rini
0ce033d258 Merge branch 'master' of git://git.denx.de/u-boot-arm
Albert's rework of the linker scripts conflicted with Simon's making
everyone use __bss_end.  We also had a minor conflict over
README.scrapyard being added to in mainline and enhanced in
u-boot-arm/master with proper formatting.

Conflicts:
	arch/arm/cpu/ixp/u-boot.lds
	arch/arm/cpu/u-boot.lds
	arch/arm/lib/Makefile
	board/actux1/u-boot.lds
	board/actux2/u-boot.lds
	board/actux3/u-boot.lds
	board/dvlhost/u-boot.lds
	board/freescale/mx31ads/u-boot.lds
	doc/README.scrapyard
	include/configs/tegra-common.h

Build tested for all of ARM and run-time tested on am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-18 14:37:18 -04:00
Albert ARIBAUD
ef123c5253 Refactor linker-generated arrays
Refactor linker-generated array code so that symbols
which were previously linker-generated are now compiler-
generated. This causes relocation records of type
R_ARM_ABS32 to become R_ARM_RELATIVE, which makes
code which uses LGA able to run before relocation as
well as after.

Note: this affects more than ARM targets, as linker-
lists span possibly all target architectures, notably
PowerPC.

Conflicts:
	arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
	arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
	arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
	board/ait/cam_enc_4xx/u-boot-spl.lds
	board/davinci/da8xxevm/u-boot-spl-da850evm.lds
	board/davinci/da8xxevm/u-boot-spl-hawk.lds
	board/vpac270/u-boot-spl.lds

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-12 23:28:40 +01:00
Albert ARIBAUD
65cdd6430e Remove linker lists (LGAs) from SPL linker scripts
Many SPL linker scripts needlessly include linker lists (aka LGAs).
Remove them whenever possible; keep it only in the seven am335x_evm
variants (am335x_evm, am335x_evm_uart[1-5], am335x_evm_spiboot),
where there is actual content in output section .u_boot_list.

This commit keeps all u-boot.bin and u-boot-spl.bin in ARM targets
byte-identical.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-12 23:28:29 +01:00
Nikita Kiryanov
e3913f56a2 omap_hsmmc: add driver check for write protection
Add check for write protection in omap mmc driver.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-08 16:41:13 -05:00
Nikita Kiryanov
e874d5b001 omap_hsmmc: implement driver check for card detection
Implement driver check for card detection.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2013-03-08 16:41:13 -05:00
Tom Rini
1c382ead7a am33xx: Update DDR3 EMIF configuration sequence
Based on
http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
we need to re-work our sequence in config_sdram slightly to match what
the TRM describes as the correct sequence.  In our current (incorrect)
sequence some edge cases may fail to initalize correctly.

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-08 16:41:12 -05:00
Albert ARIBAUD
79f3877794 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
This required manual merging drivers/mtd/nand/Makefile
and adding am335x_evm support for CONFIG_SPL_NAND_DRIVERS
2013-01-08 13:15:45 +01:00
Mansoor Ahamed
04c3757829 am33xx: add ELM support
AM33XX has Error Location Module (ELM) that can be used in conjuction
with GPMC controller to implement BCH codes fully in hardware.
This code is mostly taken from arago tree.

Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com>
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-12-10 08:54:02 -07:00
Ilya Yanok
8eb16b7f73 am33xx: NAND support
TI AM33XX has the same GPMC controller as OMAP3 so we could just use the
existing omap_gpmc driver. This patch adds adds required
definitions/intialization.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-12-10 08:54:01 -07:00
Ilya Yanok
7df5cf35de am33xx: init OTG hardware and new musb gadget driver
AM33xx has support for dual port MUSB OTG controller. This patch
adds initialization for the controller using new MUSB gadget
driver and ether gadget.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:07 +01:00
Andrew Bradford
25164218b7 am33xx: Enable UART{1,2,3,4,5} clocks
If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232
cape or the am335x_evm daughterboard, enable the required clocks for
the UART in use.

Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
2012-10-25 14:44:24 -07:00
Peter Korsgaard
c00f69dbcd am33xx: support board specific ddr settings
Move the hardcoded ddr2/ddr3 settings for the ti boards to board code,
so other boards can use different types/timings.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[trini: Make apply with rtc32k_enable() in the file]
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25 11:31:38 -07:00
Peter Korsgaard
7f26a5a26f am33xx: move generic parts of pinmux handling out from board/ti/am335x
So they are available for other boards.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
2012-10-25 11:31:37 -07:00
Peter Korsgaard
75a23880a5 am33xx/board: use cpu_mmc_init() for default mmc initialization
So platforms can override it with board_mmc_init() if needed.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
2012-10-25 11:31:37 -07:00
Peter Korsgaard
e363426e99 am33xx: move ti i2c baseboard header handling to board/ti/am335x/
The i2c header is specific to ti(-derived) boards, and not generic for all
am335x boards.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[trini: Make re-apply with rtc32k_enable() applied]
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25 11:31:36 -07:00
Peter Korsgaard
c50cce2758 am33xx/board.c: make wdtimer/uart_base static
Only used here (and uart_base only for SPL).

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
2012-10-25 11:30:50 -07:00
Tom Rini
69916bcf71 am33xx: Add SPI SPL as an option
Add the required config.mk logic for this SoC as well as the BOOT_DEVICE
define.  Finally, enable the options on the am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25 11:30:50 -07:00
Vaibhav Hiremath
000820b583 am335x: Enable RTC 32K OSC clock
In order to support low power state, you must source kernel system
timers to persistent clock, available across suspend/resume.  In case of
AM335x device, the only source we have is, RTC32K, available in
wakeup/always-on domain.  Having said that, during validation it has
been observed that, RTC clock need couple of seconds delay to stabilize
the RTC OSC clock; and such a huge delay is not acceptable in kernel
especially during early init and also it will impact quick/fast boot
use-cases.

So, RTC32k OSC enable dependency has been shifted to
SPL/first-bootloader.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25 11:30:22 -07:00
Joel A Fernandes
391a741162 am33xx: Enable DDR3 for DDR3 version of beaglebone
DDR3 support is tested and working with beaglebone hardware. Include a check
for this board type and configure DDR3. The timings and other configuration
match EVM SK.

Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
Acked-by: Jason Kridner <jdk@ti.com>
2012-10-23 08:33:17 -07:00
Tom Rini
6507f133f3 SPL: Create arch/arm/lib/spl.c for board_init_f and jump_to_image_linux
In SPL (CONFIG_SPL_FRAMEWORK) board_init_f must setup the stack pointer,
clear the BSS and call board_init_r.  We mark this as weak as some
platforms may need to perform additional initalization at this point.
We provide a gd that we know will be in a usable location, once the BSS
has been cleared to help with this as well.  Finally, we no longer call
relocate_code so remove that from the armv7 version.

Next, both board_init_f and jump_to_image_linux are going to be
inherently arch-specific, so move these versions to arch/arm/lib/spl.c

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:49:59 -07:00
Tom Rini
47f7bcae8c SPL: Move the omap SPL framework to common/spl
Add a new flag, CONFIG_SPL_FRAMEWORK to opt into the common/spl SPL
framework, enable on all of the previously using boards.  We move the
spl_ymodem.c portion to common/ and spl_mmc.c to drivers/mmc/.  We leave
the NAND one in-place as we plan to replace it later in this series.

We use common/spl to avoid linker problems with respect to merging
constant strings in objects.   Otherwise all strings in common/ will be
linked in and kept which grows SPL in size too much.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:49:59 -07:00
Tom Rini
55cdbb8d4e ARM: SPL: Add <asm/spl.h> and <asm/arch/spl.h>
Move the SPL prototypes from <asm/omap_common.h> into <asm/spl.h> and
add <asm/arch/spl.h> for arch specific portions of CONFIG_SPL_FRAMEWORK.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:49:57 -07:00
Tom Rini
14dace7058 am33xx: Remove redundant timer config
We have the timer code in arch/arm/cpu/armv7/omap-common/timer.c that
has been configuring and enabling the timer, so remove our code that
does the same thing by different methods.

Tested on EVM GP, SK-EVM and Beaglebone.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-04 17:05:39 -07:00
Satyanarayana, Sandhya
6995a28937 am33xx evm: Update secure_emif_sdram_config during ddr init
This patch updates secure_emif_sdram_config with the
same value written to sdram_config during ddr3 initialization.

During suspend/resume, this value is copied into sdram_config.
With this, a write to sdram_config at the end of resume sequence
which triggers an init sequence can be avoided.

Without this register write in place, the DDR_RESET line goes
low for a few cycles during resume which is a violation of the
JEDEC spec.

Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
2012-09-01 14:58:19 +02:00
Tom Rini
4c0620bf42 am33xx: Add support, update omap3 McSPI driver
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:18 +02:00
Tom Rini
0689a2ef19 am33xx: Correct MMC1, remove MMC2 support
- Correct the MMC1 base offset
- Remove MMC2 (that area is reserved and not MMC2).
- Add the real BOOT_DEVICE_MMC2 value

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:18 +02:00
Tom Rini
db7dd8109c am33xx: Rework pinmux functions
- Move definition of the EEPROM contents to <asm/arch/sys_proto.h>
  - Make some defines a little less generic now.
- Pinmux must be done by done by SPL now.
- Create 3 pinmux functions, uart0, i2c0 and board.
- Add pinmux specific to Starter Kit EVM for MMC now.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
726c05d2cf am33xx evm: Add CONFIG_CMD_EEPROM and related
am33xx boards have at least one eeprom and in the case of beaglebones
with capes, more.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
65d750be59 am33xx: Add support for TI AM335x StarterKit EVM
- Board requires gpio0 #7 to be set to power DDR3.
- Board uses DDR3, add a way to determine which DDR type to call
  config_ddr with.
- Both of the above require filling in the header structure early, move
  it into the data section.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
973b663820 am33xx: Remove board/ti/am335x/evm.c
The intention has always been (and boards are to support) an i2c EEPROM
that will identify what hardware they are, allowing a single binary to
support multiple boards.  As such, remove the 'evm.c' file as there is
nothing EVM centric in it currently, only SoC peripheral configuration.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
d4898ea896 am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and support
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
318f27c98f am33xx: Rework config_ddr to make DDR3 support easier.
In order to support DDR3 as well as DDR2, we need to perform the same
init sequence, but with different values.  So change config_ddr() to
toggle setting pointers/etc for what DDR2 wants, and then calling.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
942d3f0174 am33xx: Move some variables in emif4.c, mark them static.
We need vtpreg and ddrctrl but no longer need a second ddrregs.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
a74f0c7cb5 am33xx: Correct and clean up ddr_regs struct
The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported).  Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero, remove.  Next, setting of the
'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the
ddr_data entries, so program it there.  Finally, comment on how we are
configuring the DATA1 registers that correspond to the DATA0 (dt0)
registers defined in the struct.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
82afcc9efd am33xx: Do not touch 'ratio1' fields
The various ratio1 fields are not documented in any of the documentation
I can find.  Removing these and testing has yielded success, so remove
the code that sets them and move their locations into the reserved
fields.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
5ac3b7ada1 am33xx: Rework config_io_ctrl slightly
This function sets a number of related registers to the same value (the
registers in question all have the same field descriptions and are
related in operation).  Rather than defining a struct and setting the
value repeatedly, just pass in the value.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
ff7ec0f945 am33xx: Use emif_regs struct for storing initialization values
Rather than defining our own structs to note what to use when
programming the EMIF and related re-use the emif_regs struct.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
87a1acbb69 am33xx: Turn a number of 'int' functions to 'void'
A number of memory initalization functions were int and always returned
0.  Further it's not feasible to be doing error checking here, so simply
turn them into void functions.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
c48c895433 am33xx: Document what we're doing with ddrctrl->ddrckectrl
- Remove the call to set ddrctrl->ddrioctrl as it's all zeros.
- Comment what we're really setting in ddrctrl->ddrckectrl which is that
  we're operating in the normal mode where EMIF/PHY clock is controlled
  by the PHY.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
c8da4a587c am33xx: Clean up unused DDR defines, prefix more with 'DDR2'
- Remove a handful of unused defines.
- Prefix more values with 'DDR2' as DDR3 will require different values.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
b971dfad6a am33xx: Move the call to ddr_pll_config, make it take the frequency
Depending on if we have DDR2 or DDR3 on the board we will need to call
ddr_pll_config with a different value.  This call can be delayed
slightly to the point where we know which type of memory we have.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
fda35eb982 am33xx: Pass to config_ddr the type of memory that is connected
We need to pass in the type of memory that is connected to the board.
The only reliable way to do this is to know what type of board we are
running on (which later will be knowable in s_init()).  For now, pass in
the value of DDR2.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
bce58fece5 am33xx: Make config_cmd_ctrl / config_ddr_data take const structs
Rework the EMIF4/DDR code slightly to setup the structs that
config_cmd_ctrl and config_ddr_data take to be setup at compile time and
mark them as const.  This lets us simplify the calling path slightly as
well as making it easier to deal with DDR3.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
10e7e36daf am33xx: Rework DDR2 EMIF initalization slightly
With the previous bugfix we now don't need to set two different REF_CTRL
values and instead set the final value.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
372f11f58d am33xx: Bugfix to config_sdram()
When we change SDRAM_CONFIG this triggers a refresh based on all of the
parameters that we have programmed so we must do this last.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
13f1c44bc5 am33xx: Remove extra check in enable_ddr_clocks
We do not need to check for EMIF_GCLK and L3_GCLK being active.  This
was a hold-over from bringup and no longer required.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
7d5eb34908 am33xx: Convert to using <asm/emif.h> to describe the EMIF
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:11 +02:00
Tom Rini
a438c756b6 am33xx: Enable gpio0 clock
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:11 +02:00
Chandan Nath
e79cd8eb9b am33xx: CPSW init and definitions
This patch adds platform-specific initialization for CPSW
switch on TI AM33XX SoCs.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
[Ilya: split init out of original patch]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-09-01 14:58:11 +02:00
Steve Sakoman
d3decdebde omap: am335x_evm: enable i2c1 channel
This patch sets up pinmux, enables fclk, and
defines CONFIG_I2C_MULTI_BUS

Signed-off-by: Steve Sakoman <steve@sakoman.com>
2012-09-01 14:58:10 +02:00
Steve Sakoman
3b97152b63 omap: am33xx: enable gpio support
This patch uses the code in omap-common to support gpio modules 1-3
on am33xx based boards.

It adds base address and register definitions, enables clocks to the
modules, and enables building the common gpio code for CONFIG_AM33XX
as well as CONFIG_OMAP

Signed-off-by: Steve Sakoman <steve@sakoman.com>
2012-09-01 14:58:09 +02:00
Tom Rini
2ab2810375 am33xx: Do not call init_timer twice
We do not need to call init_timer both in SPL and U-Boot itself, just
SPL needs to initialize the timer.

Signed-off-by: Tom Rini <trini@ti.com>
2012-07-07 14:07:21 +02:00
Jonathan Solnit
bbbc1ae921 ARM:OMAP+:MMC: Add parameters to MMC init
Add parameters to the OMAP MMC initialization function so the board can
mask host capabilities and set the maximum clock frequency.  While the
OMAP supports a certain set of MMC host capabilities, individual boards
may be more restricted and the OMAP may need to be configured to match
the board.  The PRG_SDMMC1_SPEEDCTRL bit in the OMAP3 is an example.

Signed-off-by: Jonathan Solnit <jsolnit@gmail.com>
2012-05-15 08:31:22 +02:00
Patil, Rachna
b4116ede36 ARM: AM33XX: Add i2c support
Add i2c driver board hookup for AM335X EVM

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Patil, Rachna <rachna@ti.com>
2012-01-23 11:57:31 +01:00
Chandan Nath
8a8f084e4f ARM:AM33XX: Add SPL support for AM335X EVM
This patch is added to support SPL feature on AM335X
platform. In this patch, MMC1 is configured as boot
device for SPL and support for other devices will be
added in the next patch series.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2012-01-16 08:40:12 +01:00
Chandan Nath
876bdd6d46 ARM:AM33XX: Add mmc/sd support
This patch add supports for mmc/sd driver on AM335X platform.
PLL and pinmux configurations for mmc/sd are configured in this
patch.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-01-16 08:40:12 +01:00
Chandan Nath
fb072a3ead ARM:AM33XX: Fix ddr and timer register offset
This patch is added to update incorrect ddr and timer
register offset.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-01-16 08:40:11 +01:00
Chandan Nath
5289e83a8c ARM:AM33XX: Add support for TI AM335X EVM
This patch adds basic support for booting the board.
This patch adds support for the UART necessary to
get to the u-boot prompt.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:36 +02:00
Chandan Nath
62d7fe7c91 ARM:AM33XX: Add emif/ddr support
This patch adds AM33xx emif/ddr support along with board specific
defines.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:36 +02:00
Chandan Nath
f87fa62af9 ARM:AM33XX: Add clock definitions
This patch adds basic clock definition of am33xx SoC.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:36 +02:00
Chandan Nath
5655108a82 ARM:AM33XX: Added support for AM33xx
This patch adds basic support for AM33xx which is based on ARMV7
Cortex A8 CPU.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:36 +02:00