Tom Rini a74f0c7cb5 am33xx: Correct and clean up ddr_regs struct ... The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry. Correct this by documenting a missing register that will be used at some point in the future (when write leveling is supported). Further, the cmdNcs{force,delay} fields are undocumented and we have been setting them to zero, remove. Next, setting of the 'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the ddr_data entries, so program it there. Finally, comment on how we are configuring the DATA1 registers that correspond to the DATA0 (dt0) registers defined in the struct. Signed-off-by: Tom Rini <trini@ti.com>		2012-09-01 14:58:13 +02:00
..
board.c	am33xx: Pass to config_ddr the type of memory that is connected	2012-09-01 14:58:12 +02:00
clock.c	am33xx: Move the call to ddr_pll_config, make it take the frequency	2012-09-01 14:58:12 +02:00
config.mk	ARM:AM33XX: Add SPL support for AM335X EVM	2012-01-16 08:40:12 +01:00
ddr.c	am33xx: Correct and clean up ddr_regs struct	2012-09-01 14:58:13 +02:00
emif4.c	am33xx: Correct and clean up ddr_regs struct	2012-09-01 14:58:13 +02:00
Makefile	ARM:AM33XX: Add SPL support for AM335X EVM	2012-01-16 08:40:12 +01:00
sys_info.c	ARM:AM33XX: Added support for AM33xx	2011-10-27 21:56:36 +02:00