u-boot/arch/arm/cpu/armv7/am33xx
Mark Jackson 296de3bbec Initialise correct GPMC WAITx irq for AM33xx
Currently WAIT0 irq is reset and then WAIT1 irq is enabled.
Fix it such that WAIT0 irq is enabled instead.

Signed-off-by: Mark Jackson <mpfj@newflow.co.uk>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-03-22 10:57:00 -04:00
..
board.c omap_hsmmc: add driver check for write protection 2013-03-08 16:41:13 -05:00
clock.c Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-01-08 13:15:45 +01:00
config.mk am33xx: Add SPI SPL as an option 2012-10-25 11:30:50 -07:00
ddr.c am33xx: Update DDR3 EMIF configuration sequence 2013-03-08 16:41:12 -05:00
elm.c am33xx: add ELM support 2012-12-10 08:54:02 -07:00
emif4.c am33xx: support board specific ddr settings 2012-10-25 11:31:38 -07:00
Makefile am33xx: add ELM support 2012-12-10 08:54:02 -07:00
mem.c Initialise correct GPMC WAITx irq for AM33xx 2013-03-22 10:57:00 -04:00
mux.c am33xx: move generic parts of pinmux handling out from board/ti/am335x 2012-10-25 11:31:37 -07:00
sys_info.c ARM:AM33XX: Added support for AM33xx 2011-10-27 21:56:36 +02:00
u-boot-spl.lds Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-03-18 14:37:18 -04:00