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1e7e374b35
The original write to sdram_config is correct for DDR3 but incorrect
for DDR2 so SPL was hanging. For DDR2, the write to sdram_config
should be after the writes to ref_ctrl. This was working for DDR3
because there was a write of 0x2800 to ref_ctrl before a write
to sdram_config.
Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3),
Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3)
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
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| .. | ||
| board.c | ||
| clock.c | ||
| config.mk | ||
| ddr.c | ||
| elm.c | ||
| emif4.c | ||
| Makefile | ||
| mem.c | ||
| mux.c | ||
| sys_info.c | ||
| u-boot-spl.lds | ||