- make highboot configurations use environment at high end, too,
to avoid flash fragmentation
- always use redundand environment
- don't enable video code for modules without graphics controller
- provide useful (though different) mtdparts settings
- get rid of CONFIG_CS_AUTOCONF which was always set anyway
* Extend mkconfig tool to print more useful target name
Hint: the CPLD on the TQM5200 must be programmed with a software
version supporting the high boot option! The new TQM5200S is
already supporting this option. On the TQM5200 this option will be
supported in configurations with MPC5200 rev B processors.
To actually "high boot", set jumper X30 on the STK52xx.
Patch by Martin Krause, 12 Jul 2006
- Support for TQM5200S (short version without graphic controller)
- Support for modules with 'N' type S29GL128N Spansion flashes
(requires changes to flash layout)
- Support for MPC5200B cpu (mostly support for second SDRAM bank)
The PS/2 keyobard driver for the TQM85xx modules only supports the
internal DUART of the MPC85xx CPU. Since the MPC8560 doesn't
include a DUART, the TQM8560 modules can't be used with the PS/2
keyboard controller on the STK85xx board.
The PS/2 keyboard driver should work with the modules TQM8540,
TQM8541 and TQM8555, but it only has been tested on a TQM8540, yet.
Make sure the PS/2 controller on the STK85xx is programmed. Jumper
settings: X66 1-2, 9-10; X61 2-3
Patch by Martin Krause, 21 Jun 2006
- increase CFG_FLASH_ERASE_TOUT from 2 to 15 seconds
- use CFG_FLASH_WRITE_TOUT for programming instead of CFG_FLASH_ERASE_TOUT
- remove "Unlock Bypass" mode, because macronix flashes do not support
this mode officially
- fix flash reset command from 0x00FF to 0x00F0. 0x00FF is only specified
for Intel compatible flashes, not for AMD compatible.
Patch by Martin Krause, 15 Feb 2006
The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module
integrated in a little aluminium case.
Patch by Martin Krause, 8 Jun 2006
Some code cleanup
Added code for reading and writing Mac addresses to/from ID EEPROM(0x57).
With attached patch, we can use command "mac/mac read/mac save/"
to read and write EEPROM under u-boot prompt.
U-boot will calculate the checksum of EEPROM while bootup,
if it is right, then u-boot will check whether the mac address
of eTSEC0/1/2/3 is availalbe (non-zero).
If there is mac address availabe in EEPROM, u-boot will use it,
otherewise, u-boot will use the mac address defined in
MPC8641HPCN.h. This matches the requirement to set unique mac address
for each TSEC port.
Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
* Added comments and a printf to warn that PCI-X won't
work at 33MHz
Patch by Andy Fleming 17-Mar-2006
Signed-off-by: Andy Fleming <afleming@freescale.com>
Patch by Martin Krause, 07 Nov 2005
Tested on a STK85XX baseboard. Make sure the PS/2 controller
has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3
Make the automatic CS configuration the default.
The dedicated configurations CONFIG_TQM5200_AA, CONFIG_TQM5200_AB
and CONFIG_TQM5200_AC are removed.
"TQM5200_config" is now the default for STK52XX.200 base boards.
On a STK52XX.100 base board "TQM5200_STK100_config" must be used.
Patch by Martin Krause, 07 Nov 2005
- Add IXP4xx NPE ethernet MAC support
- Add support for Intel IXDPG425 board
- Add support for Prodrive PDNB3 board
- Add IRQ support
Patch by Stefan Roese, 23 May 2006
[This patch does not include cpu/ixp/npe/IxNpeMicrocode.c which still
sufferes from licensing issues. Blame Intel.]
- Fix OMAP support that omap5912osk compiles in current source tree
- Update with code from "http://omap.spectrumdigital.com/osk5912"
to fix problems with DDR initialization
- Fix timer setup
- Use CFI flash driver and support complete 32MB of onboard flash
- Add "print_cpuinfo()" and "checkboard()" functions to display
CPU (with frequency) and Board infos
Patch by Stefan Roese, 10 May 2006
Enable the CFI driver.
Remove bogus LAWBAR7 cruft.
Use correct TEXT_BASE, Fixup load script.
Enable SPD EEPROM during DDR setup.
Use generic RFC 1918 IP addresses by default.
- Removed MPC8349ADS port
- Added PCI support to MPC8349ADS
- reworked memory map to allow mapping of all regions with BATs
Patch by Kumar Gala 20 Apr 2006
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
relocate ichache_State to ram
u-boot can run from internal flash
Add EB+MCF-EV123 board support.
Add m68k Boards to MAKEALL
Patch from Jens Scharsig, 08 Aug 2005
- Fix dbau1x00 boards broken by dbau1550 patch
PLL:s were not set for boards other than 1550.
Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST.
Default boot is now bootp for cards other than 1550.
Patch by Thomas Lange Aug 10 2005
- Add Intel legacy lock/unlock support to common CFI driver
On some Intel flash's (e.g. Intel J3) legacy unlocking is
supported, meaning that unlocking of one sector will unlock
all sectors of this bank. Using this feature, unlocking
of all sectors upon startup (via env var "unlock=yes") will
get much faster.
- Fixed problem with multiple reads of envronment variable
"unlock" as pointed out by Reinhard Arlt & Anders Larsen.
- Removed unwanted linefeeds from "protect" command when
CFG_FLASH_PROTECTION is enabled.
- Changed p3p400 board to use CFG_FLASH_PROTECTION
Patch by Stefan Roese, 01 Apr 2006
* Changes/fixes for drivers/cfi_flash.c:
- Correctly handle the cases where CFG_HZ != 1000 (several
XScale-based boards)
- Fix the timeout calculation of buffered writes (off by a
factor of 1000)
Patch by Anders Larsen, 31 Mar 2006
405 SDRAM: - The SDRAM parameters can now be defined in the board
config file and the 405 SDRAM controller values will
be calculated upon bootup (see PPChameleonEVB).
When those settings are not defined in the board
config file, the register setup will be as it is now,
so this implementation should not break any current
design using this code.
Thanks to Andrea Marson from DAVE for this patch.
440 DDR: - Added function sdram_tr1_set to auto calculate the
TR1 value for the DDR.
- Added ECC support (see p3p440).
Patch by Stefan Roese, 17 Mar 2006
- Use correct flash sector size
- Use correct memory test end address
- Add support for bzip2 compression
- Various small fixes
Patch by Yuli Barcohen, 05 Jun 2005
- Fix SDRAM timing on both local bus and 60x bus
- Add support for second flash bank (SIMM)
- Change boot flash base
Patch by Yuli Barcohen, 05 Jun 2005
* For READ_STATUS and READID commands always 8 bytes need to be read from
NDDB. Otherwise they stay there and get send to flash as the first data
word when writing.
* In nand_base.c the oob variable is not reset so this->oob_buf is
overwritten what eventually screws up the bad block descriptor table.
code and in SoC code). Boards using the old way have CFG_NAND_LEGACY and
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a added. Build breakage for
NETTA.ERR and NETTA_ISDN - will go away when the new NAND support is
implemented for these boards.
* Debug message can be turned on and off.
* Waiting for events now times out.
* Implemented RESET command.
* Added appropriate nand_bbt_descriptor and nand_oobinfo.
Remaining Problems:
* Read Status still behaves weird an returns invalid stuff sometimes.
* ECC Placement does not respect our scheme in nand_oobinfo.
CONFIG_OF_HAS_BD_T will put a copy of the bd_t
into the resulting flat device tree.
CONFIG_OF_HAS_UBOOT_ENV will copy the environment
variables from u-boot into the flat device tree
Patch by Kumar Gala 11 Jan 2006
- Support for TQM8541/8555 boards added.
- Complete rework of TQM8540/8560 support.
- Common TQM85xx code now supports all current TQM85xx platforms
(TQM8540/8541/8555/8560).
- DDR SDRAM size detection added.
- CAS latency default values can be overwritten by setting "serial#"
to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used.
If problems are detected with this non default CAS latency,
the defualt values will be used instead.
- FLASH size detection added.
- Moved FCC ethernet driver initialization behind TSEC driver init
-> TSEC is first device.
Patch by Stefan Roese, 30 Nov 2005
On PPC44x platforms, the startup message generated in "cpu.c" only
comprised the ppc type and revision but not additional informations
like speed etc. Those speed infos where printed in the board specific
code. This new implementation now prints all CPU infos in the common
cpu specific code. No board specific code is needed anymore and
therefore removed from all current 44x implementations.
Patch by Stefan Roese, 27 Nov 2005
- Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c
- CFG_FLASH_QUIET_TEST added to use the common CFI driver
for bank autodetection
Patch by Stefan Roese, 22 Nov 2005
