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Add PCI support for the TQM834x board.

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This commit is contained in:
Rafal Jaworowski 2005-10-17 02:39:53 +02:00
parent 326bf40fb7
commit 6902df56a0
13 changed files with 280 additions and 353 deletions
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2
CHANGELOG
View file

@ -2,6 +2,8 @@
Changes for U-Boot 1.1.4:
======================================================================
* Add PCI support for the TQM834x board.
* Add fat & ext2 support to AMCC 440EP boards Yosemite & Bamboo.
Fix identation on ext2ls help entry.
Patch by Stefan Roese, 14 Oct 2005

2
board/tqm834x/Makefile
View file

@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o
OBJS = $(BOARD).o pci.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)

220
board/tqm834x/pci.c Normal file
View file

@ -0,0 +1,220 @@
/*
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <asm/mmu.h>
#include <common.h>
#include <pci.h>
#ifdef CONFIG_PCI
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_tqm834x_config_table[] = {
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_IDSEL_NUMBER, PCI_ANY_ID,
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
}
},
{}
};
#endif
static struct pci_controller pci1_hose = {
#ifndef CONFIG_PCI_PNP
config_table:pci_tqm834x_config_table,
#endif
};
/**************************************************************************
* pci_init_board()
*
* NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
* per TQM834x design physical connections to external devices (PCI sockets)
* are routed only to the PCI1 we do not account for the second one - this code
* supports PCI1 module only. Should support for the PCI2 be required in the
* future it needs a separate pci_controller structure (above) and handling -
* please refer to other boards' implementation for dual PCI host controllers,
* for example board/Marvell/db64360/pci.c, pci_init_board()
*
*/
void
pci_init_board(void)
{
volatile immap_t * immr;
volatile clk8349_t * clk;
volatile law8349_t * pci_law;
volatile pot8349_t * pci_pot;
volatile pcictrl8349_t * pci_ctrl;
volatile pciconf8349_t * pci_conf;
u16 reg16;
u32 reg32;
struct pci_controller * hose;
immr = (immap_t *)CFG_IMMRBAR;
clk = (clk8349_t *)&immr->clk;
pci_law = immr->sysconf.pcilaw;
pci_pot = immr->ios.pot;
pci_ctrl = immr->pci_ctrl;
pci_conf = immr->pci_conf;
hose = &pci1_hose;
/*
* Configure PCI controller and PCI_CLK_OUTPUT
*/
/*
* WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
* line actually used for clocking all external PCI devices in TQM83xx.
* Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
* unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
* are known to hang the board; this issue is under investigation
* (13 oct 05)
*/
reg32 = OCCR_PCICOE1;
#if 0
/* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
reg32 = 0xff000000;
#endif
if (clk->spmr & SPMR_CKID) {
/* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
* fields accordingly */
reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
| OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
| OCCR_PCICD6 | OCCR_PCICD7);
}
clk->occr = reg32;
udelay(2000);
/*
* Release PCI RST Output signal
*/
pci_ctrl[0].gcr = 0;
udelay(2000);
pci_ctrl[0].gcr = 1;
udelay(2000);
/*
* Configure PCI Local Access Windows
*/
pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_TRGT_IF_PCI1 | LAWAR_SIZE_512M;
pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_TRGT_IF_PCI1 | LAWAR_SIZE_16M;
/*
* Configure PCI Outbound Translation Windows
*/
/* PCI1 mem space */
pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
/* PCI1 IO space */
pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
/*
* Configure PCI Inbound Translation Windows
*/
/* we need RAM mapped to PCI space for the devices to
* access main memory */
pci_ctrl[0].pitar1 = 0x0;
pci_ctrl[0].pibar1 = 0x0;
pci_ctrl[0].piebar1 = 0x0;
pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_IWS_256M;
hose->first_busno = 0;
hose->last_busno = 0xff;
/* PCI memory space */
pci_set_region(hose->regions + 0,
CFG_PCI1_MEM_BASE,
CFG_PCI1_MEM_PHYS,
CFG_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* PCI IO space */
pci_set_region(hose->regions + 1,
CFG_PCI1_IO_BASE,
CFG_PCI1_IO_PHYS,
CFG_PCI1_IO_SIZE,
PCI_REGION_IO);
/* System memory space */
pci_set_region(hose->regions + 2,
CONFIG_PCI_SYS_MEM_BUS,
CONFIG_PCI_SYS_MEM_PHYS,
CONFIG_PCI_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
hose->region_count = 3;
pci_setup_indirect(hose,
(CFG_IMMRBAR+0x8300),
(CFG_IMMRBAR+0x8304));
pci_register_hose(hose);
/*
* Write to Command register
*/
reg16 = 0xff;
pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
&reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
reg16);
/*
* Clear non-reserved bits in status register.
*/
pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
0xffff);
pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
0x80);
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
/*
* Hose scan.
*/
hose->last_busno = pci_hose_scan(hose);
}
#endif /* CONFIG_PCI */

50
board/tqm834x/tqm834x.c
View file

@ -30,10 +30,7 @@
#include <spd.h>
#include <miiphy.h>
#include <asm-ppc/mmu.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
#define IOSYNC asm("eieio")
#define ISYNC asm("isync")
@ -145,36 +142,31 @@ int checkboard (void)
puts("Board: TQM834x\n");
#ifdef CONFIG_PCI
printf("PCI1: 32 bit, %d MHz (compiled)\n",
CONFIG_SYS_CLK_FREQ / 1000000);
#else
printf("PCI1: disabled\n");
#endif
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t * immr;
u32 w, f;
immr = (immap_t *)CFG_IMMRBAR;
if (!(immr->reset.rcwh & RCWH_PCIHOST)) {
printf("PCI: NOT in host mode..?!\n");
return 0;
}
/* get bus width */
w = 32;
if (immr->reset.rcwh & RCWH_PCI64)
w = 64;
/* get clock */
f = gd->pci_clk;
printf("PCI1: %d bit, %d MHz\n", w, f / 1000000);
#else
printf("PCI: disabled\n");
#endif
return 0;
}
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found
*/
/* FIXME: No PCI support */
#endif /* CONFIG_PCI */
/**************************************************************************
* pci_init_board()
*/
void
pci_init_board(void)
{
#ifdef CONFIG_PCI
extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
pci_mpc83xx_init(hose);
#endif /* CONFIG_PCI */
}
/**************************************************************************
*

1
cpu/mpc83xx/Makefile
View file

@ -32,7 +32,6 @@ COBJS = traps.o \
cpu_init.o \
speed.o \
interrupts.o \
pci.o \
i2c.o \
spd_sdram.o

4
cpu/mpc83xx/cpu.c
View file

@ -60,7 +60,9 @@ int checkcpu(void)
puts("Rev: Unknown\n");
return -1; /* Not sure what this is */
}
printf("Rev: %02x at %s MHz\n",pvr & 0x0000FFFF, strmhz(buf, clock));
printf("Rev: %d.%d at %s MHz\n", (pvr & 0xf0) >> 4,
(pvr & 0x0f), strmhz(buf, clock));
return 0;
}

252
cpu/mpc83xx/pci.c
View file

@ -1,252 +0,0 @@
/*
* Copyright 2004 Freescale Semiconductor.
* Copyright (C) 2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Change log:
*
* 20050101: Eran Liberty (liberty@freescale.com)
* Initial file creating (porting from 85XX & 8260)
*/
/*
* PCI Configuration space access support for MPC85xx PCI Bridge
*/
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
#include <pci.h>
#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
#include <asm/i2c.h>
#endif
#if defined(CONFIG_PCI)
void
pci_mpc83xx_init(volatile struct pci_controller *hose)
{
volatile immap_t * immr;
volatile clk8349_t * clk;
volatile law8349_t * pci_law;
volatile pot8349_t * pci_pot;
volatile pcictrl8349_t * pci_ctrl;
volatile pciconf8349_t * pci_conf;
u8 val8,tmp8,ret;
u16 reg16,tmp16;
u32 val32,tmp32;
immr = (immap_t *)CFG_IMMRBAR;
clk = (clk8349_t *)&immr->clk;
pci_law = immr->sysconf.pcilaw;
pci_pot = immr->ios.pot;
pci_ctrl = immr->pci_ctrl;
pci_conf = immr->pci_conf;
/*
* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
*/
val32 = clk->occr;
udelay(2000);
clk->occr = 0xff000000;
udelay(2000);
/*
* Configure PCI Local Access Windows
*/
pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
/*
* Configure PCI Outbound Translation Windows
*/
pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
/* mapped to PCI1 IO space 0x0 to local 0xe2000000 */
pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK);
/* mapped to PCI2 IO space 0x0 to local 0xe3000000 */
pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
/*
* Configure PCI Inbound Translation Windows
*/
pci_ctrl[0].pitar1 = 0x0;
pci_ctrl[0].pibar1 = 0x0;
pci_ctrl[0].piebar1 = 0x0;
pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
pci_ctrl[1].pitar1 = 0x0;
pci_ctrl[1].pibar1 = 0x0;
pci_ctrl[1].piebar1 = 0x0;
pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
/*
* Assign PIB PMC slot to desired PCI bus
*/
#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE);
#endif
val8 = 0;
ret = i2c_write(0x23,0x6,1,&val8,1);
ret = i2c_write(0x23,0x7,1,&val8,1);
val8 = 0xff;
ret = i2c_write(0x23,0x2,1,&val8,1);
ret = i2c_write(0x23,0x3,1,&val8,1);
val8 = 0;
ret = i2c_write(0x26,0x6,1,&val8,1);
val8 = 0x34;
ret = i2c_write(0x26,0x7,1,&val8,1);
#if defined(PCI_64BIT)
val8 = 0xf4; /* PMC2<->PCI1 64bit */
#elif defined(PCI_ALL_PCI1)
val8 = 0xf3; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit */
#elif defined(PCI_ONE_PCI1)
val8 = 0xf9; /* PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit */
#elif defined(PCI_TWO_PCI1)
val8 = 0xf5; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit */
#else
val8 = 0xf5;
#endif
ret = i2c_write(0x26,0x2,1,&val8,1);
val8 = 0xff;
ret = i2c_write(0x26,0x3,1,&val8,1);
val8 = 0;
ret = i2c_write(0x27,0x6,1,&val8,1);
ret = i2c_write(0x27,0x7,1,&val8,1);
val8 = 0xff;
ret = i2c_write(0x27,0x2,1,&val8,1);
val8 = 0xef;
ret = i2c_write(0x27,0x3,1,&val8,1);
asm("eieio");
/*
* Release PCI RST Output signal
*/
udelay(2000);
pci_ctrl[0].gcr = 1;
#ifndef PCI_64BIT
pci_ctrl[1].gcr = 1;
#endif
udelay(2000);
hose[0].first_busno = 0;
hose[0].last_busno = 0xff;
pci_set_region(hose[0].regions + 0,
CFG_PCI1_MEM_BASE,
CFG_PCI1_MEM_PHYS,
CFG_PCI1_MEM_SIZE,
PCI_REGION_MEM);
pci_set_region(hose[0].regions + 1,
CFG_PCI1_IO_BASE,
CFG_PCI1_IO_PHYS,
CFG_PCI1_IO_SIZE,
PCI_REGION_IO);
hose[0].region_count = 2;
pci_setup_indirect(&hose[0],
(CFG_IMMRBAR+0x8300),
(CFG_IMMRBAR+0x8304));
#define PCI_CLASS_BRIDGE 0x06
reg16 = 0xff;
tmp32 = 0xffff;
pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
/*
* Clear non-reserved bits in status register.
*/
pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
#ifndef PCI_64BIT
hose[1].first_busno = 0;
hose[1].last_busno = 0xff;
pci_set_region(hose[1].regions + 0,
CFG_PCI2_MEM_BASE,
CFG_PCI2_MEM_PHYS,
CFG_PCI2_MEM_SIZE,
PCI_REGION_MEM);
pci_set_region(hose[1].regions + 1,
CFG_PCI2_IO_BASE,
CFG_PCI2_IO_PHYS,
CFG_PCI2_IO_SIZE,
PCI_REGION_IO);
hose[1].region_count = 2;
pci_setup_indirect(&hose[1],
(CFG_IMMRBAR+0x8380),
(CFG_IMMRBAR+0x8384));
pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
/*
* Clear non-reserved bits in status register.
*/
pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
#endif
#if defined(PCI_64BIT)
printf("PCI1 64bit on PMC2\n");
#elif defined(PCI_ALL_PCI1)
printf("PCI1 32bit on PMC1 & PMC2 & PMC3\n");
#elif defined(PCI_ONE_PCI1)
printf("PCI1 32bit on PMC1,PCI2 32bit on PMC2 & PMC3\n");
#else
printf("PCI1 32bit on PMC1 & PMC2 & PMC3 in default\n");
#endif
#if 1
/*
* Hose scan.
*/
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
#endif
}
#endif /* CONFIG_PCI */

1
cpu/mpc83xx/speed.c
View file

@ -329,6 +329,7 @@ int get_clocks (void)
gd->lbiu_clk = lbiu_clk ;
gd->lclk_clk = lclk_clk ;
gd->ddr_clk = ddr_clk ;
gd->pci_clk = pci_sync_in;
gd->cpu_clk = gd->core_clk;
gd->bus_clk = gd->lbiu_clk;

2
drivers/pci.c
View file

@ -142,7 +142,7 @@ struct pci_controller *pci_bus_to_hose (int bus)
if (bus >= hose->first_busno && bus <= hose->last_busno)
return hose;
debug ("pci_bus_to_hose() failed\n");
printf("pci_bus_to_hose() failed\n");
return NULL;
}

13
drivers/pci_auto.c
View file

@ -319,7 +319,18 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
PCI_DEV(dev));
break;
#endif
#ifdef CONFIG_MPC834X
case PCI_CLASS_BRIDGE_OTHER:
/*
* The host/PCI bridge 1 seems broken in 8349 - it presents
* itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
* device claiming resources io/mem/irq.. we only allow for
* the PIMMR window to be allocated (BAR0 - 1MB size)
*/
DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
break;
#endif
default:
pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
break;

1
include/asm-ppc/global_data.h
View file

@ -62,6 +62,7 @@ typedef struct global_data {
u32 lbiu_clk;
u32 lclk_clk;
u32 ddr_clk;
u32 pci_clk;
#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;

37
include/asm-ppc/immap_83xx.h
View file

@ -28,43 +28,6 @@ typedef struct law8349 {
#define LAWBAR_BAR 0xFFFFF000
#define LAWBAR_RES ~(LAWBAR_BAR)
u32 ar; /* LBIU local access window attribute register */
/*
* This Macro were moved into mmu.h
*/
#if 0
/* 0 The local bus local access window n is disabled. 1 The local bus
* local access window n is enabled and other LBLAWAR0 and LBLAWBAR0 fields
* combine to identify an address range for this window.
*/
#define LAWAR_EN 0x80000000
/* Identifies the size of the window from the starting address. Window
* size is 2^(SIZE+1) bytes. 000000–001010Reserved. Window is
* undefined.
*/
#define LAWAR_SIZE 0x0000003F
#define LAWAR_SIZE_4K 0x0000000B
#define LAWAR_SIZE_8K 0x0000000C
#define LAWAR_SIZE_16K 0x0000000D
#define LAWAR_SIZE_32K 0x0000000E
#define LAWAR_SIZE_64K 0x0000000F
#define LAWAR_SIZE_128K 0x00000010
#define LAWAR_SIZE_256K 0x00000011
#define LAWAR_SIZE_512K 0x00000012
#define LAWAR_SIZE_1M 0x00000013
#define LAWAR_SIZE_2M 0x00000014
#define LAWAR_SIZE_4M 0x00000015
#define LAWAR_SIZE_8M 0x00000016
#define LAWAR_SIZE_16M 0x00000017
#define LAWAR_SIZE_32M 0x00000018
#define LAWAR_SIZE_64M 0x00000019
#define LAWAR_SIZE_128M 0x0000001A
#define LAWAR_SIZE_256M 0x0000001B
#define LAWAR_SIZE_512M 0x0000001C
#define LAWAR_SIZE_1G 0x0000001D
#define LAWAR_SIZE_2G 0x0000001E
#define LAWAR_RES ~(LAWAR_EN|LAWAR_SIZE)
#endif
} law8349_t;
/*

48
include/configs/TQM834x.h
View file

@ -122,6 +122,7 @@ extern int tqm834x_num_flash_banks;
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
/* disable remaining mappings */
@ -241,7 +242,7 @@ extern int tqm834x_num_flash_banks;
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_MULTI
#endif
#define CONFIG_MPC83XX_TSEC1 1
@ -262,45 +263,32 @@ extern int tqm834x_num_flash_banks;
* General PCI
* Addresses are mapped 1-1.
*/
/* FIXME: Real PCI support will come in a follow-up update. */
#undef CONFIG_PCI
#define CONFIG_PCI
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
#define CFG_PCI2_MEM_BASE 0xA0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI2_IO_BASE 0x00000000
#define CFG_PCI2_IO_PHYS 0xe3000000
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
#if defined(CONFIG_PCI)
#define PCI_ALL_PCI1
#if defined(PCI_64BIT)
#undef PCI_ALL_PCI1
#undef PCI_TWO_PCI1
#undef PCI_ONE_PCI1
#endif
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
/* PCI1 host bridge */
#define CFG_PCI1_MEM_BASE 0xc0000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0xe2000000
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xFIXME
#define PCI_ENET0_MEMADDR 0xFIXME
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE
#define PCI_ENET0_MEMADDR CFG_PCI1_MEM_BASE
#define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif /* CONFIG_PCI */
@ -418,7 +406,7 @@ extern int tqm834x_num_flash_banks;
HRCWH_PCI_HOST |\
HRCWH_32_BIT_PCI |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_PCI2_ARBITER_ENABLE |\
HRCWH_PCI2_ARBITER_DISABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\