This adds basic BayTrail platform ASL files. They are intended to be
included in dsdt.asl of any board that is based on this platform.
Note: ACPI mode support for GPIO/LPSS/SCC/LPE are not supported for
now. They will be added in the future.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Like other MADT table write routines, make acpi_create_madt_lapics()
return how many bytes it has written instead of the table end addr.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds several generic ASL libraries that can be included by
other ASL files, which are:
- debug.asl: for debug output using POST I/O port and legacy serial port
- globutil.asl: for string compare routines
- statdef.asl: for _STA status values
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The comment of initializing table header revision says:
/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
which might mislead it may increase per ACPI spec revision.
However this is not the case. It's actually a fixed number
as defined in ACPI spec, and in the laest ACPI spec 6.1,
some table header revisions are still 1. Clean these up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Per ACPI spec, the FACS table address must be aligned to a 64 byte
boundary (Windows checks this, but Linux does not).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use u32 instead of unsigned long in the table write routines, as
other routines do.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rearrange the routine order a little bit, to follow the order
in which ACPI table is defined in acpi_table.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rename fill_header() to acpi_fill_header() for consistency.
Change its signature to remove the 'length' parameter and
make it a public API.
Also remove the unnecessary include files, and improve the
AmlCode[] comment a little bit.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This acpi_create_ssdt_generator() currently does nothing.
Remove this for now.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reorder the ACPI tables appearance by following the order:
RSDP, RSDT, XSDT, FADT, FACS, MADT, MCFG. And adjust the
table flag defines accordingly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
- Use "U-BOOT" and "U-BOOTBL" for the OEM ID and OEM table ID.
- Do not typedef acpi_header_t, instead use struct acpi_table_hader.
- Use a shorter name aslc_id and aslc-revision.
- Change MCFG base address to use 32-bit value pairs (_l and _h).
- Apply ACPI_APIC_ prefix to MADT APIC type macros and make
their names to be more readable.
- Apply __packed to struct acpi_madt_irqoverride and struct
acpi_madt_lapic_nmi tables, as they are not naturally aligned
by the compiler which leads to wrong sizeof(struct).
- Rename model to res1 as it is reserved after ACPI spec 1.0.
- Apply ACPI_ prefix to the PM profile macros and change them
to enum.
- Add ospm_flags to FACS structure which is defined since ACPI 4.0.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
- Remove #include <> header files.
- Remove APM_CNT register defines, which should not be here as
they are SMI related.
- Remove MP_IRQ_ defines as they are duplicates of the same ones
in asm/mpspec.h.
- Remove ACTL register defines, which should not be here as they
are chipset specific.
- Remove functional fixed hardware defines, which are not used.
- Remove dev_scope related defines, which are not used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This updates all x86 boards that currently have IRQ router in the
dts files to include ACTL register details.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
By default SCI is disabled after power on. ACTL is the register to
enable SCI and route it to PIC/APIC. To support both ACPI in PIC
mode and APIC mode, configure SCI to use IRQ9.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reserve IRQ9 which is to be used as SCI interrupt number
for ACPI in PIC mode.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fix the following two build warnings in function 'write_acpi_tables':
warning: format '%lx' expects argument of type 'long unsigned int',
but argument 2 has type 'u32' [-Wformat=]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The following build warning is seen in tables.c:
warning: implicit declaration of function 'memalign'
Add the missing header file to fix it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Remove asm/acpi.h which is never used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Both real Malta boards & QEMU's Malta emulation can feature MIPS32r6
CPUs. Allow building U-Boot for such systems by selecting
CONFIG_SUPPORTS_CPU_MIPS32_R6 for Malta.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Add support for targetting MIPS32r6 & MIPS64r6 systems, in the same way
that we currently select release 1 or release 2 targets. MIPSr6 is not
entirely backwards compatible with earlier releases of the architecture.
Some instructions are encoded differently, some are removed, some are
reused, so it is not practical to run U-Boot built for earlier revisions
on a MIPSr6 system. Update their Kconfig help text to reflect that.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Rather than having the values for CONFIG_SYS_CPU depend upon each
architecture revision, have them depend upon the more general
CONFIG_CPU_MIPS32 & CONFIG_CPU_MIPS64 which in turn depend upon the
architecture revisions.
This is done in preparation for adding MIPSr6 support, which would
otherwise need to introduce new cases here.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
In MIPS assembly there have historically been 2 variants of immediate
addition - the standard "addi" which traps if an overflow occurs, and
the unchecked "addiu" which does not trap on overflow. In release 6 of
the MIPS architecture the trapping variants of immediate addition &
subtraction have been removed. In preparation for supporting MIPSr6,
stop using the trapping instructions from assembly & switch to their
unchecked variants.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Add support for the TPLink WDR4300 router, which is based on the
AR9344 MIPS 74Kc CPU and has 128 MiB of RAM. The USB is supported
on this system as well.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
Add support for the Atheros AR934x WiSoCs. This patchs adds complete
system init, including PLL and DRAM init, both of which happen from
full C environment, since the AR934x has proper SRAM.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
Add code to ungate the ethernet controller on ar933x and ar934x .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
Add node for both ethernet controllers in the ar933x.
The PHY is attached only to the first ethernet controller.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
Add code to ungate the USB controller on ar933x and ar934x .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
Add generic EHCI node for the ChipIdea EHCI controller in the ath79.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
The assignment const T var; var = value; is illegal, since var is
constant. Drop the const to fix the compiler warning.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
The indent in this file triggers my OCD, so fix it. Replace multiple
spaces with tabs and align the values in one column.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
There really is zero reason for including netdev.h in generic mips CPU code.
Removing the netdev.h from cpu.c also fixes the following compiler warning:
In file included from arch/mips/cpu/cpu.c:10:0:
include/netdev.h:204:41: warning: 'struct eth_device' declared inside parameter list [enabled by default]
int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int));
^
include/netdev.h:204:41: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch add board-level code and base DT for AP143.
Signed-off-by: Wills Wang <wills.wang@live.com>
[updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch add board-level code and base DT for AP121.
Signed-off-by: Wills Wang <wills.wang@live.com>
[updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch add some common code for QCA/Atheros ath79 SOCs such as
DDR tuning, chip reset and CPU detection.
Signed-off-by: Wills Wang <wills.wang@live.com>
Commit ac337168a unified functions to flush and invalidate dcache by
range. These two functions were no-op for SoCs other than 4xx and
MPC86xx. Adding these functions seemed to be correct but introduced
issues when the dcache is flushed. While the root cause is under
investigation, disable these functions for affected SoCs so various
drivers can work.
Signed-off-by: York Sun <york.sun@nxp.com>
During DDR-2133 operation, the transmit data eye margins determined
during the memory controller initialization may be sub-optimal, set
DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For SoCs that contain multiple SEC engines, each of them needs
to be initialized (by means of initializing among others the
random number generator).
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Some SOCs, specifically the ones in the C29x familiy can have
multiple security engines. This patch adds a system configuration
define which indicates the maximum number of SEC engines that
can be found on a SoC.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Freescale PPC SoCs do not hard-code security engine's Job Ring 0
address, rather a define is used. This patch adds the same
functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts)
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
MMCSD_MODE_FAT has been renamed to MMCSD_MODE_FS by commit 205b4f33.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
MMCSD_MODE_FAT has be renmaed to MMCSD_MODE_FS by commit 205b4f33.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
init_early_memctl_regs() is also be called in board_early_init_f().
So remove the duplicated call in spl code.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As the issue about the stack will get corrupted when switching between
the early and final mmu tables is fixed by commit 70e21b064, the
workaround to flush dcache is unnecessary and should be removed.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The address value and size value set for QSPI dts node "reg"
property have type of u64 on arm64.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For Qoriq PPC&ARM v7 platforms, the crypto node is being fixup'ed in
order to update the SEC internal version (aka SEC ERA). This patch
adds the same functionality to the ARMv8 SoCs.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The initial training for the DDRC may provide results that are not
optimized. The workaround provides better read timing margins.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This option currently enables both the command and the SCSI functionality.
Rename the existing option to CONFIG_SCSI since most of the code relates
to the feature.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add outsw() and insw() functions for sandbox, as these are needed by the IDE
code. The functions will not do anything useful if called, but allow the
code to be compiled.
Also add out16() and in16(), required by systemace.
Signed-off-by: Simon Glass <sjg@chromium.org>
This started as 'ahci' and was renamed to 'disk' during code review. But it
seems that this is too generic. Now that we have a 'blk' uclass, we can use
that as the generic piece, and revert to ahci for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
1. Support compatible string "spi-gpio" which is used by Linux
Linux use different bindings, so use UBOOT_COMPAT and
LINUX_COMPAT to differentiate them.
2. Introduce SPI_MASTER_NO_RX and SPI_MASTER_NO_TX to handle
no rx or no tx case.
3. Tested on i.MX6 UltraLite board with 74LV595 spi-gpio chip.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This prevents the following boot-time message on any board where only the
first DC is in use, yet the DC's DT node is enabled:
stdio_add_devices: Video device failed (ret=-22)
(This happens on at least Harmony, Ventana, and likely any other Tegra20
board with display enabled other than Seaboard).
The Tegra DC's DT node represents a display controller. It may itself
drive an integrated RGB display output, or be used by some other display
controller such as HDMI. For this reason the DC node itself is not
enabled/disabled in DT; the DC itself is considered a shared resource, not
the final (board-specific) display output. The node should instantiate a
display output driver only if the rgb subnode is enabled. Other output
drivers are free to use the DC if they are enabled and their DT node
references the DC's DT node. Adapt the Tegra display drivers' bind()
routine to only bind to the DC's DT node if the RGB subnode is enabled.
Now that the display driver does the right thing, remove the workaround
for this issue from Seaboard's DT file.
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To use serial uclass and DM, CONFIG_SYS_MALLOC_F must be used.
So CONFIG_SYS_GENERIC_GLOBAL_DATA has been undefined and
call to board_init_f_mem() is added for all cpu's.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Acked-by: Simon Glass <sjg@chromium.org>
According to the product website, the full names are i.MX 7Solo
and i.MX 7Dual, whereas the short form is i.MX7S and i.MX7D. Be
consistent and print the short form for both supported i.MX 7 SoCs.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.
While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).
Signed-off-by: Stefan Agner <stefan@agner.ch>
Several UART input selects are missing. The fourth input select
for UART2_TX_DATA_ALT0 is actually also missing in the documentation.
(at least in Rev. B of the i.MX 7Dual Reference Manual). However,
when looking at the tables of other input selects, it is very natural
that there must be an input select for the UART2_TX_DATA_ALT0 pad.
The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and
it was required to set that particular input select register to get a
working UART2.
This patch adds the IOMUX setting for using SD1_DAT5 as GPIO5:9.
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Peng Fan <van.freenix@gmail.com>
Commit bfb33f0bc4 ("sunxi: mctl_mem_matches: Add missing memory
barrier") broke compilation for the Pine64, as dram_helper.c now
includes <asm/armv7.h>, which does not compile on arm64.
Fix this by moving all barrier instructions into a separate header
file, which can easily be shared between arm and arm64.
Also extend the inline assembly to take the "sy" argument, which is
optional for ARMv7, but mandatory for v8.
This fixes compilation for 64-bit sunxi boards (Pine64).
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This is mandatory, otherwise the USB does not work.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.
"
So If L2 cache is already enabled by ROM, chaning value of ACR
will cause SLVERR and uboot hang.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
The current delays in the DDR initialization routines for am33xx
architectures are sometimes not running long enough leading to DDR
init errors. On am437x, this shows up as an L3 NOC error after the
kernel boots. This is due to the timer not being initialized
properly, but instead still containing the timer init values from
the boot ROM which cause timers to expire in 1/4th the time
required.
timer_init is typically not called until board_init_r, however on
am33xx/am43xx udelay is required in sdram_init which is called
from board_init_f, so a call to timer_init is required earlier.
Note that this issue introduced in v2015.01 by:
b352dde "am33xx: Drop timer_init call from s_init".
Although this could instead fixed by reverting said commit, it
would cause timer_init to be called twice in both SPL and non-SPL
cases. This gives a little more fine grained control and also
matches what is being done on omap-command and fsl-layerscape.
Signed-off-by: Russ Dill <russ.dill@ti.com>
Commit 724219a65f "ARM: always perform per-CPU GIC init" removed some
ifdefs to unify the MULTIENTRY-vs-non-MULTIENTRY paths. However, the
wrong endif was removed. This patch adds back that missing endif, and
adds a new ifdef to match the endif the now-correctly-terminated block
used to match against. Use "git show -U25 724219a65f55" to see enough
context to make the original issue clear.
In practical terms, this makes no difference to runtime behaviour. The
code that was incorrectly compiled into the binary when ifndef MULTIENTRY
is a no-op for other cases, since branch_if_master evaluates to a hard-
coded jump. The only issues were:
- A few extra instructions were added to the binary.
- The comment on the endif at the very end of the function, indicating
which ifdef it matched, were wrong.
An alternative might be to simply fix the comment on that trailing ifdef,
but that only addresses the second point above, not the first.
Fixes: 724219a65f ("ARM: always perform per-CPU GIC init")
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
In current Linux kernel Tegra DT files, 64-bit addresses are represented
in unit addresses as a pair of comma-separated 32-bit values. Apparently
this is no longer the correct representation for simple busses, and the
unit address should be represented as a single 64-bit value. If this is
changed in the DTs, arm/arm/mach-tegra/board2.c:ft_system_setup() will no
longer be able to find and enable the GPU node, since it looks up the node
by name.
Fix that function to enable nodes based on their compatible value rather
than their node name. This will work no matter what the node name is, i.e
for DTs both before and after any rename operation.
Cc: Thierry Reding <treding@nvidia.com>
Cc: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This reverts commit b5788dc0dd.
Ram size is incorrectly reported as 512MB on a firefly-rk3288 board
with 2GB of ram. Reverting this patch displays the full amount of ram.
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Simon Glass <sjg@chromium.org>
Unfortunately with this change we now are unable to do FS mode boots
from MMC1 as with the way the code works today we will always load and
assume that the hard-coded raw location contains U-Boot. Further, we
cannot fix this by just changing other logic to try FS-then-RAW as it
would also make us have to ignore what order the ROM is telling us to
try.
This reverts commit 22d90d560a.
Signed-off-by: Tom Rini <trini@konsulko.com>
The code in uniphier_sld3_sbc_init() is pin-muxing, so it would
be a better fit in uniphier_sld3_early_pin_init().
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The System Bus is not available by default on the ROM boot mode of
PH1-LD20. To use devices connected to the System Bus, such as the
Micro Support Card, it is necessary to set up pin-muxing and some
System Bus Controller register.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
PH1-LD20 does not have the dedicated boot swap select latch.
Instead, it is controlled from the boot mode select.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
We are running with the caches disabled when mctl_mem_matches gets called,
but the cpu's write buffer is still there and can still get in the way,
add a memory barrier to fix this.
This avoids mctl_mem_matches always returning false in some cases, which
was resulting in:
U-Boot SPL 2015.07 (Apr 14 2016 - 18:47:26)
DRAM: 1024 MiB
U-Boot 2015.07 (Apr 14 2016 - 18:47:26 +0200) Allwinner Technology
CPU: Allwinner A23 (SUN8I)
DRAM: 512 MiB
Where 512 MiB is the right amount, but the DRAM controller would be
initialized for 1024 MiB.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
ABB should be initialized for all required domains voltage domain
for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If
we do not do this, kernel configuring just the frequency using the
default boot loader configured voltage can fail on many corner lot
units and has been hard to debug. This specifically is a concern with
DRA7 generation of SoCs since other than VDD_MPU, all other domains
are only permitted to setup the voltages to required OPP only at boot.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Since we setup the voltage and frequency for the MM domain, we *must*
setup the ABB configuration needed for the domain as well. If we do not
do this, kernel configuring just the frequency using the default boot
loader configured voltage can fail on many corner lot units.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
ABB TX_DONE mask will vary depending on ABB module. For example,
3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain,
DRA7 has it on all domains with the exception of CORE, RTC.
Hence, move the txdone mask definition over to structure describing
voltage domain.
Signed-off-by: Nishanth Menon <nm@ti.com>
This information is already available under vcores->volts.efuse.reg.
There is no reason for duplicating the information since AVS Class 0
definitions are common for OMAP5 and DRA7 and defined with
STD_FUSE_OPP_* macros. This allows a central location of defining
the ABB and voltage definitions especially since they are reused.
This also makes it simpler to prevent mistakes involved when changing
the boot OPP for the device.
Signed-off-by: Nishanth Menon <nm@ti.com>
This is a binding which only exists in U-Boot, but is
required to get working serial in U-Boot.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Currently only the serial pl01x driver is using DT,
and the other drivers still use platform data but
as more DT lands in the upstream kernel the aim is
to migrate the other drivers over to DT as well to
have a fully DT configured hikey u-boot.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Import the upstream kernel dts into U-Boot. Currently
only serial is supported, but a lot more DT changes are
queued for v4.7.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This syncs up the current cmd/Kconfig and include/configs/ files with the
only exception being CMD_NAND. Due to how we have used this historically
we need to take further care here when converting.
Signed-off-by: Tom Rini <trini@konsulko.com>
PH1-LD20 does not support 1.8V signaling for SD card; only Default
Speed and High Speed (up to 50MHz) with 3.3V signaling is supported.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The current table look-up for the DTB file name turned out bothersome
in terms of maintainability; I ended up adding a new entry every time
a new board is supported.
There is a common pattern between the DT compatible string and the
corresponding file name; drop the vendor prefix "socionext," and
prefix it with "uniphier-" and suffix it with ".dtb".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
No need to stop booting U-Boot even if boot mode is unknown.
Setting the "bootmode" environment is only useful for booting
Linux Kernel. Anyway, U-Boot has already booted by this point.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
For PH1-LD20 or later, per-pin input-enable control is supported,
that is, we need to set-up IECTRL registers for a group of pins.
This helper function will be useful for a bunch of register settings.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, fdtgrep would not accept uniphier-ph1-ld20-ref.dtb
and uniphier-ph1-ld11-ref.dtb unless the aliases node comes
the first in the root node.
$ make -s uniphier_pxs2_ld6b_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld20-ref
[snip]
LDS spl/u-boot-spl.lds
LD spl/u-boot-spl
OBJCOPY spl/u-boot-spl-nodtb.bin
FDTGREP spl/u-boot-spl.dtb
Error at 'fdt_find_regions': FDT_ERR_BADLAYOUT
/aliases node must come before all other nodes
Error: FDT_ERR_BADMAGIC
make[1]: *** [spl/u-boot-spl.dtb] Error 1
make: *** [spl/u-boot-spl] Error 2
This commit moves the aliases node as the error message from the
fdtgrep tool suggests, although this requirement does not sound
reasonable to me.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Because DT properties are 4-byte aligned, the pointer access
*(fdt64_t *) in this code causes unaligned access.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Our own ACPI implementation (when CONFIG_QEMU_ACPI_TABLE is not set)
does not build anymore after x86 has been fully converted to DM PCI.
Instead of trying to fix the build errors, given we now have the ACPI
support via QEMU's fw_cfg interface, which is a more reliable way to
generate correct ACPI tables than by ourselves, hence drop our own
ACPI implementation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
flush_dcache_all() is used in the very end of U-Boot self relocation
to write back all copied and then patched code and data to their
new location in the very end of available memory space.
Since that has nothing to do with IO (i.e. no external DMA happens
here) IOC won't help here and we need to write back data cache contents
manually.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This enables full ethernet usage, including U-Boot to write the board
specific MAC address (ethaddr) into the DT blob before passing it to
Linux.
Without this, the ethaddr is not detected in U-Boot at all, resulting
in this error upon bootup:
...
Model: EBV SOCrates
Net:
Error: ethernet@ff702000 address not set.
No ethernet found.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Fix a small typo in some of the SoCFPGA dts files that has spread via
copy-and-paste.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Add support for Technexion's PICO-IMX6UL-EMMC board.
For information about this board, please visit:
http://www.technexion.com/products/pico/pico-som/pico-imx6-emmc
Signed-off-by: Richard Hu <richard.hu@technexion.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree,
the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the
ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is
generated, and the LVDS display will hang when the ipu_di_clk is sourced from
ldb_di_clk.
To fix the problem, both the new and current parent of the ldb_di_clk should
be disabled before the switch. This patch ensures that correct steps are
followed when ldb_di_clk parent is switched in the beginning of boot.
This patch was ported from the 3.10.17 NXP kernel
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.10.17_1.0.1_ga&id=eecbe9a52587cf9eec30132fb9b8a6761f3a1e6d
NXP errata number: ERR009219, EB821
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
The echo -ne "\xNN" does not work in certain bourne-compatible shells, like
dash. The recommended way of hex->char conversion is using printf(1), but
there is a pitfall here. The GNU printf does support "\xNN" format, but
according to the opengroup documentation, this is not part of POSIX. The
POSIX printf only defines "\NNN" where N is octal. Thus, for the sake of
compatibility, we use that.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
MIPS arch do not update 'reg' property of /memory node.
As a result Linux bootup will not work unless board.dts
file contains right /memory offset-size information or
board implements required memory fixup.
Fixing by renaming (unused) _arch_fixup_memory_node_ to
_arch_fixup_fdt_ in arch/mips/lib/bootm.c inline with ARM arch.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The current code in ARMv8's lowlevel_init() skips the per-CPU GIC
initialization ifndef CONFIG_ARMV8_MULTIENTRY. However, the per-CPU init
should always occur; it's just the one-time init that should only happen
on the master.
Once this consideration is taken into account, the only difference between
the paths when CONFIG_ARMV8_MULTIENTRY is undefined/defined is the use of
branch_if_slave. Naively, any unified code would need to invoke this
conditionally upon ifdef CONFIG_ARMV8_MULTIENTRY. However, branch_if_slave
already checks CONFIG_ARMV8_MULTIENTRY and does nothing if it isn't
defined, so we don't even need that ifdef at the call site.
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
commit 62c5674ea1 ("omap: SPL boot devices cleanup and completion")
cleans up the boot device ids for amx3xx soc. But mistakenly updates wrong
device IDs for AM43xx USB. Fixing the same here.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
fix 19/48 broken board compilations, due to a now too smal 16-bit
relative jump
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
As per mmc device tree binding documentation card detect gpio has
to be active low signal. When a hardware is designed with active
high card detect, gpio polarity has to be changed with
cd-inverted dt property.
In DRA72x and AM57xx EVMs the card detect gpio is designed as
active low gpio. So correcting the dt card detect gpio
definition.
Also adding card-detect gpio for DRA74x EVM.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
As per mmc device tree binding documentation card detect gpio has
to be active low signal. When a hardware is designed with active
high card detect, gpio polarity has to be changed with
cd-inverted dt property.
In AM43xx the card detect gpio is designed as active low gpio.
So correcting the dt card detect gpio definition.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
- Set CONFIG_SYS_CACHELINE_SIZE to ARCH_DMA_MINALIGN as that should be
good enough.
- Make <asm/io.h> include <asm/types.h> like other arches do
- Enable many many more drivers in sandbox_defconfig so that we can get
more build-time testing on this platform.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move all the gpio definitions to driver file as
there is no use of them in other files.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove non driver model support as it moved
to driver model. Dont need non driver model
anymore.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Enable DM GPIO and ZYNQ GPIO using kconfig instead of the board
config file.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There are mini configurations which need to be fit to OCM that's why
these options shouldn't be enabled by default.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds the sata port phy OOB timing values in the sata
device-tree node.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Mainline kernel has no r1p12 compatible string that's why console stops
to work with the latest DTS files. Append generic compatible string.
Keep in your mind that using this generic compatible string not all uart
features will be available.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Modifying device tree node to support legacy interrupts.
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
GPIO driver supports an input interrupt that's why gpio node itself can
be labeled as interrupt controller.
Reported-by: John Linn <linnj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds ddrc memory controller node in dts.
size mentioned in dts is 0x30000, because we need to access DDR_QOS
INTR registers located at fd090208 from this driver.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ZynqMP DMA's main clock and apb clock are added
in zynqmp DT.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
ZynqMP is not using global interrupt-parent setting that's why
it has to be listed in every node separately. PMU node missed it and
this patch is adding it.
Reported-by: John Linn <John.Linn@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add power-domains to the DT and attach devices to them.
The power-domains are all logical domains as understood by firmware.
Each PD is identified by a unique identifier that the platform firmware
understands.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds broken-tuning property to SD and
eMMC nodes.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove jumbo properties which are handled in the driver directly
and use mainline compatible string which is already handled by the
driver.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch add 8-bit bus width property to eMMC node.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch makes compatible string as "m25p80" for qspi node in
ep108 device tree file
Signed-off-by: Ranjit Waghmode <ranjit.waghmode@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change the dtsi include code to use the C pre-processor #include instead
of the device tree /include/. This brings all ZynqMP device trees inline
with each other.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add missing adv7511 and configure to match Base TRD.
Signed-off-by: Christian Kohn <christian.kohn@xilinx.com>
Reviewed-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
- Have compatible string as the first property
- Sync with Linux kernel dtsi
- Add missing interrupt properties
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Added addtional bindings required for FPGA Manager operation
of the Xilinx Zynq Devc configuration interface.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
GPIO driver supports an input interrupt that's why gpio node itself can
be labeled as interrupt controller.
Reported-by: John Linn <linnj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The Orange Pi One SBC, is a stripped down version of the popular
Orange Pi PC. The one is a H3 based SBC, with 512M of RAM,
micro-sd slot, 1 host usb, 1 otg usb, hdmi and 100Mbit ethernet.
The dts is identical to the dts submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We have CONFIG_CMD_GPIO=y in almost all sunxi boards, but after
its Kconfig conversion it has ended up missing on some recently
added boards.
Simply select it for ARCH_SUNXI, so that we get it on all
sunxi boards for both a consistent user experience and simpler
defconfig files.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
DLDO3 is used to provide Port-D power and PD is used for the
usb-hub / sata-5v enable pins. The 2.5V comes from the schematic
and matches the factory image fex file.
The dts changes are the minimal changes needed for u-boot to
pick-up the usb host controllers. The upstream kernel does not
(yet) have usb host support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Some boards have on board usb devices which need longer than the USB
spec's 1 second to connect from board powerup. Add a config option which
when non 0 adds an extra delay before the first usb bus scan.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
v7_maint_dcache_all() does not work reliable when build with gcc6,
see: https://bugzilla.redhat.com/show_bug.cgi?id=1318788
While debugging this I learned that v7_maint_dcache_all() is unreliable
when build with gcc5 too when it is marked as noinline.
This commit fixes the reliability issues by replacing the C-code with
the ready to use asm implementation from the kernel.
Given that this code when written as C-code clearly is quite fragile
(also see the existing comments about the C-code being the way it is
to get optimal assembly) and that we have a proven asm alternative,
I believe that this is the best solution.
Note that we actually already had a copy of the kernel's
v7_flush_dcache_all() before this commit in
arch/arm/mach-uniphier/arm32/lowlevel_init.S.
This commit moves that code arch/arm/cpu/armv7/cache_v7_asm.S, renames
it to __v7_flush_dcache_all(), and adds a v7_flush_dcache_all() wrapper
which saves / restores the clobbered registers for use from C-code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now that rpi_*defconfig and Kconfig (rather than the config header file)
provide the identity of the build, we don't need to separate config
headers and board directories for each RPi variant. Set CONFIG_SYS_BOARD
and CONFIG_SYS_CONFIG_NAME so that we can get rid of the duplication. This
requires a tiny number of extra ifdefs in the config header.
The only disadvantage of this approach is that the $board/$board_name
environment variables aren't as descriptive as they used to be. This isn't
really an issue because those only exist to allow scripts to create DTB
filenames at runtime. However, the RPi board code already sets $fdtfile to
something more accurate based on FW-reported board ID anyway.
While at it, unify some Kconfig select options, and add a MAINTAINERS
entry for bcm283x too.
Partially-suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Commit cf7c93cdd7 "usb: ehci: Implement V2P mapping"
introduced usage of virt_to_phys() in ehci-hcd.
Since there was no implementation of virt_to_phys() for ARC
compilation of the ehci-generic driver failed.
This change adds virt_to_phys() stub for ARC so now
USB driver for AXS101 board could be built again.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Acked-by: Marek Vasut <marex@denx.de>
ISS is obsolete now and nSIM is used for simulation instead.
In its turn nSIM properly handles baud-rate settings so get rid
of now useless check.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Add notes re: enabling the UART to the RPi 3 32-bit help text. Fully
describe the RPi 3 64-bit board option.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
On all Pis so far, the VC FW provides a short stub to set up the ARM CPU
before entering the kernel (a/k/a U-Boot for us). This feature is not
currently supported by the VC FW when booting in 64-bit mode. However,
this feature will likely appear in the near future, and this U-Boot port
assumes that such a feature is in place. Without that feature, or a
temporary workaround described below, U-Boot will not boot.
Once the VC FW does provide the ARM stub, u-boot.bin built for rpi_3 can
be used drectly as kernel7.img, in the same way as any other RPi port. The
following config.txt is required:
# Fix mini UART input frequency, and setup/enable up the UART.
# Without this option, U-Boot will not boot, even if you don't care
# about the serial console. This option will always be required for
# all RPi3 use-cases, unless the PL011 UART is used, which is not
# yet supported by rpi_3* builds of U-Boot.
enable_uart=1
# Boot in AArch64 (64-bit) mode.
# It is possible that a future VC FW will remove the need for this
# option, instead auto-setting 32-/64-bit mode based on the "kernel"
# filename present on the SD card.
arm_control=0x200
Prior to the VC FW providing the ARM boot stub, you can use the following
steps to build an equivalent stub into the U-Boot binary:
git clone https://github.com/swarren/rpi-3-aarch64-demo.git \
../rpi-3-aarch64-demo
(cd ../rpi-3-aarch64-demo && ./build.sh)
Build U-Boot for rpi_3 in the usual way
cat ../rpi-3-aarch64-demo/armstub64.bin u-boot.bin > u-boot.bin.stubbed
Use u-boot.bin.stubbed as kernel7.img on the Pi SD card.
In this case, the following additional entries are required in config.txt:
# Tell the FW to load the kernel image at address 0, the reset vector.
kernel_old=1
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
There are ARM SoCs (such as the BCM2837) do not contain an ARM GIC. Fix
the ARMv8 CPU startup code to compile in this case.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
The dwmmc.h include was forgotten during the migration of dwmmc
probing to DM. Since the shiny DM is in place now, remove this
relic of the past.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Thus far, the socfpga init code had hard-coded the configuration
of the ethernet PHY interface to RGMII in the ethernet registers
in sysmgr space, so PHYs connected in another modes did not work.
This patch fixes support for configurations where the ethernet PHYs
are connected over MII/GMII/RMII interfaces by parsing the phy-mode
OF property of the GMACs and configuring the ethernet registers in
sysmgr space accordingly.
Signed-off-by: Marek Vasut <marex@denx.de>
Reported-by: Denis Bakhvalov <denis.bakhvalov@nokia.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h
but not the writes[bwql], reads[bwql] needed by some drivers.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
To enable DM on MPC85xx, we need pre-relocation malloc, which is
implemented in this patch.
We also make sure that the IVORs are always 4-aligned on e500 to prevent
alignment exceptions caused by code changes in start.S.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Cc: York Sun <york.sun@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This patch aims to fix the order of CSU slave index for the LS1021a
board.
Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
When switching between the early and final mmu tables, the stack will
get corrupted if the Non-Secure attribute is different. For ls1043a,
this issue is currently masked because flush_dcache_all is called
before the switch when CONFIG_SYS_DPAA_FMAN is defined.
Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Currently only chip-select 0 is supported by the kirkwood SPI driver.
The Armada XP / 38x SoCs also use this driver and support multiple chip
selects. This patch adds support for multiple CS on MVEBU.
The register definitions are restructured a bit with this patch. Grouping
them to the corresponding registers.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jteki@openedev.com>
This option enable adding new platform suport just by adding defconfig
and DTS file which will target generic configuration for SoC.
Make no sense to extend Kconfig just create a pointer between DTS and
configuration file.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Read information about timer and interrupts from DT. This is the first
small step to move timer and intc to DM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Provide board specific option how to read MAC address from ROM.
Do it in generic way to be reusable by differnet boards.
If this is not enough board specific functions can be created.
Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Armada 375 still has some problems with d-cache enabled in the ethernet
driver (mvpp2). So lets keep the d-cache disabled until this is solved.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch adds basic support for the Marvell A375 eval board. Tested
are the following interfaces:
- I2C
- SPI
- SPI NOR
- Ethernet (mvpp2), port 0 & 1
Currently the A375 SerDes and DDR3 init code is not intergrated. So
the SPL U-Boot is not fully functional.
Right now, this A375 mainline U-Boot can only be used by chainloading
it via the original Marvell U-Boot. This can be done via this
command:
=> tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch adds basic support for the Armada 375. Please note that
currently the SerDes and DDR3 init code for the A375 is not
included / enabled. This will be done in a later, follow-up patch.
Right now, this A375 mainline U-Boot can only be used by chainloading
it via the original Marvell U-Boot. This can be done via this
command:
=> tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This commit add support for 96Boards Dragonboard410C.
It is board based on APQ8016 Qualcomm SoC, complying with
96boards specification.
Features (present out of the box):
- 4x Cortex A53 (ARMv8)
- 2x USB Host port
- 1x USB Device port
- 4x LEDs
- 1x HDMI connector
- 1x uSD connector
- 3x buttons (Power, Vol+, Vol-/Reset)
- WIFI, Bluetooth with integrated antenna
- 8GiB eMMC
U-Boot boots chained with fastboot in 64-bit mode.
For detailed build instructions see readme.txt in board directory.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>
First supported chip is APQ8016 (that is compatible with MSM8916).
Drivers in SoC code:
- Reset controller (PSHOLD)
- Clock controller (very simple clock configuration for MMC and UART)
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
This patch adds emulated spmi bus controller with part of
pm8916 pmic on it to sandbox and tests validating SPMI uclass.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Most of ehci-fsl header describe USB controller
designed by Chipidea and used by various SoC vendors.
This patch renames it to a generic header: ehci-ci.h
Contents of file are not changed (so it contains several
references to freescale SoCs).
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Simon Glass <sjg@chromium.org>
This moves the sniper board from the lge to lg, in order to match the devicetree
vendor prefix already defined in the kernel.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
The default board_init_f() implementation performs a call to
board_init_r() as the last step of the sequence. Fix the comment
for this function to reflect the actual execution flow.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
The Raspberry Pi 3 contains a BCM2837 SoC. The BCM2837 is a BCM2836 with
the CPU complex swapped out for a quad-core ARMv8. This can operate in 32-
or 64-bit mode. 32-bit mode is the current default selected by the
VideoCore firmware on the Raspberry Pi 3. This patch adds a 32-bit port of
U-Boot for the Raspberry Pi 3.
>From U-Boot's perspective, the only delta between the RPi 2 and RPi 3 is a
change in usage of the SoC UARTs. On all previous Pis, the PL011 was the
only UART in use. The Raspberry Pi 3 adds a Bluetooth module which uses a
UART to connect to the SoC. By default, the PL011 is used for this purpose
since it has larger FIFOs than the other "mini" UART. However, this can
be configured via the VideoCore firmware's config.txt file. This patch
hard-codes use of the mini UART in the RPi 3 port. If your system uses the
PL011 UART for the console even on the RPi 3, please use the RPi 2 U-Boot
port instead. A future change might determine which UART to use at
run-time, thus allowing the RPi 2 and RPi 3 (32-bit) ports to be squashed
together.
The mini UART has some limitations. One externally visible issue in the
BCM2837 integration is that the UART divides the SoC's "core clock" to
generate the baud rate. The core clock is typically variable, and under
control of the VideoCore firmware for thermal management reasons. If the
VC FW does modify the core clock rate, UART communication will be
corrupted since the baud rate will vary from the expected value. This was
not an issue for the PL011 UART, since it is fed by a fixed 3MHz clock. To
work around this, the VideoCore firmware can be told not to modify the SoC
core clock. However, the only way this can happen and be thermally safe is
to limit the core clock to a low/minimum frequency. This leaves
performance on the table for use-cases that don't care about a UART
console. Consequently, use of the mini UART console must be explicitly
requested by entering the following line into config.txt:
enable_uart=1
A recent version of the VC firmware is required to ensure that the mini
UART is fully and correctly initialized by the VC FW; at least
firmware.git 046effa13ebc "firmware: arm_loader: emmc clock depends on
core clock See: https://github.com/raspberrypi/firmware/issues/572".
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This adds an explanation of which Raspberry Pi models each target option
supports.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
MSMC segment Privilege ID is not consistent accross the keystone2 SoCs.
As the first step to ensure complete SoC wide coherency setup, lets
refactor the macros to remove the #if-deffery around the code which
obfuscates which IDs are actually enabled for which SoC.
As a result of this change the PCIe configuration is moved after the
msmc configuration is complete, but that should ideally have no
functional impact.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
- Move most of the flags required into LLVM_RELFLAGS to test at build
time instead of requiring them to be passed in.
- Update doc/README.clang to reflect this
- Switch to rpi_2 as the example as it's closer to working out of the
box than rpi is.
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Signed-off-by: Tom Rini <trini@konsulko.com>
The Pine64+ is a system based on the Allwinner A64 SoC. It is capable of
running AArch64 code and thus is the first of its kind for the sunxi target.
This patch adds a defconfig and device tree chunks for it.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[agraf: Change patch description]
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Allwinner A64 SoC is used in the Pine64. This patch adds
all bits necessary to compile U-Boot for it running in AArch64
mode.
Unfortunately SPL is not ready yet due to legal problems, so
we need to boot using the binary boot0 for now.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[agraf: remove SPL code, move to AArch64]
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Some parts of the sunxi code cast explicitly between u32 values and pointers.
This is not a problem in practice, because all 64bit SoCs today only use the
lower 32 bits for their phyical address space. But we need to make sure that
the compiler is sure this is not an accident as well.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
We currently depend SPL config options on specific machine types which doesn't
scale. Fortunately there's already a kconfig variable that tells us whether we
want to build SPL code at all, so just depend them on this.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while
most of it is just generic code that could as well be used on an AArch64 SoC.
Move all files that are not really tied to armv7 into a new mach-sunxi
directory.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This provides the minimal changes to the H8Homlet v2 dts to enable USB
in U-boot. It is not what will be submitted to the kernel.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This provides the minimal changes to the Cubietruck Plus dts to enable USB
in U-boot. It is not what will be submitted to the kernel.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This provides the minimal changes to the A83T dtsi to enable USB in
U-boot. It is not what will be submitted to the kernel.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Eliminate the "ph1"_ prefixes from function names because "uniphier_"
describes the SoC familiy better.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
On PH1-sLD3, eMMC and NAND are assigned to different I/O pins.
Both devices can be enabled at the same time.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, these functions assume #address-cells and #size-cells are
both one. Fix them to support 64bit DTB.
Also, I am fixing a buffer overrun bug while I am here. The array
size of gd->bd->bd_dram is CONFIG_NR_DRAM_BANKS. The number of
iteration in the loop should be limited by that CONFIG.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Since no clock driver is implemented for peripherals in U-Boot yet,
this property is needed for the serial driver to set up the divisor
register.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The A83T has 3 PHYs, the last one being HSIC, which has 2 clocks.
Also there is only 1 OHCI.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The A83T has 3 USB PHYs: 1 for USB OTG, 1 for standard USB 1.1/2.0 host,
1 for USB HSIC.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
As the need for various magic sram pokes has shown this maybe useful
info to have. e.g. this shows one of my a23 tablets having an id of
1661 rather then the usual 1650 for the a23.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
I noticed that for certain SoC versions boot0 does a magic poke when
build for A33. I'm not aware of this actually being necessary anywhere,
but better safe then sorry.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This bit needs to be set for system suspend/resume to work. This setting
will be documented in an updated TRM at some time in the future.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This patch enable VID support for ls2080ardb platform.
It uses the common VID driver.
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs
to be put in bypass mode in uboot to enable CAAM transcations to pass
through.
For non-secure boot, SP BootROM doesn't enable SMMU, which is in
bypass mode out of reset.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The GUR (DCFG) registers in CCSR space are in little endian format.
Define a config CONFIG_SYS_FSL_CCSR_GUR_LE in
arch/arm/include/asm/arch-fsl-layerscape/config.h
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
"fdt_high" env variable was set to 0xcfffffff for secure boot.
Change it to 0xa0000000 for LS2080 to be consistent with non-secure
boot targets.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
To unify steps for secure boot for xip (eg. NOR) and non-xip memories
(eg. NAND, SD), bootscipts and its header are copied to main memory.
Validation and execution are performed from there.
For other ARM Platforms (ls1043 and ls1020), to avoid disruption of
existing users, this copy step is not used for NOR boot.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
During secure boot, Linux image along with other images are validated
using bootscript. This bootscript also needs to be validated before
it executes. This requires a header for bootscript.
When secure boot is enabled, default bootcmd is changed to first
validate bootscript using the header and then execute the script.
For ls2080, NOR memory map is different from other ARM SoCs. So a new
address on NOR is used for this bootscript header (0x583920000). The
Bootscript address is mentioned in this header along with addresses of
other images.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sec_init has been called at the beginning to initialize SEC Block
(CAAM) which is used by secure boot validation later for both ls2080a
qds and rdb. 64-bit address in ESBC Header has been enabled. Secure
boot defconfigs are created for boards (NOR boot).
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For secure boot, a header is used to identify key table, signature
and image address. A new header structure is added for lsch3.
Currently key extension (IE) feature is not supported. Single key
feature is not supported. Keys must be in table format. Hence, SRK
(key table) must be present. Max key number has increase from 4 to
8. The 8th key is irrevocable. A new barker Code is used.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add configs for various IPs used during secure boot. Add address
and endianness for SEC and Security Monitor. SRK are fuses in SFP
(fuses for public key's hash). These are stored in little endian
format.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In LS2080, SFP has version 3.4. It is in little endian. The base
address is 0x01e80200. SFP is used in Secure Boot to read fuses.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The qspi_cfg register is set by PBI when booting from QSPI. No need
to changing it again.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Implement i2c_idle_bus in driver, then setup_i2c can
be dropped for boards which enable DM_I2C/DM_GPIO/PINCTRL.
The i2c_idle_bus force bus idle flow follows setup_i2c in
arch/arm/imx-common/i2c-mxv7.c
This patch is an implementation following linux kernel patch:
"
commit 1c4b6c3bcf30d0804db0d0647d8ebeb862c6f7e5
Author: Gao Pan <b54642@freescale.com>
Date: Fri Oct 23 20:28:54 2015 +0800
i2c: imx: implement bus recovery
Implement bus recovery methods for i2c-imx so we can recover from
situations where SCL/SDA are stuck low.
Once i2c bus SCL/SDA are stuck low during transfer, config the i2c
pinctrl to gpio mode by calling pinctrl sleep set function, and then
use GPIO to emulate the i2c protocol to send nine dummy clock to recover
i2c device. After recovery, set i2c pinctrl to default group setting.
"
See Documentation/devicetree/bindings/i2c/i2c-imx.txt for detailed
description.
1. Introuduce scl_gpio/sda_gpio/bus in mxc_i2c_bus.
2. Discard the __weak attribute for i2c_idle_bus and implement it,
since we have pinctrl driver/driver model gpio driver. We can
use device tree, but not let board code to do this.
3. gpio state for mxc_i2c is not a must, but it is recommended. If
there is no gpio state, driver will give tips, but not fail.
4. The i2c controller was first probed, default pinctrl state will
be used, so when need to use gpio function, need to do
"pinctrl_select_state(dev, "gpio")" and after force bus idle,
need to switch back "pinctrl_select_state(dev, "default")".
This is example about how to use the gpio force bus
idle function:
"
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
status = "okay";
[....]
};
[.....]
pinctrl_i2c1_gpio: i2c1grp_gpio {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
>;
};
"
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
dma_addr_t holds any valid DMA address. If the DMA API only uses 32-bit
addresses, dma_addr_t need only be 32 bits wide. Bus addresses, e.g., PCI BARs,
may be wider than 32 bits, but drivers do memory-mapped I/O to ioremapped
kernel virtual addresses, so they don't care about the size of the actual
bus addresses.
Also 32 bit ARM systems with LPAE enabled can use 64bit address space, but
DMA still use 32bit address like in case of DRA7 and Keystone platforms.
This is inspired from the Linux kernel types implementation[1]
[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/include/linux/types.h#n142
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
SRAM is used for early stack, but kernel disables its clock on suspend.
Re-enable SRAM clock on startup, otherwise u-boot crashes on resume from suspend.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Fix typo "choosen" instead of "chosen" in pcm052.dts.
Not tested but should fix boot process and terminal output.
Signed-off-by: Alexander Merkle <alexander.merkle@lauterbach.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fix typo "choosen" instead of "chosen" in vf610-twr.dts.
Fixes boot process and terminal output for Vybrid series.
Signed-off-by: Alexander Merkle <alexander.merkle@lauterbach.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fixes:
arch/arm/mach-bcm283x/mbox.c: In function ‘bcm2835_mbox_call_prop’:
arch/arm/mach-bcm283x/mbox.c:118:48: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
arch/arm/mach-bcm283x/mbox.c:126:29: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Currently, CONFIG_BCM2835 is defined for all BCM283x builds and _BCM2836
is defined when building for that SoC. That means there isn't a single
define that means "exactly BCM2835". This will complicate future patches
where BCM2835-vs-anything-else needs to be determined simply.
Modify the code to define one or the other of CONFIG_BCM2835/BCM2836 so
future patches are simpler.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Now that we have support for running with caches enabled in HYP mode,
opt in to that on the Raspberry Pi 2. This brings a significant performance
boost.
Signed-off-by: Alexander Graf <agraf@suse.de>
We currently always modify the SVC versions of registers and only support
the short descriptor PTE format.
Some boards however (like the RPi2) run in HYP mode. There, we need to modify
the HYP version of system registers and HYP mode only supports the long
descriptor PTE format.
So this patch introduces support for both long descriptor PTEs and HYP mode
registers.
Signed-off-by: Alexander Graf <agraf@suse.de>
We want to be able to reuse device drivers from 32bit code, so let's add
definitions for all the dcache options that 32bit code has.
While at it, fix up the DCACHE_OFF configuration. That was setting the bits
to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless
bits and make the index explicit.
Signed-off-by: Alexander Graf <agraf@suse.de>
do_set_iodelay can now be used from board files based on needs of the
platforms variation they have.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Since many platforms may need different pad configuration required
depending on variation of the platform with minor deltas, it is
easier to maintain a sub step based approach to allow for pin mux
and iodelay configuration which may depend on the platform variations
and need to be done in IO isolation.
While we retain the older __recalibrate_iodelay function which provides
a ready sequencing, __recalibrate_iodelay_start and
__recalibrate_iodelay_end may be alternatively used now and the callers
will be responsible for the correct sequencing of operations.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Based on data from EMIF configuration tool 1.1.1. Expected update for
CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT in the next revision of the tool has
been incorporated as well.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add support for detection of SR2.0 version of DRA72x family of
processors.
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fix up BOOT_SET_BITFIELD to be a static inline function to be readable
with the same functionality.
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
BOOT_READ_BITFIELD can easily be a static inline function and be a
little more readable with the same functionality.
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
BOOTBITMASK is almost impossible to decode, so convert it into a simpler
static line functions of equivalent solution.
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Same flash driver can be used by other stm32 families like stm32f7.
Better place for this driver would be mtd driver location.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
If including MX7D in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS
will not effect.So move MX7D to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to
"select MX7D" to boards using i.MX7 Dual.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
If including MX6SX in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS
will not effect.So move MX6SX to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to
"select MX6SX" to boards using i.MX6 SoloX.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
This patch add support for the CCV xPress board which is equipped
with the i.MX6UL. And provides the following interfaces:
- 128MiB DDR
- UART
- I2C
- eMMC (with booting)
- Ethernet
- USB
This patch adds two build targets. One with and one without SPL. The
non-SPL version is used for loading U-Boot via USB (imx_usb_loader).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Add the base address for the i.MX6UL so that this UART can be used.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Make the watchdog registers 16-bit wide, as they are according to TRM.
Signed-off-by: Leonid Iziumtsev <leonid.iziumtsev@se.atlascopco.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Switch the DDR3 calibration from ad-hoc implementation of wait_for_bit()
to generic implementation of wait_for_bit().
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Configure the PMIC_STBY_REQ pin as open drain 100K according
to the design team's requirement for the PMIC_STBY_REQ pin
for i.MX 6UltraLite TO1.0.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
To i.MX6UL, default ARM rate and AHB rate is 396M and 198M,
no need to set them.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
When clear this bit, the periph_clk_sel cannot be set and that
CDHIPR[periph_clk_sel_busy] handshake never clears.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This patch adds support for Altera StratixV bitstream programming. 2 FPGAs
are connected to the SPI busses. This patch uses board specific write
code to program the bitstream via SPI direct write mode.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Stefan Roese <sr@denx.de>
The direct write config register is needed for SPI direct write mode
configuration.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Stefan Roese <sr@denx.de>
These attribute defines may be used to map an area of memory for direct
access to the specific SPI devices. See SPI Direct Access Mode for
further information.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Stefan Roese <sr@denx.de>
In mctl_channel_init, (0x50<<26) which overflows 32bit.
It was supposed to be 0x50<<16,corrected now.
Reported-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Always select OF_BOARD_SETUP on sunxi, rather then having it in almost
all our defconfigs. This also fixes it missing from some recently
added defconfigs.
This commit also modifies our ft_board_setup() to not cause warnings
when CONFIG_VIDEO_DT_SIMPLEFB is not set, since we will now always
build it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
cpu_eth_init is no longer called for dm enabled eth drivers, this
was causing the sunxi gmac eth controller to no longer work in u-boot.
This commit fixes this by calling the clock, reset and pinmux setup
function from s_init() and enabling the phy power pin (if any) from
board_init().
The enabling of phy power cannot be done from s_init because it uses dm
and dm is not ready yet at this point.
Note that the mdelay is dropped as the phy gets enabled much earlier
now, so it is no longer needed.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Karsten Merker <merker@debian.org>
Tested-by: Michael Haas <haas@computerlinguist.org>
The H3 has USB0 - USB3, add support for having a USB vbus pin for USB3.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
On the A83T and H3, the SID block is at a different address.
Furthurmore, the e-fuses are at an offset of 0x200 within the
hardware's address space.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Orange Pi 2 is a SBC based on the Allwinner H3 SoC with a uSD slot,
4 USB ports connected via a USB-2 hub, a 10/100M ethernet port using the
SoC's integrated PHY, Wifi via a RTL8189ETV sdio wifi chip, USB OTG, HDMI,
a TRRS headphone jack for stereo out and composite out, a microphone,
an IR receiver, a CSI connector, 2 LEDs, a 3 pin UART header
and a 40-pin GPIO header.
The added dts file is identical to the one submitted to the upstream
kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Dserve DSRV9703C is a 9.7" A10 tablet with a 1024x768 ips LCD,
1G RAM, 4GB flash, a Focaltech FT5406EE8 touchscreen and rtl8188ctv wifi.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Polaroid MID2809PXE4 is a 9" tablet which is clearly marked
Polaroid MID2809PXE4 on the back. It features a 9" 16:9 800x480 LCD,
A23 Soc, 1GB RAM, 8GB NAND, gsl3670 touchscreen and esp8089 wifi.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Difrnce dit4350 tablet is a tiny tablet with a 4.3" 16:9 480x272 LCD,
A13 SoC, 512M RAM, 4G NAND, solomon systech ssd2532qn6 touchscreen at
i2c1 address 0x48, Memsic MXC622X accelerometer at i2c1 address 0x15 and
rtl8188etv wifi.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The colorfly e708 q1 is a 7" tablet which is clearly marked as colorfly
e708 q1 on the back. It features a 9:16 800x1280 IPS LCD, A31s SoC,
1GB RAM, 8G NAND, ilitek 2139qt004 touchscreen on i2c-1 addr 0x41,
stk8313 accelerometer on i2c-2 addr 0x22 and a rtl8188etv wifi chip.
The added dts is identical to the dts submitted to the upstream kernel,
note this commit also syncs axp22x.dtsi and sun6i-a31.dtsi with the
upstream kernel as the added dts depends on these.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Fix a copy and paste error which caused us to use the uart rather then
the twi reset bits in clock_twi_onoff for sun9i.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
clock_sun8i_a83.c did not contain a clock_twi_onoff implementation
at all, this is fixed by moving the clock_sun6i.c implementation,
which is correct for the a83 too, to a shared location.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The clock_sun6i.c implementation was not deasserting the reset for
the regular i2c controllers, this commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Sync dts files with the upstream kernel including
changes queued for 4.6:
https://git.kernel.org/cgit/linux/kernel/git/mripard/linux.git/commit/?h=sunxi/dt-for-4.6
Note this adds a number of new unused board dts files. I've asked the
authors of the kernel commits adding these to submit a matching defconfig
to u-boot.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
I've had this one a23 tablet which would not boot and I've finally
figured out what the problem is by looking at the released boot0 code,
it seems the magic sram controller poke which we need to do in s_init()
depends on the revision of the a23.
Specifically this change is needed to get the A23 SoC I have with the
following serial to boot: "E6071AB 26Y7".
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This allows to boot from NOR flash (or SRAM) with help of an external
loader (NOR-loader).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
For ARM32 architecture, CONFIG_DEBUG_LL is available for early
low-level debugging (and actually UniPhier 32bit SoCs use it), but
ARM64 architecture does not support it. Instead, CONFIG_DEBUG_UART
is available as an architecture-independent debug facility.
This commit supports it on all the UniPhier SoCs (including the new
ARMv8 SoCs), which is very useful for new SoC bringups.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The System Control block moved to a completely different register
map for ARMv8 SoCs, so it cannot be shared with the ARM 32-bit ones.
Define register macros in a new header file.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This helper function would be useful for new SoCs with per-pin
input enable controlling, such as PH1-LD20, PH1-LD11, etc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
These commands are not necessarily needed for usual operations
(they are useful in case of DDR memory trouble), but enabling them
by default would be nice in terms of the compilation test coverage.
They are small enough, so limited impact on the memory footprint.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Due to some hardware guy's awful work, this version is not compatible
with v3.6: the logic of BIT(0) of the reset logic is inverted! (and
v3.6.10 is horribly wrong in multiple ways), but this is what we have
to solve now.
The v3.6 expects 0x0000 set to the register for reset de-assertion,
while v3.6 does 0x0001.
This commit (ab)uses another bug of v3.6.10 to work around the issue.
The UniPhier System Bus is a 16-bit bus, which this support card is
connected to. A 32-bit write to the bus (writel() function call) is
divided into two 16-bit write transactions, with LSB the first. What
is amazing for v3.6.10 is that access to address 4N + 2 goes to 4N
(Jesus Christ!).
For clarification, things are like this:
writel(0x00010000, MICRO_SUPPORT_CARD_RESET);
is done with two bus transactions as follows
[1] write 0x0000 to address MICRO_SUPPORT_CARD
[2] write 0x0001 to address MICRO_SUPPORT_CARD + 2
For v3.6, [1] is written to the register and [2] is correctly ignored
because there is nothing at the address MICRO_SUPPORT_CARD + 2. This
is what we expect.
For v3.6.10, [1] is written to the reset register and then [2] is
over-written to the same register due to the bus access bug.
For the latter, it produces a glitch signal to the BIT[0], so the
device state is lost due to the reset pulse. This solution only
works for the start-up code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The ifdef conditionals in header files prevent us from multi-SoC
support in a single U-Boot image. Detect SoC specific parameters
run-time rather than define them statically with an ifdef in
ddrphy-regs.h.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
There is a bunch of duplication in the System Bus Controller init
code. Roughly, there are two types in the SBC mode: Adress/Data
Multiplex Mode and Save Pins Mode. Consolidate per-SoC functions
into the two, plus per-SoC optional init code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The current CONFIG names like "CONFIG_ARCH_UNIPHIER_PH1_PRO4" is too
long. It would not hurt to drop "PH1_" because "UNIPHIER_" already
well specifies the SoC family. Also, rename files for consistency.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Import uniphier-support-card.dtsi from Linux Kernel and make it
available on the UniPhier reference boards.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Update the link script to drop this code when not needed. This is only done
for two architectures at present.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
The eSDHC could select to use platform clock or peripheral clock to
generate SD clock. The default selection is platform clock. So, fix
the clock frequency value that's calculated for eSDHC.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The serdes protocol entries in Serdes table 1 for protocol
0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45
and 0x47 are updated to reflect the entries in
current Reference Manual.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Reported-by: Jose Rivera <german.rivera@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
During initial DDR training, false parity errors may be detected.
This patch adds workaround to fix the erratum.
Tested on LS2085QDS and LS2080RDB.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The per-PCI controller LUT (Look-Up-Table) is a 32-entry table
that maps PCI requester IDs (bus/dev/fun) to a stream ID.
Add defines for the register offsets.
Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Update comments around how stream IDs are partitioned.
Stream IDs allocated to PCI are no longer divided up by
controller, but are instead a contiguous range
Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Remove stream ID partitioning support that has been made
obsolete by upstream device tree bindings that specify how
representing how PCI requester IDs are mapped to MSI specifiers
and SMMU stream IDs.
Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As the compatible property values for QSPI and DSPI dts nodes
are changed in kernel, FSL_QSPI_COMPAT and FSL_DSPI_COMPAT
need to be updated too.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Enable wuo config to accelerate coherent ordered writes for LS2080A
and LS2085A.
WRIOP IP is connected to RNI-20 Node.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
With commit 7985cdf we converted all systems except for the Layerscape
SoCs to the generic descriptor table based page table setup.
On the Layerscape SoCs however, we just provide an empty table stub
and do the setup ourselves. To reserve enough memory for the tables,
we need to override the default counting mechanism which would end up
with an empty table because we have no maps.
Fixes: 7985cdf
Reported-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: York Sun <york.sun@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch makes the following changes to the SR1500 board port:
- Update defconfig to support SPI NOR (use make savedefconfig).
- Increase SPI speed to a maximum of 100MHz for faster system
bootup.
- Change environment location, so that its not between SPL and
main U-Boot. This way the combined SPL / U-Boot image can
be used for updates.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
This change is required to avoid warnings about invalid
size-cells defined in device-tree pinctrl nodes for Exynos.
Tested on:
- Odroid U3
- Odroid XU3
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM,
installed on the congatec Qseven 2.0 evaluation carrier board
(conga-QEVAL).
Its port is very similar to the MinnowboardMAX port and also uses
the Intel FSP as described in doc/README.x86.
Currently supported are the following interfaces / devices:
- UART (via Winbond legacy SuperIO chip on carrier board)
- Ethernet (PCIe Intel I210 / E1000)
- SPI including SPI NOR as boot-device
- USB 2.0
- SATA via U-Boot SCSI IF
- eMMC
- Video (HDMI output @ 800x600)
- PCIe
Not supported yet is:
- I2C
- USB 3.0
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.
Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard
Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).
The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI
without any 16-bit init. This can help during development by allowing U-Boot
to avoid doing all the init required by the platform.
U-Boot expects its GDT to be set up correctly by its 16-bit code. If
coreboot doesn't do this (because it hasn't run the payload setup code yet)
then this won't happen.
In this case we cannot rely on the GDT settings. U-Boot will hang or crash
if these are wrong. Provide a development-only option to set up the GDT
correctly. This is just a hack so you can jump to U-Boot from any stage of
coreboot, not just at the end.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is not needed now that the memory controller driver has the SPD data
in its own node.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adjust the existing implementation to use the new common SDRAM init code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The code to call the memory reference code is common to several Intel CPUs.
Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
(PEI), where EFI stands for Extensible Firmware Interface.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is missing, with causes lldiv() to fail on boards with use the private
libgcc. Add the missing routine.
Code is available for using the CLZ instruction but it is not enabled at
present.
This comes from coreboot version 4.0.
Signed-off-by: Simon Glass <sjg@chromium.org>
Provide a way to determine the HSIO (high-speed I/O) version supported by
the Intel Management Engine (ME) implementation on the platform.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Broadwell uses a binary blob called the memory reference code (MRC) to start
up its SDRAM. This is similar to ivybridge so we can mostly use common code
for running this blob.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Broadwell requires quite a bit of power-management setup. Add code to set
this up correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
[squashed in http://patchwork.ozlabs.org/patch/598373/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Broadwell needs a special binary blob to set up the PCH. Add code to run
this on start-up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly
uses common code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver for the broadwell northbridge. This sets up the location of
several blocks of registers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Add a SATA driver for broadwell. This supports connecting an SSD and the
usual U-Boot commands to read and write data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.
The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver for the broadwell low-power platform controller hub.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
This adds the broadwell architecture, with the CPU driver and some useful
header files.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Intel has invented yet another binary blob which firmware is required to
run. This is run after SDRAM is ready. It is linked to load at a particular
address, typically 0, but is a relocatable ELF so can be moved if required.
Add support for this in the build system. The file should be placed in the
board directory, and called refcode.elf.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't need this anymore - we can use device tree and the new pinconfig
driver instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver which sets up the pin configuration on x86 devices with an ICH6
(or later) Platform Controller Hub.
The driver is not in the pinctrl uclass due to some oddities of the way x86
devices work:
- The GPIO controller is not present in I/O space until it is set up
- This is done by writing a register in the PCH
- The PCH has a driver which itself uses PCI, another driver
- The pinctrl uclass requires that a pinctrl device be available before any
other device can be probed
It would be possible to work around the limitations by:
- Hard-coding the GPIO address rather than reading it from the PCH
- Using special x86 PCI access to set the GPIO address in the PCH
However it is not clear that this is better, since the pin configuration
driver does not actually provide normal pin configuration services - it
simply sets up all the pins statically when probed. While this remains the
case, it seems better to use a syscon uclass instead. This can be probed
whenever it is needed, without any limitations.
Also add an 'invert' property to support inverting the input.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present pin configuration on link does not use the standard mechanism,
but some rather ugly custom code. As a first step to resolving this, add the
pin configuration to the device tree.
Four of the GPIOs must be available before relocation (for SDRAM pin
strapping).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Each CPU needs to have its microcode loaded. Add support for this so that
all CPUs will have the same version.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Enable the microcode feature so that the microcode version is shown with the
'cpu detail' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
As each core starts up, record its microcode version and CPU ID so these can
be presented with the 'cpu detail' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the MRC options are private to ivybridge. Other Intel CPUs also
use these settings. Move them to a common place.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is common with memory-mapped I/O to use the address of a structure member
to access memory, as in:
struct some_regs {
u32 ctrl;
u32 data;
}
struct some_regs *regs = (struct some_regs *)BASE_ADDRESS;
writel(1, ®->ctrl);
writel(2, ®->data);
This does not currently work with inl(), outl(), etc. Add a cast to permit
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The clrsetbits_...() macros are useful for working with memory mapped I/O.
But they do not work with I/O space, as used on x86 machines.
Add some macros to provide similar features for I/O.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function was removed in the previous clean-up. Drop it from the header
file also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some of the Intel ME code is common to several Intel CPUs. Move it into a
common location. Add a header file for report_platform.c also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[squashed in http://patchwork.ozlabs.org/patch/598372/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This same name is used in USB. Add a prefix to distinguish it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some of the Intel CPU code is common to several Intel CPUs. Move it into a
common location along with required declarations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is similar to MCH in that it is used in various drivers. Add it to
the common header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
There are several blocks of registers that are accessed from all over the
code on Intel CPUs. These don't currently have their own driver and it is
not clear whether having a driver makes sense.
An example is the Memory Controller Hub (MCH). We map it to a known location
on some Intel chips (mostly those without FSP - Firmware Support Package).
Add a new header file for these registers, and move MCH into it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This code is used on several Intel CPUs. Move it into a common location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
intel_common directory and move it in there.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These two identifiers can be useful for drivers which need to adjust their
behaviour depending on the CPU family or stepping (revision).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The Intel SIPI (start-up inter-processor interrupt) vector is the entry
point for each secondary CPU (also called an AP - applications processor).
The assembler and C code are linked, so add comments to indicate this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The timeout step is always 50us. By updating apic_wait_timeout() to print
the debug messages we can simplify the code. Also tidy up a few messages and
comments while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO
is probed. However, it assumes that the first GPIO to be probed is in the
first GPIO bank. If this is not the case then the init will write to the
wrong registers.
Fix this. Also add a note that this code is deprecated. We should move to
using device tree instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the board ID GPIOs are hard-coded. Move them to the device tree
so that we can use general SDRAM init code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The SDRAM SPD (Serial Presence Detect) information should be contained
with the SDRAM controller. This makes it easier for the controller to access
it and removes the need for a separate compatible string.
As a first step, move the information.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
In order to use GPIO phandles we need to add some GPIO properties as
specified by the GPIO bindings. Add these for link.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Many of the model-specific indexes are common to several Intel CPUs. Add
some more common ones, and remove them from the ivybridge-specific header
file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This does not need to be modified at run-time, so make it const.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
SeaBIOS is an open source implementation of a 16-bit x86 BIOS.
It can run in an emulator or natively on x86 hardware with the
use of coreboot. With SeaBIOS's help, we can boot some OSes
that require 16-bit BIOS services like Windows/DOS.
As U-Boot, we have to manually create a table where SeaBIOS gets
system information (eg: E820) from. The table unfortunately has
to follow the coreboot table format as SeaBIOS currently supports
booting as a coreboot payload.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To prepare generating coreboot table from U-Boot, implement functions
to handle the writing.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For those secondary bootloaders like SeaBIOS who want to live in
the F segment, which conflicts the configuration table address,
now we allow write_tables() to write the configuration tables in
high area (malloc'ed memory).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Given all table write routines have the same signature, we can
simplify the codes by using a function table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change the parameter and return value of write_acpi_tables() to u32
to conform with other table write routines.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a new variable rom_table_start and pass it to ROM table write
routines. This reads better than previous single rom_table_end.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Clean up this file a little bit:
- Remove inclusion of <linux/compiler.h>
- Use tab in the macro definition
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
coreboot_tables.h should not include sysinfo related stuff.
Move those to asm/arch-coreboot/sysinfo.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move asm/arch-coreboot/tables.h to asm/coreboot_tables.h so that
coreboot table definitions can be used by other x86 builds.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Starting with 96e5b03 we use a linker list for partition table
information. However since we use this in SPL we need to make sure that
the SPL linker scripts include these as well. While doing this, it's
best to simply include all linker lists to future proof ourselves.
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reported-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
