These comments were copied from the Linux kernel driver in
drivers/platform/x86/intel_scu_ipc.c
Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Now that we have I2C#6 working, it's time to add a corresponsing
ACPI binding.
Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Now that we have the pinctrl driver for Merrifield in place we can make
use of it and set I2C#6 pins appropriately.
Initial configuration came from the firmware. Which quite likely has
been used in the phones, where that is not part of Atom peripheral, is
in use. Thus we need to override the leftover.
Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This API is going to be used to configure some pins that are protected
for simple modification.
It's not a comprehensive pinctrl driver but can be turned into one
when we need this in the future. Now it is planned to be used only
in one place. So that's why I decided not to pollute the codebase with a
full-blown pinctrl-merrifield nobody will use.
This driver reads corresponding fields in DT and configures pins
accordingly.
The "protected" flag is used to distinguish configuration of SCU-owned
pins from the ordinary ones.
The code has been adapted from Linux work done by Andy Shevchenko
in pinctrl-merrfifield.c
Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix build warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This interface will be used to configure properly some pins on
Merrifield that are shared with SCU.
scu_ipc_raw_command() writes SPTR and DPTR registers before sending
a command to SCU.
This code has been ported from Linux work done by Andy Shevchenko.
Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
In int-ll64.h, we always use the following typedefs:
typedef unsigned int u32;
typedef unsigned long uintptr_t;
typedef unsigned long long u64;
This does not need to match to the compiler's <inttypes.h>.
Do not include it.
The use of PRI* makes the code super-ugly. You can simply use
"l" for printing uintptr_t, "ll" for u64, and no modifier for u32.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
All architectures have the same definition for s8/16/32/64
and u8/16/32/64.
Factor out the duplicated code into <asm-generic/int-ll64.h>.
BTW, Linux unified the kernel space definition into int-ll64.h
a few years ago as you see in Linux commit 0c79a8e29b5f
("asm/types.h: Remove include/asm-generic/int-l64.h").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
You do not need to use the typedefs provided by compiler.
Our compilers are either IPL32 or LP64. Hence, U-Boot can/should
always use int-ll64.h typedefs like Linux kernel, whatever the
typedefs the compiler internally uses.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
As of today, the proposal of adding "acpi_rsdp_addr" to the kernel
boot protocol does not make its way to the kernel mainline. This
creates some confusion if we leave it in the U-Boot code base.
Remove it for now until we have a clear picture with kernel upstream.
Note this eventually does a partial revert to commit 3469bf4274
("x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parameters")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present Linux kernel loaded from U-Boot as an EFI payload does
not boot. This fills in kernel's boot params structure with the
required critical EFI information like system table address and
memory map stuff so that kernel can obtain essential data like
runtime services and ACPI table to boot.
With this patch, now U-Boot as an EFI payload becomes much more
practical: it is another option of kernel bootloader, ie, can be
a replacement for grub.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This implements payload-specific install_e820_map() to get E820 map
from the EFI memory map descriptors.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
A few fixes for 2018.09. Most noticable are:
- unbreak x86 target (-fdata-section fallout)
- fix undefined behavior in a few corner cases
- make Jetson TX1 boot again
- RTS fixes
- implement reset for simple output
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Merge tag 'signed-efi-2018.09' of git://github.com/agraf/u-boot
Patch queue for efi - 2018-08-21
A few fixes for 2018.09. Most noticable are:
- unbreak x86 target (-fdata-section fallout)
- fix undefined behavior in a few corner cases
- make Jetson TX1 boot again
- RTS fixes
- implement reset for simple output
We left -fdata-sections disabled for x86_64 before because we encountered
random bugs that were at that time inexplicable.
Turns out this really was just side effects of missing .bss* statements
in the linker scripts. With those fixed, we can enable data sections for all
targets.
Signed-off-by: Alexander Graf <agraf@suse.de>
When we build with -fdata-sections we may end up with bss subsections. Our
linker script explicitly lists only a single consecutive bss section though.
Adapt the statement to also include subsections.
This fixes booting efi-x86_app_defconfig.
Signed-off-by: Alexander Graf <agraf@suse.de>
It was observed sometimes U-Boot as the EFI payload fails to boot on
QEMU. This is because TSC calibration fails with no valid frequency.
This adds default TSC frequency in the device tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It was observed sometimes U-Boot as the coreboot payload fails to
boot on QEMU. This is because TSC calibration fails with no valid
frequency. This adds default TSC frequency in the device tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
There is no need to keep a separate coreboot_fb.dtsi since now we
have a generic coreboot payload dts.
While we are here, this also remove the out-of-date description in
the documentation regarding to coreboot framebuffer driver with
U-Boot loaded as a payload from coreboot. As the testing result with
QEMU 2.5.0 shows, the driver just works like a charm.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently building U-Boot as the coreboot payload requires user
to change the build configuration for a specific board during
menuconfig process. This uses the board's native device tree
to configure the hardware. For example, the device tree provides
PCI address range for the PCI host controller and U-Boot will
re-program all PCI devices' BAR to be within this range. In order
to make sure we don't mess up the hardware, we should guarantee
the range matches what coreboot programs the chipset.
But we really should make the coreboot payload support easier.
Just like EFI payload, we can create a generic coreboot payload
for all x86 boards as well. The payload is configured to include
as many generic drivers as possible. All stuff that touches low
level initialization are not allowed as such is the coreboot's
responsibility. Platform specific drivers (like gpio, spi, etc)
are not included.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
After some thought, I believe there is an unfortunate naming flaw in
binman. Entries have a position and size, but now that we support
hierarchical sections it is unclear whether a position should be an
absolute position within the image, or a relative position within its
parent section.
At present 'position' actually means the relative position. This indicates
a need for an 'image position' for code that wants to find the location of
an entry without having to do calculations back through parents to
discover this image position.
A better name for the current 'position' or 'pos' is 'offset'. It is not
always an absolute position, but it is always an offset from its parent
offset.
It is unfortunate to rename this concept now, 18 months after binman was
introduced. However I believe it is the right thing to do. The impact is
mostly limited to binman itself and a few changes to in-tree users to
binman:
tegra
sunxi
x86
The change makes old binman definitions (e.g. downstream or out-of-tree)
incompatible if they use the 'pos = <...>' property. Later work will
adjust binman to generate an error when it is used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some times gcc may generate data that is then used within code that may
be part of an efi runtime section. That data could be jump tables,
constants or strings.
In order to make sure we catch these, we need to ensure that gcc emits
them into a section that we can relocate together with all the other
efi runtime bits. This only works if the -ffunction-sections and
-fdata-sections flags are passed and the efi runtime functions are
in a section that starts with ".text".
Up to now we had all efi runtime bits in sections that did not
interfere with the normal section naming scheme, but this forces
us to do so. Hence we need to move the efi_loader text/data/rodata
sections before the global *(.text*) catch-all section.
With this patch in place, we should hopefully have an easier time
to extend the efi runtime functionality in the future.
Signed-off-by: Alexander Graf <agraf@suse.de>
[agraf: Fix x86_64 breakage]
We need to know about x86 relocation definitions even in cases where
we don't officially build against the x86 target, such as with sandbox.
So let's move the x86 definitions into the common elf header, where all
other architectures already have them.
Signed-off-by: Alexander Graf <agraf@suse.de>
The wrapper #ifndef is currently missing in acpi_table.h. Add it to
prevent it from being included multiple times.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
write_acpi_tables() currently touches ACPI hardware to switch to
ACPI mode at the end. Move such operation out of this function,
so that it only does what the function name tells us.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
acpi_find_fadt(), acpi_find_wakeup_vector() and enter_acpi_mode()
are something unrelated to ACPI tables generation. Move these to
a separate library.
This also fixes several style issues reported by checkpatch in the
original codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
This converts all x86 boards over to DM sysreset.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
In preparation for the reset driver conversion, eliminate the
reset_cpu() call in the FSP init path as it's too early for the
reset driver to work.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds a reset driver for tangier processor.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
This adds full reset bit in the reset register value in the ACPI FADT
table, so that kernel can do a thorough reboot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
On x86 traditional E820 table is used to pass the memory information
to kernel. With EFI loader we can build the EFI memory map from it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies
the microcode update data block encoded in Device Tree to the bootstrap
processor but not passed to the other CPUs when multiprocessing is enabled.
If the bootstrap processor successfully performs a microcode update
from Device Tree, use the same data block for the other processors.
Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed build errors on edison and qemu-x86]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This adds the scsi command to coreboot and qemu, to be in consistent
with other x86 targets.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present in dram_init_banksize() it ignores conventional memory
above 4GB. This leads to wrong DRAM size is printed during boot.
Remove such limitation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since commit bb0bb91cf0 ("efi_stub: Use efi_uintn_t"), EFI x86
64-bit payload does not work anymore. The call to GetMemoryMap()
in efi_stub.c fails with return code EFI_INVALID_PARAMETER. Since
the payload itself is still 32-bit U-Boot, efi_uintn_t gets wrongly
interpreted as int, but it should actually be long in a 64-bit EFI
environment.
This changes the x86 __kernel_size_t conditionals to use compiler
provided defines instead. That way we always adhere to the build
environment we're in and the definitions adjust automatically.
Fixes: bb0bb91cf0 ("efi_stub: Use efi_uintn_t")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For boards that don't route serial port pins out, it's quite common
to attach a USB keyboard as the input device, along with a monitor.
However USB is not automatically started in the generic efi payload
codes. This uses a payload specific last_stage_init() to start the
USB bus, so that a USB keyboard can be used on the U-Boot shell.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
car.o can only be used with start.o, not with start64.o.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Follow Linux commit 10b62a2f785a (".gitignore: move *.dtb and *.dtb.S
patterns to the top-level .gitignore").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently when EFI application boots, it says:
CPU: x86_64, vendor <invalid cpu vendor>, device 0h
Fix this by calling x86_cpu_init_f() in arch_cpu_init().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To avoid confusion, let's rename the efi-x86 target to efi-x86_app.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This turns on the EFI framebuffer driver support so that a graphics
console can be of additional help.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that we have generic EFI payload support, drop EFI-specific test
logics in BayTrail Kconfig and codes, and all BayTrail boards too.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that we have generic EFI payload support for all x86 boards,
drop the QEMU-specific one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It is possible to create a generic EFI payload for all x86 boards.
The payload is configured to include as many generic drivers as
possible. All stuff that touches low-level initialization are not
allowed as such is the EFI BIOS's responsibility. Platform specific
drivers (like gpio, spi, etc) are not included.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds arch_cpu_init() to the payload codes, in preparation for
supporting a generic efi payload.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present the EFI application and payload support codes in the x86
directory is distributed in a hybrid way. For example, the Kconfig
options for both app and payload are in arch/x86/lib/efi/Kconfig,
but the source codes in the same directory get built only for
CONFIG_EFI_STUB.
This refactors the codes by consolidating all the EFI support codes
into arch/x86/cpu/efi, just like other x86 targets.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
UEFI specifies the calling convention used in Microsoft compilers;
first arguments of a function are passed in (%rcx, %rdx, %r8, %r9).
All other compilers use System V ABI by default, passing first integer
arguments of a function in (%rdi, %rsi, %rdx, %rcx, %r8, %r9).
These ABI also specify different sets of registers that must be preserved
across function calls (callee-saved).
GCC allows using the Microsoft calling convention by adding the ms_abi
attribute to a function declaration.
Current EFI implementation in U-Boot specifies EFIAPI for efi_main()
in the test apps but uses default calling convention in lib/efi.
Save efi_main() arguments in the startup code on x86_64;
use EFI calling convention for _relocate() on x86_64;
consistently use EFI calling convention for efi_main() everywhere.
Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Fix warning when compiling cherryhill.dts with latest DTC:
"Warning (avoid_unnecessary_addr_size): /pci/pch@1f,0: unnecessary
#address-cells/#size-cells without "ranges" or child "reg" property"
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add Panther Point chipset interrupt pin/PIRQ information, and
enable the generation of PIRQ routing table and MP table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently both pirq_reg_to_linkno() and pirq_linkno_to_reg() assume
consecutive PIRQ routing control registers. But this is not always
the case on some platforms. Introduce a new device tree property
intel,pirq-regmap to describe how the PIRQ routing register offset
is mapped to the link number and adjust the irq router driver to
utilize the mapping.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The "intel,pirq-link" property in Intel IRQ router's dt bindings
has two cells, where the second one represents the number of PIRQ
links on the platform. However current driver does not parse this
information from device tree. This adds the codes to do the parse
and save it for future use.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Attempting to use a toolchain that is preconfigured to generate code
for the 32-bit architecture (i386), for example, the i386-linux-gcc
toolchain on kernel.org, to compile the 64-bit EFI payload does not
build. This updates the makefile fragments to ensure '-m64' is passed
to toolchain when building the 64-bit EFI payload stub codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The pinctrl_ich6 driver is currently unconditionally built for all
x86 boards. Let's use a Kconfig option to control the build.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
LINK_V2N and LINK_N2V are currently defines, so they cannot handle
complex logics. Change to inline functions for future extension.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present there are 3 irq router drivers. One is the common one
and the other two are chipset specific for queensbay and quark.
However these are really the same drivers as the core logic is
the same. The two chipset specific drivers configure some registers
that are outside the irq router block which should really be part
of the chipset initialization.
Now we remove these specific drivers and make all x86 boards use
the common one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This enables the 206ax cpu driver on Intel Cougar Canyon 2 board,
so that SMP can be supported too.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The 206ax cpu driver does not require pre-relocation flag to work.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present this 206ax cpu driver is only built when FSP is not used.
This updates the Makefile to enable the build for both cases.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It turns out that like Braswell, Intel FSP for IvyBridge requires
SPI controller settings to be locked down, as the U-Boot ICH SPI
driver fails with the following message on Cougar Canyon 2 board:
"ICH SPI: Opcode 9f not found"
Update the SPI node property to indicate this fact.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The Panther Point chipset connected to Ivybridge has xHC integrated,
imply it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The guaranteed vid bit ranges in IACORE_VIDS MSR is actually
[22:16]. This corrects the comment for it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This undocumented function relies on arch-specific code to declare a nop
weak version. Add the weak function in common code instead to avoid having
to duplicate the same function in each arch.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
The efi selftest and the hello application require CRT0 and RELOC to be
built.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Variables EFI_RELOC and EFI_CRT0 have to be defined to build the
EFI unit tests. This patch ensures this for the x86 architecure.
If we compile with EFI_STUB, the bitness depends on CONFIG_EFI_STUB_64BIT.
Otherwise the bitness depends on CONFIG_X86_64.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
x86 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().
This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have multiple licenses (in
these cases, dual license) declared in the SPDX-License-Identifier tag.
In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A
or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B"
as per the Linux Kernel style document. Note that parenthesis are
allowed so when they were used before we continue to use them.
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.
Signed-off-by: Tom Rini <trini@konsulko.com>
If CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set, don't switch
graphics card to VESA mode. This applies to both native mode
and emulator mode of running the VGA BIOS.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This changes 'struct e820entry' to 'struct e820_entry' to conform
with the coding style.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
This fixes the following checkpatch warning:
warning: Prefer 'unsigned int' to bare use of 'unsigned'
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
The commit 3f70a6f577 ("x86: Add clr/setbits functions")
introduced the {read|write}_ macros to manipulate data.
Those macros are not used by any code in the u-boot project (despite the
io.h itself). Other architectures use io.h with {in|out}_* macros.
This commit brings some unification across u-boot supported architectures.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add readq() and writeq() definitions for x86.
Please note: in 32-bit code readq/writeq will generate two 32-bit
memory access instructions instead of one atomic 64-bit operation.
Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The portable executable header has a field describing the machine type.
The machine type should match the binary. So on i386 we should use
IMAGE_FILE_MACHINE_I386 and on x86_64 we should use
IMAGE_FILE_MACHINE_AMD64. The actual value is issued by the objcopy
command invoked in scripts/Makefile.lib in depdendence of the value of
EFI_TARGET.
The value is used both for EFI_STUB and for EFI_LOADER.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
On x86 platforms, U-Boot does not pass Device Tree data to the kernel.
This prevents the kernel from using FDT loaded by U-Boot.
Read the working FDT address from the "fdtaddr" environment variable
and add a copy of the FDT data to the kernel setup_data list.
Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add #include <linux/libfdt.h> to zimage.c to fix build error]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Merge init_helpers.h in the new file init.h
with only prototypes for init_cache_f_r
used in common/board_f.c
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.
This commit moves the header code:
include/libfdt.h -> include/linux/libfdt.h
include/libfdt_env.h -> include/linux/libfdt_env.h
and replaces include directives:
#include <libfdt.h> -> #include <linux/libfdt.h>
#include <libfdt_env.h> -> #include <linux/libfdt_env.h>
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Only ARM and in some configs MIPS really implement arch_fixup_fdt().
Others just use the same boilerplate which is not good by itself,
but what's worse if we try to build with disabled CONFIG_CMD_BOOTM
and enabled CONFIG_OF_LIBFDT we'll hit an unknown symbol which was
apparently implemented in arch/xxx/lib/bootm.c.
Now with weak arch_fixup_fdt() right in image-fdt.c where it is
used we get both items highlighted above fixed.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The variable t_rfc is never used, so drop it. The variables ddr_wctl
and ddr_wcmd are only used in certain manual instances, so guard their
declaration by the same check as their use.
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
At present the acpi_rsdp_addr variable is directly referenced in
setup_zimage(). This changes to use an API for better encapsulation
and extension.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
New field acpi_rsdp_addr, which has been introduced in boot protocol
v2.14 [1], in boot parameters tells kernel the exact address of RDSP
ACPI table. Knowing it increases robustness of the kernel by avoiding
in some cases traversal through a part of physical memory.
It will slightly reduce boot time by the same reason.
[1] See Linux kernel commit
2f74cbf ("x86/boot: Add the ACPI RSDP address to struct setup_header::acpi_rdsp_addr")
@ https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=2f74cbf
for the details.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: updated the kernel commit git URL and fixed one style issue]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
The commit
20bfac0599 ("x86: zImage: add Intel MID platforms support")
introduced an assignment of subarch field in boot parameters, though
missed the right place of doing that. It doesn't matter if we have or
not a kernel command line supplied, we just set that field. Although
guard it by protocol version which supports it.
Fixes: 20bfac0599 ("x86: zImage: add Intel MID platforms support")
Cc: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The commit
eece493a7a ("cmd: qfw: bring ACPI generation code into qfw core")
moves ACPI related code to another file and missed an update of
references in acpi_table.c.
Do it now.
Fixes: eece493a7a ("cmd: qfw: bring ACPI generation code into qfw core")
Cc: Miao Yan <yanmiaobest@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
ASL compiler warns:
ASL board/intel/edison/dsdt.asl
board/intel/edison/dsdt.asl.tmp 238: Method (_CRS, 0, NotSerialized)
Remark 2120 - Control Method should be made Serialized ^ (due to creation of named objects within)
Do as suggested by ASL compiler.
Fixes: 5d8c4ebd95 ("x86: tangier: Add Bluetooth to ACPI table")
Reported-by: Ferry Toth <fntoth@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
As defined on reference board followed by Intel Edison a Bluetooth
device is attached to HSU0, i.e. PCI 0000:04.1.
Describe it in ACPI accordingly.
Note, we use BCM2E95 ID here as one most suitable for such device based
on the description in commit message of commit 89ab37b489d1
("Bluetooth: hci_bcm: Add support for BCM2E95 and BCM2E96")
in the Linux kernel source tree.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The recent commit 03c4749dd6c7
("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation")
in the Linux kernel reveals the issue we have in ACPI tables here,
i.e. we must use hardware numbers for GPIO resources and,
taking into consideration that GPIO and pin control are *different* IPs
on Intel Tangier, we need to supply numbers properly.
Besides that, it improves user experience since the official documentation
for Intel Edison board is referring to GPIO hardware numbering scheme.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We only need to compile and link these files when building for full
U-Boot. Move them to under cmd/x86/ to make sure they aren't linked in
and undiscarded due to u_boot_list_2_cmd_* being included).
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
FLIS IP since now gets its own ACPI ID.
Drop PRP0001 workaround in favour of official ACPI HID.
Corresponding kernel commit dabd4bc6de2b
pinctrl: intel: merrifield: Introduce ACPI device table
in the pin control subsystem tree [1] targeting v4.16.
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/commit/?h=for-next&id=dabd4bc6de2b
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
This patch removes the inclusion of the libgcc math functions and
replaces them by functions coded in C, taken from the coreboot
project. This makes U-Boot building more independent from the toolchain
installed / available on the build system.
The code taken from coreboot is authored from Vadim Bendebury
<vbendeb@chromium.org> on 2014-11-28 and committed with commit
ID e63990ef [libpayload: provide basic 64bit division implementation]
(coreboot git repository located here [1]).
I modified the code so that its checkpatch clean without any
functional changes.
[1] git://github.com/coreboot/coreboot.git
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This reverts commit 13c531e52a.
The error message with FIT style image mentioned in the above commit
only happens when booting using FIT image containing bzImage kernel
and without setup node (setup.bin). The current documentation for
x86 FIT support in doc/uImage.FIT/x86-fit-boot.txt mentions that
kernel's setup.bin file is required for building x86 FIT images.
The above commit breaks FIT images generated as described in the
documentation. Revert it to allow booting with images built in the
documented way.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
x86_vendor_name is defined as
static const char *const x86_vendor_name[]
So its elements should not be compared to 0.
Remove superfluous paranthesis.
Problem identified with Coccinelle.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
ROM has been made read-only in qemu recently (namely commit 208fa0e4:
"pc: make 'pc.rom' readonly when machine has PCI enabled"). So this
patch restores compatibility between U-Boot and qemu.
Signed-off-by: Anton Gerasimov <anton@advancedtelematic.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: mention qemu commit title in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Currently, pylibfdt is always compiled if swig is installed on your
machine. It is really annoying because most of targets (excepts
x86, sunxi, rockchip) do not use dtoc or binman.
"checkbinman" and "checkdtoc" are wrong. It is odd that the final
build stage checks if we have built necessary tools. If your platform
depends on dtoc/binman, you must be able to build pylibfdt. If swig
is not installed, it should fail immediately.
I added PYLIBFDT, DTOC, BINMAN entries to Kconfig. They should be
property select:ed by platforms that need them. Kbuild will descend
into scripts/dtc/pylibfdt/ only when CONFIG_PYLIBFDT is enabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The supported sleep states are generic on Intel processors. Move the
ASL definition to the common place.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
On some platforms (eg: Braswell), the FSP will not produce the
graphics info HOB unless you plug some cables to the display
interface (eg: HDMI) on the board. Add such notes in the FSP
video driver.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Intel Braswell FSP requires SPI controller settings to be locked down,
let's do this in the chrryhill.dts and remove previous Kconfig option.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This reverts commit 1e6ebee667.
It's not appropriate to call the Intel SPI driver specific stuff in
the FSP codes. We may add a simple DTS property "intel,spi-lock-down"
and let the Intel SPI driver call these stuff instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
In an S3 resume path, MRC cache is mandatory. Enforce the dependency
in the Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Imply does not work for a Kconfig choice. Update ENV_IS_IN_SPI_FLASH
to be the default one for Intel Braswell.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It was observed that when booting Linux kernel on Intel Cherry Hill
board, unexpected crash happens quite randomly. Sometimes kernel
just oops, while sometimes kernel throws MCE errors and hangs:
mce: [Hardware Error]: Machine check events logged
mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 4: c400000000010151
mce: [Hardware Error]: TSC 0 ADDR 130f3f2c0
mce: [Hardware Error]: PROCESSOR 0:406c3 TIME 1508160686 SOCKET 0 APIC 0 microcode 363
This looks like a hardware error per mcelog. After debugging, it
seems turning off turbo mode on the processor does not expose this
behavior, although U-Boot runs OK with turbo mode on. Suspect it is
related to an errata of Braswell processor.
To fix this, remove the Braswell cpu driver which does the turbo
mode configuration, and switch to use the generic cpu-x86 driver.
Also there is a configuration option in the FSP that turns on the
turbo mode and that has been turned off too.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Azalia configuration may be different across boards, hence it's not
appropriate to do that in the SoC level. Instead, let's make the
SoC update_fsp_azalia_configs() routine as a weak version, and do
the actual work in the board codes.
So far it seems only som-db5800-som-6867 board enables the Azalia.
Move the original codes into som-db5800-som-6867.c.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
At present we directly pass the Azalia config pointer to the FSP UPD.
This updates to use a function to do the stuff, like Braswell does.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
So far there are two copies of Azalia struct defines with one in
baytrail and the other one in braswell. This consolidates these
two into one, put it in the common place, and remove the prefix
pch_ to these structs to make their names more generic.
This also corrects reset_wait_timer from us to ms.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This is only needed when graphics console is used. For kernel with
native graphics driver, this can be turned off to speed up.
Change this option's default to n in the Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
It was observed that when booting a Ubuntu 16.04 kernel, doing ACPI
S3 suspend/resume sometimes causes the Ubuntu kernel hang forever.
The issue is however not reproduced with a kernel built from i386/
x86_64 defconfig configuration.
The unstability is actually caused by unexpected interrupts being
generated during the S3 resume. For some unknown reason, FSP (gold4)
for BayTrail configures the GPIO DFX5 PAD to enable level interrupt
(bit 24 and 25). As this pin keeps generating interrupts during an
S3 resume, and there is no IRQ requester in the kernel to handle it,
the kernel seems to hang and does not continue resuming.
Clear the mysterious interrupt bits for this pin.
Reported-by: Stefan Roese <sr@denx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Intel Tangier SoC is a part of Intel Merrifield platform which doesn't
utilize ACPI by default. Here is an attempt to unleash ACPI flexibility
power on Intel Merrifield based platforms.
The change brings minimum support of the devices that found on
Intel Merrifield based end user device.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
U-Boot widely uses error() as a bit noisier variant of printf().
This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:
# define __compiletime_error(message) __attribute__((error(message)))
This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux. (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)
Let's convert error() into now treewide-available pr_err().
Done with the help of Coccinelle, excluing tools/ directory.
The semantic patch I used is as follows:
// <smpl>
@@@@
-error
+pr_err
(...)
// </smpl>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>
Convert the x86 architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for x86 this is primarily a matter of moving code.
This has only been build-tested, feedback from architecture maintainers
is welcome.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
legacy_hole_base_k and legacy_hole_size_k are defined but
not used.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With bootstage we need access to the timer before driver model is set up.
To handle this, put the required state in global_data and provide a new
function to set up the device, separate from the driver's probe() method.
This will be used by the 'early' timer also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This adds support to Intel Cherry Hill board, a board based on
Intel Braswell SoC. The following devices are validated:
- serial port as the serial console
- on-board Realtek 8169 ethernet controller
- SATA AHCI controller
- EMMC/SDHC controller
- USB 3.0 xHCI controller
- PCIe x1 slot with a graphics card
- ICH SPI controller with an 8MB Macronix SPI flash
- Integrated graphics device as the video console
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
FSP's built-in UPD configuration enables PUNIT power configuration,
but on B0 stepping, this causes CPU hangs in fsp_init(). Disable it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds microcode device tree fragment for Braswell B0 (406C2),
C0 (406C3) and D0 (406C4) stepping SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.
Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
FSP spec 1.1 adds 3 new APIs and their offsets are in the header.
Update the 'fsp hdr' command to show these new entries.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When a VBT is given to an FSP that supports graphics initialization,
the FSP will produce a graphics info HOB that contains all necessary
information for the linear frame buffer of the integrated graphics
device. This adds a DM video driver for it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that binman is able to recognize the Video BIOS Table entry,
add such one in the u-boot.dtsi.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds Kconfig options for Video BIOS Table which is normally
required if you are using an Intel FSP firmware that is complaint
with spec 1.1 or later to initialize the integrated graphics device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds a new HOB type for graphics information introduced in FSP
spec 1.1. When graphics capability is included in FSP and enabled,
FSP produces an FSP_GRAPHICS_INFO_HOB as described in the EFI PI
specification which provides information about the graphics mode and
framebuffer.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
FSP spec 1.1 adds one more member to the struct common_buf to
determine the memory size that can be reserved by FSP below "top
of low usable memory" for bootloader usage. This new member uses
the reserved space so that it is still compatible with previous
FSP spec 1.0.
A new HOB (FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID) is also
published when common_buf.tolum_size is valid and non zero.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Import include/linux/dma-direction.h from Linux 4.13-rc7 and delete
duplicated definitions of enum dma_data_direction.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
It was noticed a few times, that the reboot from Linux (reboot command)
is different from the reboot (reset command) under U-Boot. The U-Boot
version does seem to reset the board more deeply (PCI cards etc) than
the Linux reboot.
This is actually caused by missing full reset bit in the reset register
value in the ACPI FADT table.
Reported-by: Stefan Roese <sr@denx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
These options should not be exposed to other platforms.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.
This introduces a Kconfig option CONFIG_FSP_LOCKDOWN_SPI for such
FSPs. When it is on, U-Boot will configure the SPI opcode registers
before the lock-down.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.
Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.
Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we support multiple environment drivers but there is not way to
select between them at run time. Also settings related to the position and
size of the environment area are global (i.e. apply to all locations).
Until these limitations are removed we cannot really support more than one
environment location. Adjust the location to be a choice so that only one
can be selected. By default the environment is 'nowhere', meaning that the
environment exists only in memory and cannot be saved.
Also expand the help for the 'nowhere' option and move it to the top since
it is the default.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Move all of the imply logic to default X if Y so it works again]
Signed-off-by: Tom Rini <trini@konsulko.com>
When CONFIG_EFI_PARTITION is not set, the following build error is
seen in arch/x86/lib/acpi_s3.c:
error: expected declaration specifiers or '...' before '*' token
static void asmlinkage (*acpi_do_wakeup)(void *vector) = (void*)WAKEUP_BASE;
This is actually caused by missing asmlinkage declaration, but with
CONFIG_EFI_PARTITION on, the declaration comes from part.h which
is included from common.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Neither new design uses ISA bus, nor does any U-Boot codes use these
codes. Remove them.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
After MMC is converted to DM, convert to use DM SCSI as well for all
x86 boards and imply BLK for both MMC and SCSI drivers.
CONFIG_SCSI_DEV_LIST is no longer used. Clean them up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert the pci_mmc driver over to driver model and migrate all x86 boards
that use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove DM_MMC from edison_defconfig]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
The value of uma_memory_size depends on an undefined value
from the stack. The value of uma_memory_size is changed but
never used.
So simply remove this superfluous code.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This converts Intel ICH6 GPIO driver to Kconfig, and add it to the
imply list of platform drivers.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Like other peripheral drivers, move USB related drivers to platform
Kconfig as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Imply Tangier-specific drivers in the platform Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
U-Boot as coreboot payload can run on any x86 hardware ideally.
Let's imply some common drivers that are useful.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Imply drivers that are working with Ivybridge platform in the
platform Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
BayTrail integrates lots of peripherals that have U-Boot drivers.
Imply those in the platform Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Platform knows whether MRC cache is implemented, but using it can
be a choice of a specific board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is architecture-dependent early initialization hence should
be put in the platform Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
arch_misc_init() is intended to do architecture-dependent stuff.
This is required by each platform.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
CONFIG_BOARD_EARLY_INIT_F literally indicates board-specific codes
and should be not 'default y' for all x86 boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Intel Management Engine is required by the platform, however it's
not a must have when building a U-Boot image. For example, during
development normally programming ME firmware is a one-time effort.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some firmwares might have another window for generated tables.
So, introduce two configuration options to select start address and
maximum length for the generated tables.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
64-bit U-Boot image is a combination of 32-bit U-Boot (SPL) plus
64-bit U-Boot (proper). For the U-Boot proper, it has be compiled
to 64-bit object codes. Attempting to use a toolchain to compile
64-bit U-Boot for qemu-x86_64, like kernel.org 4.9 i386-linux-gcc,
fails with the following errors:
arch/x86/cpu/intel_common/microcode.c:79:2: error: PIC register
clobbered by 'ebx' in 'asm'
The issue is because toolchain is preconfigured to generate code
for the 32-bit architecture (i386), and currently '-m64' is missing
in the makefile fragment. Using kernel.org 4.9 x86_64-linux-gcc
works out of the box, since it is preconfigured to generate 64-bit
codes.
When compiling U-Boot SPL, '-m32' is passed to the toolchain, no
mater 32-bit (i386-linux-) or 64-bit (x86_64-linux) the toolchain
is preconfigured to generate.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present U-Boot x86 build is using -mpreferred-stack-boundary=2
which is 4 bytes stack boundary alignment. With 64-bit U-Boot, the
minimal required stack boundary alignment is 16 bytes.
If -mpreferred-stack-boundary is not specified, the default is 4
(16 bytes). Switch to use the default one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present the AHCI SCSI driver only supports PCI with driver model.
Rename the existing function to indicate this and add support for adding
a non-PCI controller .
Signed-off-by: Simon Glass <sjg@chromium.org>
If ACPI HW reduced bit in FADT is set we should ignore any ACPI hardware
communications.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some platforms might require different approach when filling memory
mappings configuration table.
Allow them to override the common method.
At the same time export acpi_create_mcfg_mmconfig().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
In Baytrail and Quark support code acpi_fill_madt() is identical.
Deduplicate its implementation by moving to lib/acpi_tables.c.
At the same time mark acpi_fill_madt() with __weak attribute to keep a
possibility to override it in platform code
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
ACPI specification defines FADT fields marked as reserved in U-Boot.
Name these fields in accordance with ACPI specification.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fill OEM revision field in the tables by U-Boot build date.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Change from EHCI to xHCI on the DFI BayTrail SoM.
The xHCI USB hub is connected to an GPIO on the DFI BayTrail SoM. For
correct operation, it needs to get reset upon power-up. Otherwise it
may happen that the hub is not detected after a software reboot. This
patch also configures this GPIO in the dts for correct operation.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add Intel Edison board which is using U-Boot.
The patch is based on work done by the following people (in alphabetical
order):
Aiden Park <aiden.park@intel.com>
Dukjoon Jeon <dukjoon.jeon@intel.com>
eric.park <eric.park@intel.com>
Fabien Chereau <fabien.chereau@intel.com>
Felipe Balbi <felipe.balbi@linux.intel.com>
Scott D Phillips <scott.d.phillips@intel.com>
Sebastien Colleur <sebastienx.colleur@intel.com>
Steve Sakoman <steve.sakoman@intel.com>
Vincent Tinelli <vincent.tinelli@intel.com>
In case we're building for Intel Edison, we must have 4096 bytes of
zeroes in the beginning on u-boot.bin. This is done in
board/intel/edison/config.mk.
First run sets hardware_id environment variable which is read from
System Controller Unit (SCU).
Serial number (serial# environment variable) is generated based on eMMC
CID.
MAC address on USB network interface is unique to the board but kept the
same all over the time.
Set mac address from U-Boot using following scheme:
OUI = 02:00:86
next 3 bytes of MAC address set from eMMC serial number
This allows to have a unique mac address across reboot and flashing.
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[bmeng: Add MAINTAINERS file for Intel Edison board]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Add Intel Tangier SoC support.
Intel Tangier SoC is a core part of Intel Merrifield platform. For
example, Intel Edison board is based on such platform.
The patch is based on work done by the following people (in alphabetical
order):
Aiden Park <aiden.park@intel.com>
Dukjoon Jeon <dukjoon.jeon@intel.com>
eric.park <eric.park@intel.com>
Fabien Chereau <fabien.chereau@intel.com>
Scott D Phillips <scott.d.phillips@intel.com>
Sebastien Colleur <sebastienx.colleur@intel.com>
Steve Sakoman <steve.sakoman@intel.com>
Vincent Tinelli <vincent.tinelli@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Some cross-platform drivers rely on this header present.
Make it so for x86.
It's just a copy'n'paste of arch/arm/include/asm/dma-mapping.h.
Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
BayTrail SoC supports both EHCI and xHCI controllers. However only
one host controller (either EHCI or xHCI) can be used. To enable
HSIC and SS ports, xHCI must be used. This turns on xHCI support on
Intel MinnowMax board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
As a demonstration of how to use SCSI with driver model, move link over
to use this. This patch needs more work, but illustrates the concept.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This reverts commit ddb3ac3c71.
With MMC converted to driver model, SCSI driver is broken due to
zero address access at (ops->read) in block_dread() function.
The fix (SCSI driver converted to DM) is ready in u-boot-dm branch,
but it is too late for this relese to get that in.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rather than including this arch-specific header file in common.h, include
it from within x86's u-boot.h header.
Also drop the comment about something to be fixed. It is not clear what
needs fixing.
Signed-off-by: Simon Glass <sjg@chromium.org>
First of all, it's inappropriate to call setup_internal_uart() in a
generic API fsp_init(), as CONFIG_INTERNAL_UART is an option that
is only available on BayTrail platform. Secondly even for BayTrail,
there is no need to call setup_internal_uart() at all, as Intel FSP
will do this for us.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
It was observed that when -DDEBUG is used to generate a debug build,
U-Boot does not boot on MinnowMax board. A workaround is to disable
CONFIG_DEBUG_UART. The real issue is that in order to have the debug
uart to work, BayTrail SoC needs to be configured so that its internal
uart is available to be used as the debug uart.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present lpe/lpss-sio/scc FSP properties are all boolean, but in
fact for "enable-lpe" it has 3 possible options. This adds macros
for these options and change the property from a boolean type to
an integer type, and change their names to explicitly indicate what
the property is really for.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Introduce various meaningful macros for FSP settings and switch over
to use them instead of magic numbers.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
"serial-debug-port-address" and "serial-debug-port-type" settings
are actually reserved in the FSP UPD data structure. Remove them.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The default value of "fsp,mrc-init-tseg-size" should be 1 (1MB) per
FSP default settings. 0 is not valid.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Remove 'pad-offset' of soc_gpio_s5_0, soc_gpio_s5_1, soc_gpio_s5_2,
pin_usb_host_en0 and pin_usb_host_en1. These offsets are actually
wrong. Correct value should be added by 0x2000, but since they
are supposed to be 'mode-gpio', 'pad-offset' is not needed at all.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a device-tree property use-lvl-write-cache that will cause
writes to lvl to be cached instead of read from lvl before each
write. This is required on some platforms that have the register
implemented as dual read/write (such as Baytrail).
Prior to this fix the blue USB port on the Minnowboard Max was
unusable since USB_HOST_EN0 was set high then immediately set
low when USB_HOST_EN1 was written.
This also resolves the 'gpio clear | set' command warning like:
"Warning: value of pin is still 0"
Signed-off-by: George McCollister <george.mccollister@gmail.com>
<rebased on latest origin/master, fixed all baytrail boards>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds a call to dm_remove_devices_flags() to
bootm_announce_and_cleanup() so that drivers that have one of the removal
flags set (e.g. DM_FLAG_ACTIVE_DMA_REMOVE) in their driver struct, may
do some last-stage cleanup before the OS is started.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert the pci_mmc driver over to driver model and migrate all x86 boards
that use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
U-Boot sets up the real mode interrupt handler stubs starting from
address 0x1000. In most cases, the first 640K (0x00000 - 0x9ffff)
system memory is reported as system RAM in E820 table to the OS.
(see install_e820_map() implementation for each platform). So OS
can use these memories whatever it wants.
If U-Boot is in an S3 resume path, care must be taken not to corrupt
these memorie otherwise OS data gets lost. Testing shows that, on
Microsoft Windows 10 on Intel Baytrail its wake up vector happens to
be installed at the same address 0x1000. While on Linux its wake up
vector does not overlap this memory range, but after resume kernel
checks low memory range per config option CONFIG_X86_RESERVE_LOW
which is 64K by default to see whether a memory corruption occurs
during the suspend/resume (it's harmless, but warnings are shown
in the kernel dmesg logs).
We cannot simply mark the these memory as reserved in E820 table
because such configuration makes GRUB complain: unable to allocate
real mode page. Hence we choose to back up these memories to the
place where we reserved on our stack for our S3 resume work.
Before jumping to OS wake up vector, we need restore the original
content there.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
Introduce a new CONFIG_S3_VGA_ROM_RUN option so that U-Boot can
bypass executing VGA roms in S3.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
Before jumping to OS waking up vector, we need turn on ACPI mode
for S3, just like what we do for a normal boot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
To do something more in acpi_resume() like turning on ACPI mode,
we need locate ACPI FADT table pointer first. But currently this
is done in acpi_find_wakeup_vector().
This changes acpi_resume() signature to accept ACPI FADT pointer
as the parameter. A new API acpi_find_fadt() is introduced, and
acpi_find_wakeup_vector() is updated to use FADT pointer as the
parameter as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
enter_acpi_mode() is useful on other boot path like S3 resume, so
make it public.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
In enter_acpi_mode() PM1_CNT register is changed to PM1_CNT_SCI_EN
directly without preserving its previous value. Update to change
the register access to read-modify-write (RMW).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
Call board_final_cleanup() before write_tables(), so that anything
done in board_final_cleanup() on a normal boot path is also done
on an S3 resume path.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
When SeaBIOS is being used, U-Boot reserves a memory area to be
used for configuration tables like ACPI. But it should not be
cleared otherwise ACPI table will be missing.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
At the end of pre-relocation phase, save the new stack address
to CMOS and use it as the stack on next S3 boot for fsp_init()
continuation function.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
This adds a library that provides CMOS (inside RTC SRAM) access
at a very early stage when driver model is not available yet.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
In an S3 resume path, U-Boot does everything like a cold boot except
in the last_stage_init() it jumps to the OS resume vector.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
This adds one API acpi_find_wakeup_vector() to locate OS wakeup
vector from the ACPI FACS table, to be used in the S3 boot path.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
This adds a wake up stub before jumping to OS wake up vector.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
U-Boot itself as well as everything that is consumed by U-Boot (like
heap, stack, dtb, etc) needs to be reserved and reported in the E820
table when S3 resume is on.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
When U-Boot is built without ACPI S3 support, it should not report
S3 in the ACPI table otherwise when kernel does STR it won't work.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
Add one member in the global data to store previous sleep state,
and display the state during boot in print_cpuinfo().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
When ACPI S3 resume is turned on, we should pass different boot mode
to FSP init instead of default BOOT_FULL_CONFIG.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
This adds OS_RESUME (0x40) and RESUME_FAILURE (0xed) post codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
This adds APIs for determining previous sleep state from ACPI I/O
registers, as well as clearing sleep state on BayTrail SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
This introduces a Kconfig option for ACPI S3 resume, as well as a
header file to include anything related to ACPI S3 resume.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
Rather than using CMD_CBFS for both the filesystem and its command, we
should have a separate option for each. This allows us to enable CBFS
support without the command, if desired, which reduces U-Boot's size
slightly.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply FS_CBFS on SYS_COREBOOT]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_CBFS
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: imply CMD_CBFS on SYS_COREBOOT]
Signed-off-by: Tom Rini <trini@konsulko.com>
At present on a cold reboot we must reset the CPU to get it to full speed.
With 64-bit U-Boot this happens in SPL. At present we print the banner
before doing this, the end result being that we print the banner twice.
Print the banner a little later (after the CPU is ready) to avoid this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The Intel CPU name can have leading spaces. Remove them since they are not
useful.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This simple PMU driver allows to tyrn power on and off for selected
devices. In particularly Intel Tangier needs to power on SDHCI
controllers in order to access to them during board initialization.
In the future it might be expanded to cover other Intel MID platforms,
that's why it's located under arch/x86/lib and called pmu.c.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Intel MID platforms have few microcontrollers inside SoC, one of them
is so called System Controller Unit (SCU).
Here is the driver to communicate with microcontroller.
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Simon Glass <sjg@chromium.org>
Checking 'is_zimage' at this time will always fail and therefore booting
a FIT style image will always lead to this error message:
"## Kernel loading failed (missing x86 kernel setup) ..."
This change now removes this check and booting of FIT images works just
fine.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Since we now have the file names configurable via Kconfig for the flash
descriptor and intel-me files, add these from Kconfig in the corresponding
dts nodes.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This introduces two Kconfig options to enable board specific filenames
for the Intel binary blobs to be used to generate the SPI flash image.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This header file is used by three archs. It could be used by all of them
since relocation is a common function. Move it into a generic file.
Signed-off-by: Simon Glass <sjg@chromium.org>
This header file is used by two archs. It could be used by all of them
since it allows the cache to be on during relocation. Move it into a
generic file.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is an weak function present on all archs so we should have it in the
common header file. Remove it from arch-specific headers and add a
function comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
By making dram_init_banksize() return an error code we can drop the
wrapper. Adjust this and clean up all implementations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
At present we misuse print_cpuinfo() do so CPU init on x86. This is done
because it is the next available call after the console is enabled. But
several arches use checkcpu() instead. Despite the horrible name (which
we can fix), it seems a better choice.
Adjust the various x86 CPU implementations to move their init code into
checkcpu() and use print_cpuinfo() only for printing CPU info.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
While x86 is the only user and this could in principle be moved to
arch_cpu_init() there is some justification for this being a separate
call. It provides a way to handle init which is not CPU-specific, but
must happen before the CPU can be set up.
Rename the function to be more generic.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This patch adds the flags parameter to device_remove() and changes all
calls to this function to provide the default value of DM_REMOVE_NORMAL
for "normal" device removal.
This is in preparation for the driver specific pre-OS (e.g. DMA
cancelling) remove support.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
There is no microcode update available for SoCs used on Intel MID
platforms.
Use conditional to bypass it.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel MID platform boards have special treatment, such as boot parameter
setting.
Assign hardware_subarch accordingly if CONFIG_INTEL_MID is set.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Mobile Internet Device (MID) platforms have special treatment in
some cases, such as CPU enumeration or boot parameters configuration.
Besides that several drivers are specifically developed for the IP
blocks found on Intel MID platforms. Those drivers will be dependent to
this option.
Here we introduce specific quirk option for such cases.
It is supposed to be selected by Intel MID platform boards, for example,
Intel Edison.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Depending upon the compiler used, IRQ entries could vary in sizes. With
GCC 5.x, the code generator will use short jumps for some IRQ entries
but near jumps for others. For example, GCC 5.4.0 generates the
following:
$ objdump -d interrupt.o
<snip>
00000207 <irq_18>:
207: 6a 12 push $0x12
209: eb 85 jmp 190 <irq_common_entry>
0000020b <irq_19>:
20b: 6a 13 push $0x13
20d: eb 81 jmp 190 <irq_common_entry>
0000020f <irq_20>:
20f: 6a 14 push $0x14
211: e9 7a ff ff ff jmp 190 <irq_common_entry>
00000216 <irq_21>:
216: 6a 15 push $0x15
218: e9 73 ff ff ff jmp 190 <irq_common_entry>
This causes a problem in cpu_init_interrupts(), because the IDT setup
assumed same sizes for all IRQ entries. GCC 4.x always generated 32-bit
jumps, so this previously was not a problem.
The fix is to force 32-bit near jumps for all entries within the
inline assembly. This works for GCC 5.x, and 4.x was already using
that form of jumping.
Signed-off-by: Jason Tang <tang@jtang.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: Simon Glass <sjg@chromium.org>
This option is useful not only for development, but for the platforms
where U-Boot is run from custom ROM bootloader. For example, Intel
Edison is that board.
Make this option visible that platforms can select it if needed.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
QEMU does not need ucode and this is indicated in u-boot.dtsi
for U-Boot proper. Now add the same for SPL.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add the correct pre-relocation tag so that the required device tree
nodes are present in the SPL device tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
arch_cpu_init() and print_cpuinfo() should be only available in SPL
build.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
arch_cpu_init_dm() might not be implemented by every platform.
Implement a weak version for SPL.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
DECLARE_GLOBAL_DATA_PTR is missing which causes 64-bit build error.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Update config.mk settings to support both 32-bit and 64-bit U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add the correct pre-relocation tag so that the required device tree nodes
are present in the SPL device tree.
On x86 it doesn't make a lot of sense to have a separate SPL device tree.
Since everything is in the same ROM we might as well just use the main
device tree in both SPL and U-Boot proper. But we haven't implemented that,
so this is a good first step.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When building for 64-bit we need to put an SPL binary into the image. Update
the binman image description to reflect this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't have the code for this yet. Add a dummy version for now, so that
EFI builds correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This code is only used in 32-bit mode. Move it so that it does not get
built with 64-bit U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This code is only used in 32-bit mode. Move it so that it does not get
built with 64-bit U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
To avoid using BSS in SPL before SDRAM is set up, move this field to
global_data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
To avoid using BSS in SPL before SDRAM is set up, move this field to
global_data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a rough function to handle jumping from 32-bit SPL to 64-bit U-Boot.
This still needs work to clean it up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Booting into linux from 64-bit U-Boot is not yet supported. Avoid bringing
in the bootm code until it is implemented.
Of course 32-bit U-Boot still supports booting into both 32- and 64-bit
kernels.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some files cannot be built with 64-bit and mostly don't make sense in that
context. Disable them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These are currently not supported. Calling 64-bit code from 64-bit U-Boot is
much simpler, so this code is not needed. setjmp() is not yet implemented for
64-bit.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't support SDRAM init in 64-bit mode since it is essentially
impossible to get into that mode before SDRAM set up. Provide dummy functions
for now. At some point we will need to pass the SDRAM parameters through from
SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This doesn't build at present and is not used in a 64-bit build. Disable it
for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
If SPL is used it is always build in 32-bit mode. Add a link script to
handle the correct placement of the sections.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This needs a different image format from 32-bit x86, so add a new link
script.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When SPL and U-Boot proper have different settings for this flag, we need to
use the correct one. Fix this up in the interrupt code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present this is just an ordinary variable. We may consider making it a
fixed register in the future.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
There is not much needed at present, but set up a separate directory to put
this code as it grows.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Much of the cpu and interrupt code cannot be compiled on 64-bit x86. Move it
into its own directory and build it only in 32-bit mode.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
SPL needs to set up the machine ready for loading 64-bit U-Boot and jumping
to it. Call the existing init routines in order to accomplish this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Addresses should not be cast to size_t. Use uintptr_t instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a 64-bit relocation function. SPL loads U-Boot into RAM at a fixed
address and runs it. U-Boot then relocates itself to the top of RAM using
this relocation function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Move the core relocation code into a separate function so that the checking
code can be used for 64-bit relocation also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add code to start up U-Boot in 64-bit mode. It is fairly simple since we are
running from RAM and SPL has done the low-level init.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Update the Makefile so that some 32-bit init can be built into SPL rather
than U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Use this new option to control the location of 32-bit init. This will allow
us to place this in SPL if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Use this new option to control the location of 16-bit init. This will allow
us to place this in SPL if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present all 16/32-bit init is controlled by CONFIG_X86_RESET_VECTOR. If
this is enabled, then U-Boot is the 'first' boot loader and handles execution
from the reset vector through to U-Boot's command prompt. If it is not
enabled then U-Boot starts at the 32-bit entry and skips most of its init,
assuming that the previous boot loader has done this already.
With the move to suport 64-bit operation, we have more cases to consider.
The 16-bit and 32-bit init may be in SPL rather than in U-Boot proper.
Add Kconfig options which control the location of the 16-bit and the 32-bit
init. These are not intended to be user-setting except for experimentation.
Their values should be determined by whether 64-bit U-Boot is used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a new CONFIG_X86_64 option which will eventually cause U-Boot to be
built as a 64-bit application, with SPL doing the 16/32-bit init.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fix a cast in get_next_hob() that causes warnings on 64-bit machines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We almost always need the serial port before relocation, so mark it as such.
This will ensure that it appears in the device tree for SPL, if used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add various debug() messages in places where errors occur. This aids with
debugging.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some files are missing this declaration. Add it to avoid build errors when
we actually need the declaration.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present this uses u32 to store an address. We should use unsigned long
and avoid special types in function return values and parameters unless
necessary. This makes the code more portable.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We should use unsigned long rather than u32 for addresses. Update this so
that the table-generation code builds correctly on 64-bit machines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Basically rename X86_SUBARCH_MRST to X86_SUBARCH_INTEL_MID to be more specific.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Since we already have a bunch of Kconfig options for CMC/FSP/VGA file
names, add these from Kconfig in the corresponding dts nodes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the conversion to use binman to build x86 boards, Intel Galileo
board does not build anymore due to missing ucode entry. In fact
ucode is not needed for quark-based boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change x86 boards to use binman to produce the ROM. This involves adding the
image definition to the device tree and using it in the Makefile. The
existing ifdtool features are no-longer needed.
Note that the u-boot.dtsi file is common and is used for all x86 boards which
use microcode. A separate emulation-u-boot-dtsi is used for the others.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Commit e2f88dfd2d ("libfdt: Introduce new ARCH_FIXUP_FDT option")
allows us to skip memory setup of DTB, but a problem for ARM is that
spin_table_update_dt() and psci_update_dt() are skipped as well if
CONFIG_ARCH_FIXUP_FDT is disabled.
This commit allows us to skip only fdt_fixup_memory_banks() instead
of the whole of arch_fixup_fdt(). It will be useful when we want to
use a memory node from a kernel DTB as is, but need some fixups for
Spin-Table/PSCI.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed build error for x86:
Signed-off-by: Simon Glass <sjg@chromium.org>
Today we can compile a self-contained hello world efi test binary that
allows us to quickly verify whether the EFI loader framwork works.
We can use that binary outside of the self-contained test case though,
by providing it to a to-be-tested system via tftp.
This patch separates compilation of the helloworld.efi file from
including it in the u-boot binary for "bootefi hello". It also modifies
the efi_loader test case to enable travis to pick up the compiled file.
Because we're now no longer bloating the resulting u-boot binary, we
can enable compilation always, giving us good travis test coverage.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
On ls2080 we have a separate network fabric component which we need to
shut down before we enter Linux (or any other OS). Along with that also
comes configuration of the fabric using a description file.
Today we always stop and configure the fabric in the boot script and
(again) exit it on device tree generation. This works ok for the normal
booti case, but with bootefi the payload we're running may still want to
access the network.
So let's add a new fsl_mc command that defers configuration and stopping
the hardware to when we actually exit U-Boot, so that we can still use
the fabric from an EFI payload.
For existing boot scripts, nothing should change with this patch.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
[agraf: Fix x86 build]
Add compiler flags and make a few minor adjustments to support the efi
loader.
Signed-off-by: Simon Glass <sjg@chromium.org>
[agraf: Add Kconfig dep]
Signed-off-by: Alexander Graf <agraf@suse.de>
These files now need to be in a standard place so that they can be located
by generic Makefile rules. Move them to the 'lib' directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
These files now need to be in a standard place so that they can be located
by generic Makefile rules. Move them to the 'lib' directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
There is a build warning for three x86 boards since
write_smbios_table_wrapper() is not used. Fix it.
Fixes: e824cf3f (smbios: Allow compilation on 64bit systems)
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Highlights this time around:
- Add run time service (power control) support for PSCI (fixed in v3)
- Add efi gop pointer exposure
- SMBIOS support for EFI (on ARM)
- efi pool memory unmap support (needed for 4.8)
- initial x86 efi payload support (fixed up in v2)
- various bug fixes
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2016-10-19
Highlights this time around:
- Add run time service (power control) support for PSCI (fixed in v3)
- Add efi gop pointer exposure
- SMBIOS support for EFI (on ARM)
- efi pool memory unmap support (needed for 4.8)
- initial x86 efi payload support (fixed up in v2)
- various bug fixes
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
include/tables_csum.h
Add the required pieces to support the EFI loader on x86.
Since U-Boot only builds for 32-bit on x86, only a 32-bit EFI application
is supported. If a 64-bit kernel must be booted, U-Boot supports this
directly using FIT (see doc/uImage.FIT/kernel.its). U-Boot can act as a
payload for both 32-bit and 64-bit EFI.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
The CPU udevice already has a few callbacks to retreive information
about the currently running CPUs. This patch adds a new get_vendor()
call that returns the vendor of the main CPUs.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
For SMBIOS tables we need to know the CPU family as well as CPU IDs. This
patches allocates some space for them in the cpu device and populates it
on x86.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The SMBIOS generation code passes pointers as u32. That causes the compiler
to warn on casts to pointers. This patch moves all address pointers to
uintptr_t instead.
Technically u32 would be enough for the current SMBIOS2 style tables, but
we may want to extend the code to SMBIOS3 in the future which is 64bit
address capable.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We will need the SMBIOS generation function on ARM as well going forward,
so let's move it into a non arch specific location.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We need the checksum function without all the other table functionality
soon, so let's split it out into its own C file.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bring in these functions from Linux v4.4. They will be needed for EFI loader
support.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We need the checksum function without all the other table functionality
soon, so let's split it out into its own header file.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
These have now landed upstream. The naming is different and in one case the
function signature has changed. Update the code to match.
This applies the following upstream commits by
Thierry Reding <treding@nvidia.com> :
604e61e fdt: Add functions to retrieve strings
8702bd1 fdt: Add a function to get the index of a string
2218387 fdt: Add a function to count strings
Signed-off-by: Simon Glass <sjg@chromium.org>
This should return normal errors, not device-tree errors. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Drop init_bd_struct_r() which is no-longer used. Also drop the declaration
for init_func_spi() since this is now handled by generic board init.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fix the hex case and remove unused brackets. Use ~0U instead of ~0UL to
allow compilation on 64-bit machines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present pch_power_options() has the arguments to writel() around the
wrong way. Fix this and update it to compile on 64-bit machines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Update the configuration to use the new driver. Drop the existing plumbing
code and unused header files.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Update the samus driver to avoid the direct call to the video BIOS setup.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bring in a faster memmove() from Linux 4.7. This speeds up scrolling on the
display.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Booting Linux kernel v4.7+ does not work since Linux kernel commit 974f221c
"x86/boot: Move compressed kernel to the end of the decompression buffer".
This patch adds the latest version of the setup_header struct, adding
"init_size" which is needed since this commit referenced above. With this
patch, booting Linux v4.8-rc8 does work again on x86 boards.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
With this addition, the eMMC device available on the congatec and DFI
BayTrail SoM is detected correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Creating multiple entries of "config FOO" often gives us bad
experiences. In this case, we should specify "default X86"
as platforms that want this keyboard by default.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Once we migrate to DM-based drivers, we cannot go back to legacy
ones, i.e. config options like DM_* are not user-configurable.
Make SANDBOX and X86 select DM_KEYBOARD like other platforms do.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Unlike Linux, nothing about errno.h is arch-specific in U-Boot.
As you see, all of arch/${ARCH}/include/asm/errno.h is just a
wrapper of <asm-generic/errno.h>. Actually, U-Boot does not
export headers to user-space, so we just have to care about the
consistency in the U-Boot tree.
Now all of include directives for <asm/errno.h> are gone.
Deprecate <asm/errno.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
arch_cpu_init() can be simpler by this refactoring.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There are lots of warnings when building EFI 64-bit payload.
include/asm-generic/bitops/__fls.h:17:2:
warning: left shift count >= width of type
if (!(word & (~0ul << 32))) {
^
In fact, U-Boot itself as EFI payload is running in 32-bit mode.
So BITS_PER_LONG needs to still be 32, but EFI status codes are
64-bit when booting from 64-bit EFI. Introduce EFI_BITS_PER_LONG
to bridge those status codes with U-Boot's BITS_PER_LONG.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Generally the microcode is combined into a single block only (and removed
from the device tree) when there are multiple blocks. But this is not a
requirement.
Adjust the ivybridge code to avoid assuming this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a debug() at this point to help figure out what is wrong.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher<hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This patch adds support for the BayTrail based theadorable-x86-dfi-bt700
board which uses the DFI BT700 BayTrail Qseven SoM on a custom baseboard.
The main difference to the DFI baseboard is, that it isn't equipped
with a Super IO chip and uses the internal HS SIO UART (memory mapped
PCI based) as the console UART.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This patch adds support for the DFI BayTrail BT700 QSeven SoM installed
on the DFI Q7X-151 baseboard. The baseboard is equipped with the Nuvoton
NCT6102D Super IO chip providing the UART as console.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This patch includes the following changes:
- Remove Designware I2C support from dts as its not used
- Configure SMBus PADs in dts
- Enable I2C commands and I2C support
- Configure SMSC2513 USB hub via SMBus upon startup
- Move environment location to match Minnowmax example
- Enhancement of the default environment
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This patch adds support for the SMBus block read/write functionality.
Other protocols like the SMBus quick command need to get added
if this is needed.
This patch also removed the SMBus related defines from the Ivybridge
pch.h header. As they are integrated in this driver and should be
used from here. This change is added in this patch to avoid compile
breakage to keep the source git bisectable.
Tested on a congatec BayTrail board to configure the SMSC2513 USB
hub.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Explicitly enable ILB_SERIRQ function 1 in
cfio_regs_pad_ilb_serirq_PCONF0.
Pad configuration for SERIRQ is not set to enable the SERIRQ function
after a reset though strangely, it is on initial boot.
Rebooting from Linux, reset command in u-boot and even pushing the reset
button on the development board all lead to the SERIRQ function being
disabled (address 0xfed0c560 with value of 0x2003cc80).
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
To support the BayTrail internal SIO HS UART, the internal UART clock
needs to get configured. This patch adds support for this clock
configuration which will be done, if the PCI device(s) are found.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Don't just define ARCH_DMA_MINALIGN but also CONFIG_SYS_CACHELINE_SIZE
if it's undefined. This is needed for the xhci driver to compile.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Quite a few places have a bind() method which just calls dm_scan_fdt_dev().
We may as well call dm_scan_fdt_dev() directly. Update the code to do this.
Signed-off-by: Simon Glass <sjg@chromium.org>
With the change to set up pinctrl after relocation, link fails to boot. Add
a special case in the link code to handle this.
Fixes: d8906c1f (x86: Probe pinctrl driver in cpu_init_r())
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for Advantech SOM-DB5800 with the SOM-6867 installed.
This is very similar to conga-qeval20-qa3-e3845 in that there is a
reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867)
installed.
Currently supported:
- 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on
SOM-DB5800.
- 4x USB 2.0 (EHCI)
- Video
- SATA
- Ethernet
- PCIe
- Realtek ALC892 HD Audio
Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO
HDA_SDI0 is set in DT to enable HD Audio codec.
Pin defaults for codec pin complexs are not changed.
Not supported:
- Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500)
- USB 3.0 (XHCI)
- TPM
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
If global NVS says internal UART is not enabled, hide it in the ASL
code so that OS won't see it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that platform-specific ACPI global NVS is added, pack it into
ACPI table and get its address fixed up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This introduces quark-specific ACPI global NVS structure, defined in
both C header file and ASL file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This introduces baytrail-specific ACPI global NVS structure, defined in
both C header file and ASL file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For any FSP-enabled boards that want to enable debug UART support,
setup_internal_uart() will be called, but this API is only available
on BayTrail platform. Change to wrap it with CONFIG_INTERNAL_UART.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
There are quite a number of BayTrail boards that uses an external
SuperIO chipset to provide the legacy UART. For such cases, it's
better to have a Kconfig option to enable the internal UART.
So far BayleyBay and MinnowMax boards are using internal UART as
the U-Boot console, enable this on these two boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
We have drivers for several more devices now, so drop the strings which are
no-longer used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
There is a dummy pch driver in the coreboot directory. This causes
drivers of its children fail to function due to empty ops. Remove
the whole file since it is no longer needed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present pinctrl driver gets probed in ich6_gpio driver's probe
routine, which has two issues:
- Pin's PADs only gets configured when GPIO driver is probed, which
is not done by default. This leaves the board in a partially
functional state as we must initialize PADs correctly to get
perepherals fully working.
- The probe routine of pinctrl driver is called multiple times, as
normally there are multiple GPIO controllers. It should really
be called just once.
Move the call to syscon_get_by_driver_data() from ich6_gpio driver
to cpu_init_r().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
As of today, the latest version FSP (gold4) for BayTrail misses the
PAD configuration of the SD controller's Card Detect signal. The
default PAD value for the CD pin sets the pin to work in GPIO mode,
which causes card detect status cannot be reflected by the Present
State register in the SD controller (bit 16 & bit 18 are always zero).
Add a configuration for this pin in the pinctrl node.
Note I've checked the PAD configuration for all the pins in all the
3 controllers (eMMC/SDIO/SD). Only this SDMMC3_CD_B pin does not get
initialized to correct mode by FSP. With fsp,emmc-boot-mode set to
2 (eMMC 4.1), eMMC pins are initialized to func 1, but if we set
fsp,emmc-boot-mode to 1 (auto), those pins are initialized to func 3
which is correct according to datasheet.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present all BayTrail boards configure fsp,emmc-boot-mode to 2,
which means "eMMC 4.1" per FSP documentation. However, eMMC 4.1
only shows up on some early stepping silicon of BayTrail SoC.
Newer stepping SoC integrates an eMMC 4.5 controller. Intel FSP
provides a config option fsp,emmc-boot-mode which tells FSP which
eMMC controller it initializes. Instead of hardcoded to 2, now
we change it to 1 which means "auto".
With this change, MinnowMax board (with a D0 stepping BayTrail SoC)
can see the eMMC 4.5 controller at PCI address 00.17.00 via U-Boot
'pci' command.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Without a 'reg' property, pinctrl driver probe routine fails in
its pre_probe() with a return value of -EINVAL.
Add 'reg' property for all BayTrail boards. Note for BayleyBay,
the pinctrl node is newly added.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
An accumulated length was incorrectly added to current each pass
through the loop. On system with more than 2 cores this caused a
corrupt MADT to be generated.
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
So far this is hardcoded to 2, but it should really be read
from the I/O APIC register.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
