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x86: braswell: Add FSP configuration
Add FSP related configuration for Braswell. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng
parent
e61a2687b3
commit
fffad9264a
5 changed files with 637 additions and 1 deletions
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@ -4,4 +4,4 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += braswell.o cpu.o early_uart.o
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obj-y += braswell.o cpu.o early_uart.o fsp_configs.o
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158
arch/x86/cpu/braswell/fsp_configs.c
Normal file
158
arch/x86/cpu/braswell/fsp_configs.c
Normal file
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@ -0,0 +1,158 @@
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/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <asm/fsp/fsp_support.h>
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* Override the FSP's Azalia configuration data
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*
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* @azalia: pointer to be updated to point to a ROM address where Azalia
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* configuration data is stored
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*/
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__weak void update_fsp_azalia_configs(struct azalia_config **azalia)
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{
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*azalia = NULL;
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}
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/**
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* Override the FSP's GPIO configuration data
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*
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* @family: pointer to be updated to point to a ROM address where GPIO
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* family configuration data is stored
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* @pad: pointer to be updated to point to a ROM address where GPIO
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* pad configuration data is stored
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*/
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__weak void update_fsp_gpio_configs(struct gpio_family **family,
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struct gpio_pad **pad)
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{
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*family = NULL;
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*pad = NULL;
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}
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/**
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* Override the FSP's configuration data.
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* If the device tree does not specify an integer setting, use the default
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* provided in Intel's Braswell release FSP/BraswellFsp.bsf file.
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*/
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void update_fsp_configs(struct fsp_config_data *config,
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struct fspinit_rtbuf *rt_buf)
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{
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struct upd_region *fsp_upd = &config->fsp_upd;
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struct memory_upd *memory_upd = &fsp_upd->memory_upd;
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struct silicon_upd *silicon_upd = &fsp_upd->silicon_upd;
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const void *blob = gd->fdt_blob;
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int node;
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/* Initialize runtime buffer for fsp_init() */
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rt_buf->common.stack_top = config->common.stack_top - 32;
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rt_buf->common.boot_mode = config->common.boot_mode;
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rt_buf->common.upd_data = &config->fsp_upd;
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node = fdt_node_offset_by_compatible(blob, 0, "intel,braswell-fsp");
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if (node < 0) {
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debug("%s: Cannot find FSP node\n", __func__);
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return;
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}
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node = fdt_node_offset_by_compatible(blob, node,
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"intel,braswell-fsp-memory");
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if (node < 0) {
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debug("%s: Cannot find FSP memory node\n", __func__);
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return;
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}
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/* Override memory UPD contents */
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memory_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node,
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"fsp,mrc-init-tseg-size", MRC_INIT_TSEG_SIZE_4MB);
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memory_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node,
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"fsp,mrc-init-mmio-size", MRC_INIT_MMIO_SIZE_2048MB);
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memory_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
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"fsp,mrc-init-spd-addr1", 0xa0);
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memory_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node,
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"fsp,mrc-init-spd-addr2", 0xa2);
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memory_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node,
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"fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_32MB);
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memory_upd->aperture_size = fdtdec_get_int(blob, node,
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"fsp,aperture-size", APERTURE_SIZE_256MB);
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memory_upd->gtt_size = fdtdec_get_int(blob, node,
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"fsp,gtt-size", GTT_SIZE_1MB);
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memory_upd->legacy_seg_decode = fdtdec_get_bool(blob, node,
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"fsp,legacy-seg-decode");
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memory_upd->enable_dvfs = fdtdec_get_bool(blob, node,
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"fsp,enable-dvfs");
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memory_upd->memory_type = fdtdec_get_int(blob, node,
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"fsp,memory-type", DRAM_TYPE_DDR3);
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memory_upd->enable_ca_mirror = fdtdec_get_bool(blob, node,
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"fsp,enable-ca-mirror");
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node = fdt_node_offset_by_compatible(blob, node,
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"intel,braswell-fsp-silicon");
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if (node < 0) {
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debug("%s: Cannot find FSP silicon node\n", __func__);
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return;
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}
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/* Override silicon UPD contents */
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silicon_upd->sdcard_mode = fdtdec_get_int(blob, node,
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"fsp,sdcard-mode", SDCARD_MODE_PCI);
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silicon_upd->enable_hsuart0 = fdtdec_get_bool(blob, node,
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"fsp,enable-hsuart0");
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silicon_upd->enable_hsuart1 = fdtdec_get_bool(blob, node,
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"fsp,enable-hsuart1");
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silicon_upd->enable_azalia = fdtdec_get_bool(blob, node,
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"fsp,enable-azalia");
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if (silicon_upd->enable_azalia)
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update_fsp_azalia_configs(&silicon_upd->azalia_cfg_ptr);
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silicon_upd->enable_sata = fdtdec_get_bool(blob, node,
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"fsp,enable-sata");
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silicon_upd->enable_xhci = fdtdec_get_bool(blob, node,
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"fsp,enable-xhci");
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silicon_upd->lpe_mode = fdtdec_get_int(blob, node,
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"fsp,lpe-mode", LPE_MODE_PCI);
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silicon_upd->enable_dma0 = fdtdec_get_bool(blob, node,
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"fsp,enable-dma0");
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silicon_upd->enable_dma1 = fdtdec_get_bool(blob, node,
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"fsp,enable-dma1");
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silicon_upd->enable_i2c0 = fdtdec_get_bool(blob, node,
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"fsp,enable-i2c0");
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silicon_upd->enable_i2c1 = fdtdec_get_bool(blob, node,
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"fsp,enable-i2c1");
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silicon_upd->enable_i2c2 = fdtdec_get_bool(blob, node,
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"fsp,enable-i2c2");
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silicon_upd->enable_i2c3 = fdtdec_get_bool(blob, node,
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"fsp,enable-i2c3");
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silicon_upd->enable_i2c4 = fdtdec_get_bool(blob, node,
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"fsp,enable-i2c4");
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silicon_upd->enable_i2c5 = fdtdec_get_bool(blob, node,
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"fsp,enable-i2c5");
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silicon_upd->enable_i2c6 = fdtdec_get_bool(blob, node,
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"fsp,enable-i2c6");
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#ifdef CONFIG_HAVE_VBT
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silicon_upd->graphics_config_ptr = CONFIG_VBT_ADDR;
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#endif
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update_fsp_gpio_configs(&silicon_upd->gpio_familiy_ptr,
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&silicon_upd->gpio_pad_ptr);
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silicon_upd->emmc_mode = fdtdec_get_int(blob, node,
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"fsp,emmc-mode", EMMC_MODE_PCI);
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silicon_upd->sata_speed = fdtdec_get_int(blob, node,
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"fsp,sata-speed", SATA_SPEED_GEN3);
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silicon_upd->pmic_i2c_bus = fdtdec_get_int(blob, node,
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"fsp,pmic-i2c-bus", 0);
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silicon_upd->enable_isp = fdtdec_get_bool(blob, node,
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"fsp,enable-isp");
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silicon_upd->isp_pci_dev_config = fdtdec_get_int(blob, node,
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"fsp,isp-pci-dev-config", ISP_PCI_DEV_CONFIG_2);
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silicon_upd->turbo_mode = fdtdec_get_bool(blob, node,
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"fsp,turbo-mode");
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silicon_upd->pnp_settings = fdtdec_get_int(blob, node,
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"fsp,pnp-settings", PNP_SETTING_POWER_AND_PERF);
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silicon_upd->sd_detect_chk = fdtdec_get_bool(blob, node,
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"fsp,sd-detect-chk");
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}
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89
arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
Normal file
89
arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
Normal file
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@ -0,0 +1,89 @@
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/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSP_CONFIGS_H__
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#define __FSP_CONFIGS_H__
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#ifndef __ASSEMBLY__
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struct fsp_config_data {
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struct fsp_cfg_common common;
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struct upd_region fsp_upd;
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};
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struct fspinit_rtbuf {
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struct common_buf common; /* FSP common runtime data structure */
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};
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#endif
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/* FSP user configuration settings */
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#define MRC_INIT_TSEG_SIZE_1MB 1
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#define MRC_INIT_TSEG_SIZE_2MB 2
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#define MRC_INIT_TSEG_SIZE_4MB 4
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#define MRC_INIT_TSEG_SIZE_8MB 8
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#define MRC_INIT_MMIO_SIZE_1024MB 0x400
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#define MRC_INIT_MMIO_SIZE_1536MB 0x600
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#define MRC_INIT_MMIO_SIZE_2048MB 0x800
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#define IGD_DVMT50_PRE_ALLOC_32MB 0x01
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#define IGD_DVMT50_PRE_ALLOC_64MB 0x02
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#define IGD_DVMT50_PRE_ALLOC_96MB 0x03
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#define IGD_DVMT50_PRE_ALLOC_128MB 0x04
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#define IGD_DVMT50_PRE_ALLOC_160MB 0x05
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#define IGD_DVMT50_PRE_ALLOC_192MB 0x06
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#define IGD_DVMT50_PRE_ALLOC_224MB 0x07
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#define IGD_DVMT50_PRE_ALLOC_256MB 0x08
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#define IGD_DVMT50_PRE_ALLOC_288MB 0x09
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#define IGD_DVMT50_PRE_ALLOC_320MB 0x0a
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#define IGD_DVMT50_PRE_ALLOC_352MB 0x0b
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#define IGD_DVMT50_PRE_ALLOC_384MB 0x0c
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#define IGD_DVMT50_PRE_ALLOC_416MB 0x0d
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#define IGD_DVMT50_PRE_ALLOC_448MB 0x0e
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#define IGD_DVMT50_PRE_ALLOC_480MB 0x0f
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#define IGD_DVMT50_PRE_ALLOC_512MB 0x10
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#define APERTURE_SIZE_128MB 1
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#define APERTURE_SIZE_256MB 2
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#define APERTURE_SIZE_512MB 3
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#define GTT_SIZE_1MB 1
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#define GTT_SIZE_2MB 2
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#define DRAM_TYPE_DDR3 0
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#define DRAM_TYPE_LPDDR3 1
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#define SDCARD_MODE_DISABLED 0
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#define SDCARD_MODE_PCI 1
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#define SDCARD_MODE_ACPI 2
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#define LPE_MODE_DISABLED 0
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#define LPE_MODE_PCI 1
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#define LPE_MODE_ACPI 2
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#define CHV_SVID_CONFIG_0 0
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#define CHV_SVID_CONFIG_1 1
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#define CHV_SVID_CONFIG_2 2
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#define CHV_SVID_CONFIG_3 3
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#define EMMC_MODE_DISABLED 0
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#define EMMC_MODE_PCI 1
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#define EMMC_MODE_ACPI 2
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#define SATA_SPEED_GEN1 1
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#define SATA_SPEED_GEN2 2
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#define SATA_SPEED_GEN3 3
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#define ISP_PCI_DEV_CONFIG_1 1
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#define ISP_PCI_DEV_CONFIG_2 2
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#define ISP_PCI_DEV_CONFIG_3 3
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#define PNP_SETTING_DISABLED 0
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#define PNP_SETTING_POWER 1
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#define PNP_SETTING_PERF 2
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#define PNP_SETTING_POWER_AND_PERF 3
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#endif /* __FSP_CONFIGS_H__ */
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172
arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
Normal file
172
arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
Normal file
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@ -0,0 +1,172 @@
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/*
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* Copyright (C) 2015, Intel Corporation
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: Intel
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*/
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#ifndef __FSP_VPD_H__
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#define __FSP_VPD_H__
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struct __packed memory_upd {
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u64 signature; /* Offset 0x0020 */
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u8 revision; /* Offset 0x0028 */
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u8 unused2[7]; /* Offset 0x0029 */
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u16 mrc_init_tseg_size; /* Offset 0x0030 */
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u16 mrc_init_mmio_size; /* Offset 0x0032 */
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u8 mrc_init_spd_addr1; /* Offset 0x0034 */
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u8 mrc_init_spd_addr2; /* Offset 0x0035 */
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u8 mem_ch0_config; /* Offset 0x0036 */
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u8 mem_ch1_config; /* Offset 0x0037 */
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u32 memory_spd_ptr; /* Offset 0x0038 */
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u8 igd_dvmt50_pre_alloc; /* Offset 0x003c */
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u8 aperture_size; /* Offset 0x003d */
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u8 gtt_size; /* Offset 0x003e */
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u8 legacy_seg_decode; /* Offset 0x003f */
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u8 enable_dvfs; /* Offset 0x0040 */
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u8 memory_type; /* Offset 0x0041 */
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u8 enable_ca_mirror; /* Offset 0x0042 */
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u8 reserved[189]; /* Offset 0x0043 */
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};
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struct __packed azalia_verb_table_header {
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u32 vendor_device_id;
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u16 sub_system_id;
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u8 revision_id;
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u8 front_panel_support;
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u16 number_of_rear_jacks;
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u16 number_of_front_jacks;
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};
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struct __packed azalia_verb_table {
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struct azalia_verb_table_header header;
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u32 *data;
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};
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struct __packed azalia_config {
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u8 pme_enable:1;
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u8 docking_supported:1;
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u8 docking_attached:1;
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u8 hdmi_codec_enable:1;
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u8 azalia_v_ci_enable:1;
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u8 reserved:3;
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u8 verb_table_num;
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struct azalia_verb_table *verb_table;
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u16 reset_wait_timer_ms;
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};
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struct gpio_family {
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u32 confg;
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u32 confg_changes;
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u32 misc;
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u32 mmio_addr;
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wchar_t *name;
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};
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struct gpio_pad {
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u32 confg0;
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u32 confg0_changes;
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u32 confg1;
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u32 confg1_changes;
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u32 community;
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u32 mmio_addr;
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wchar_t *name;
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u32 misc;
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};
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struct __packed silicon_upd {
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u64 signature; /* Offset 0x0100 */
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u8 revision; /* Offset 0x0108 */
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u8 unused3[7]; /* Offset 0x0109 */
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u8 sdcard_mode; /* Offset 0x0110 */
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u8 enable_hsuart0; /* Offset 0x0111 */
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u8 enable_hsuart1; /* Offset 0x0112 */
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u8 enable_azalia; /* Offset 0x0113 */
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struct azalia_config *azalia_cfg_ptr; /* Offset 0x0114 */
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u8 enable_sata; /* Offset 0x0118 */
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u8 enable_xhci; /* Offset 0x0119 */
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u8 lpe_mode; /* Offset 0x011a */
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u8 enable_dma0; /* Offset 0x011b */
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u8 enable_dma1; /* Offset 0x011c */
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u8 enable_i2c0; /* Offset 0x011d */
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u8 enable_i2c1; /* Offset 0x011e */
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u8 enable_i2c2; /* Offset 0x011f */
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u8 enable_i2c3; /* Offset 0x0120 */
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u8 enable_i2c4; /* Offset 0x0121 */
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u8 enable_i2c5; /* Offset 0x0122 */
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u8 enable_i2c6; /* Offset 0x0123 */
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u32 graphics_config_ptr; /* Offset 0x0124 */
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struct gpio_family *gpio_familiy_ptr; /* Offset 0x0128 */
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struct gpio_pad *gpio_pad_ptr; /* Offset 0x012c */
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u8 disable_punit_pwr_config; /* Offset 0x0130 */
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u8 chv_svid_config; /* Offset 0x0131 */
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u8 disable_dptf; /* Offset 0x0132 */
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u8 emmc_mode; /* Offset 0x0133 */
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u8 usb3_clk_ssc; /* Offset 0x0134 */
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u8 disp_clk_ssc; /* Offset 0x0135 */
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u8 sata_clk_ssc; /* Offset 0x0136 */
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u8 usb2_port0_pe_txi_set; /* Offset 0x0137 */
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u8 usb2_port0_txi_set; /* Offset 0x0138 */
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u8 usb2_port0_tx_emphasis_en; /* Offset 0x0139 */
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u8 usb2_port0_tx_pe_half; /* Offset 0x013a */
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u8 usb2_port1_pe_txi_set; /* Offset 0x013b */
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u8 usb2_port1_txi_set; /* Offset 0x013c */
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u8 usb2_port1_tx_emphasis_en; /* Offset 0x013d */
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u8 usb2_port1_tx_pe_half; /* Offset 0x013e */
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u8 usb2_port2_pe_txi_set; /* Offset 0x013f */
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u8 usb2_port2_txi_set; /* Offset 0x0140 */
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u8 usb2_port2_tx_emphasis_en; /* Offset 0x0141 */
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u8 usb2_port2_tx_pe_half; /* Offset 0x0142 */
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u8 usb2_port3_pe_txi_set; /* Offset 0x0143 */
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u8 usb2_port3_txi_set; /* Offset 0x0144 */
|
||||
u8 usb2_port3_tx_emphasis_en; /* Offset 0x0145 */
|
||||
u8 usb2_port3_tx_pe_half; /* Offset 0x0146 */
|
||||
u8 usb2_port4_pe_txi_set; /* Offset 0x0147 */
|
||||
u8 usb2_port4_txi_set; /* Offset 0x0148 */
|
||||
u8 usb2_port4_tx_emphasis_en; /* Offset 0x0149 */
|
||||
u8 usb2_port4_tx_pe_half; /* Offset 0x014a */
|
||||
u8 usb3_lane0_ow2tap_gen2_deemph3p5; /* Offset 0x014b */
|
||||
u8 usb3_lane1_ow2tap_gen2_deemph3p5; /* Offset 0x014c */
|
||||
u8 usb3_lane2_ow2tap_gen2_deemph3p5; /* Offset 0x014d */
|
||||
u8 usb3_lane3_ow2tap_gen2_deemph3p5; /* Offset 0x014e */
|
||||
u8 sata_speed; /* Offset 0x014f */
|
||||
u8 usb_ssic_port; /* Offset 0x0150 */
|
||||
u8 usb_hsic_port; /* Offset 0x0151 */
|
||||
u8 pcie_rootport_speed; /* Offset 0x0152 */
|
||||
u8 enable_ssic; /* Offset 0x0153 */
|
||||
u32 logo_ptr; /* Offset 0x0154 */
|
||||
u32 logo_size; /* Offset 0x0158 */
|
||||
u8 rtc_lock; /* Offset 0x015c */
|
||||
u8 pmic_i2c_bus; /* Offset 0x015d */
|
||||
u8 enable_isp; /* Offset 0x015e */
|
||||
u8 isp_pci_dev_config; /* Offset 0x015f */
|
||||
u8 turbo_mode; /* Offset 0x0160 */
|
||||
u8 pnp_settings; /* Offset 0x0161 */
|
||||
u8 sd_detect_chk; /* Offset 0x0162 */
|
||||
u8 reserved[411]; /* Offset 0x0163 */
|
||||
};
|
||||
|
||||
#define MEMORY_UPD_ID 0x244450554d454d24 /* '$MEMUPD$' */
|
||||
#define SILICON_UPD_ID 0x244450555f495324 /* '$SI_UPD$' */
|
||||
|
||||
struct __packed upd_region {
|
||||
u64 signature; /* Offset 0x0000 */
|
||||
u8 revision; /* Offset 0x0008 */
|
||||
u8 unused0[7]; /* Offset 0x0009 */
|
||||
u32 memory_upd_offset; /* Offset 0x0010 */
|
||||
u32 silicon_upd_offset; /* Offset 0x0014 */
|
||||
u64 unused1; /* Offset 0x0018 */
|
||||
struct memory_upd memory_upd; /* Offset 0x0020 */
|
||||
struct silicon_upd silicon_upd; /* Offset 0x0100 */
|
||||
u16 terminator; /* Offset 0x02fe */
|
||||
};
|
||||
|
||||
#define VPD_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */
|
||||
|
||||
struct __packed vpd_region {
|
||||
u64 sign; /* Offset 0x0000 */
|
||||
u32 img_rev; /* Offset 0x0008 */
|
||||
u32 upd_offset; /* Offset 0x000c */
|
||||
};
|
||||
|
||||
#endif /* __FSP_VPD_H__ */
|
||||
217
arch/x86/include/asm/arch-braswell/gpio.h
Normal file
217
arch/x86/include/asm/arch-braswell/gpio.h
Normal file
|
|
@ -0,0 +1,217 @@
|
|||
/*
|
||||
* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* From coreboot src/soc/intel/braswell/include/soc/gpio.h
|
||||
*/
|
||||
|
||||
#ifndef _BRASWELL_GPIO_H_
|
||||
#define _BRASWELL_GPIO_H_
|
||||
|
||||
#include <asm/arch/iomap.h>
|
||||
|
||||
enum mode_list {
|
||||
M0,
|
||||
M1,
|
||||
M2,
|
||||
M3,
|
||||
M4,
|
||||
M5,
|
||||
M6,
|
||||
M7,
|
||||
M8,
|
||||
M9,
|
||||
M10,
|
||||
M11,
|
||||
M12,
|
||||
M13,
|
||||
};
|
||||
|
||||
enum int_select {
|
||||
L0,
|
||||
L1,
|
||||
L2,
|
||||
L3,
|
||||
L4,
|
||||
L5,
|
||||
L6,
|
||||
L7,
|
||||
L8,
|
||||
L9,
|
||||
L10,
|
||||
L11,
|
||||
L12,
|
||||
L13,
|
||||
L14,
|
||||
L15,
|
||||
};
|
||||
|
||||
enum gpio_en {
|
||||
NATIVE = 0xff,
|
||||
GPIO = 0, /* Native, no need to set PAD_VALUE */
|
||||
GPO = 1, /* GPO, output only in PAD_VALUE */
|
||||
GPI = 2, /* GPI, input only in PAD_VALUE */
|
||||
HI_Z = 3,
|
||||
NA_GPO = 0,
|
||||
};
|
||||
|
||||
enum gpio_state {
|
||||
LOW,
|
||||
HIGH,
|
||||
};
|
||||
|
||||
enum en_dis {
|
||||
DISABLE, /* Disable */
|
||||
ENABLE, /* Enable */
|
||||
};
|
||||
|
||||
enum int_type {
|
||||
INT_DIS,
|
||||
TRIG_EDGE_LOW,
|
||||
TRIG_EDGE_HIGH,
|
||||
TRIG_EDGE_BOTH,
|
||||
TRIG_LEVEL,
|
||||
};
|
||||
|
||||
enum mask {
|
||||
MASKABLE,
|
||||
NON_MASKABLE,
|
||||
};
|
||||
|
||||
enum glitch_cfg {
|
||||
GLITCH_DISABLE,
|
||||
EN_EDGE_DETECT,
|
||||
EN_RX_DATA,
|
||||
EN_EDGE_RX_DATA,
|
||||
};
|
||||
|
||||
enum inv_rx_tx {
|
||||
NO_INVERSION = 0,
|
||||
INV_RX_ENABLE = 1,
|
||||
INV_TX_ENABLE = 2,
|
||||
INV_RX_TX_ENABLE = 3,
|
||||
INV_RX_DATA = 4,
|
||||
INV_TX_DATA = 8,
|
||||
};
|
||||
|
||||
enum voltage {
|
||||
VOLT_3_3, /* Working on 3.3 Volts */
|
||||
VOLT_1_8, /* Working on 1.8 Volts */
|
||||
};
|
||||
|
||||
enum hs_mode {
|
||||
DISABLE_HS, /* Disable high speed mode */
|
||||
ENABLE_HS, /* Enable high speed mode */
|
||||
};
|
||||
|
||||
enum odt_up_dn {
|
||||
PULL_UP, /* On Die Termination Up */
|
||||
PULL_DOWN, /* On Die Termination Down */
|
||||
};
|
||||
|
||||
enum odt_en {
|
||||
DISABLE_OD, /* On Die Termination Disable */
|
||||
ENABLE_OD, /* On Die Termination Enable */
|
||||
};
|
||||
|
||||
enum pull_type {
|
||||
P_NONE = 0, /* Pull None */
|
||||
P_20K_L = 1, /* Pull Down 20K */
|
||||
P_5K_L = 2, /* Pull Down 5K */
|
||||
P_1K_L = 4, /* Pull Down 1K */
|
||||
P_20K_H = 9, /* Pull Up 20K */
|
||||
P_5K_H = 10, /* Pull Up 5K */
|
||||
P_1K_H = 12 /* Pull Up 1K */
|
||||
};
|
||||
|
||||
enum bit {
|
||||
ONE_BIT = 1,
|
||||
TWO_BIT = 3,
|
||||
THREE_BIT = 7,
|
||||
FOUR_BIT = 15,
|
||||
FIVE_BIT = 31,
|
||||
SIX_BIT = 63,
|
||||
SEVEN_BIT = 127,
|
||||
EIGHT_BIT = 255
|
||||
};
|
||||
|
||||
enum gpe_config {
|
||||
GPE,
|
||||
SMI,
|
||||
SCI,
|
||||
};
|
||||
|
||||
enum community {
|
||||
SOUTHWEST = 0x0000,
|
||||
NORTH = 0x8000,
|
||||
EAST = 0x10000,
|
||||
SOUTHEAST = 0x18000,
|
||||
VIRTUAL = 0x20000,
|
||||
};
|
||||
|
||||
#define NA 0xff
|
||||
#define TERMINATOR 0xffffffff
|
||||
|
||||
#define GPIO_FAMILY_CONF(family_name, park_mode, hysctl, vp18_mode, hs_mode, \
|
||||
odt_up_dn, odt_en, curr_src_str, rcomp, family_no, community_offset) { \
|
||||
.confg = ((((park_mode) != NA) ? park_mode << 26 : 0) | \
|
||||
(((hysctl) != NA) ? hysctl << 24 : 0) | \
|
||||
(((vp18_mode) != NA) ? vp18_mode << 21 : 0) | \
|
||||
(((hs_mode) != NA) ? hs_mode << 19 : 0) | \
|
||||
(((odt_up_dn) != NA) ? odt_up_dn << 18 : 0) | \
|
||||
(((odt_en) != NA) ? odt_en << 17 : 0) | \
|
||||
(curr_src_str)), \
|
||||
.confg_changes = ((((park_mode) != NA) ? ONE_BIT << 26 : 0) | \
|
||||
(((hysctl) != NA) ? TWO_BIT << 24 : 0) | \
|
||||
(((vp18_mode) != NA) ? ONE_BIT << 21 : 0) | \
|
||||
(((hs_mode) != NA) ? ONE_BIT << 19 : 0) | \
|
||||
(((odt_up_dn) != NA) ? ONE_BIT << 18 : 0) | \
|
||||
(((odt_en) != NA) ? ONE_BIT << 17 : 0) | \
|
||||
(THREE_BIT)), \
|
||||
.misc = ((rcomp == ENABLE) ? 1 : 0) , \
|
||||
.mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
|
||||
((family_no != NA) ? (IO_BASE_ADDRESS + community_offset +\
|
||||
(0x80 * family_no) + 0x1080) : 0) , \
|
||||
.name = 0 \
|
||||
}
|
||||
|
||||
#define GPIO_PAD_CONF(pad_name, mode_select, mode, gpio_config, gpio_state, \
|
||||
gpio_light_mode, int_type, int_sel, term, open_drain, current_source,\
|
||||
int_mask, glitch, inv_rx_tx, wake_mask, wake_mask_bit, gpe, \
|
||||
mmio_offset, community_offset) { \
|
||||
.confg0 = ((((int_sel) != NA) ? (int_sel << 28) : 0) | \
|
||||
(((glitch) != NA) ? (glitch << 26) : 0) | \
|
||||
(((term) != NA) ? (term << 20) : 0) | \
|
||||
(((mode_select) == GPIO) ? ((mode << 16) | (1 << 15)) : \
|
||||
((mode << 16))) | \
|
||||
(((gpio_config) != NA) ? (gpio_config << 8) : 0) | \
|
||||
(((gpio_light_mode) != NA) ? (gpio_light_mode << 7) : 0) | \
|
||||
(((gpio_state) == HIGH) ? 2 : 0)), \
|
||||
.confg0_changes = ((((int_sel) != NA) ? (FOUR_BIT << 28) : 0) | \
|
||||
(((glitch) != NA) ? (TWO_BIT << 26) : 0) | \
|
||||
(((term) != NA) ? (FOUR_BIT << 20) : 0) | \
|
||||
(FIVE_BIT << 15) | \
|
||||
(((gpio_config) != NA) ? (THREE_BIT << 8) : 0) | \
|
||||
(((gpio_light_mode) != NA) ? (ONE_BIT << 7) : 0) | \
|
||||
(((gpio_state) != NA) ? ONE_BIT << 1 : 0)), \
|
||||
.confg1 = ((((current_source) != NA) ? (current_source << 27) : 0) | \
|
||||
(((inv_rx_tx) != NA) ? inv_rx_tx << 4 : 0) | \
|
||||
(((open_drain) != NA) ? open_drain << 3 : 0) | \
|
||||
(((int_type) != NA) ? int_type : 0)), \
|
||||
.confg1_changes = ((((current_source) != NA) ? (ONE_BIT << 27) : 0) | \
|
||||
(((inv_rx_tx) != NA) ? FOUR_BIT << 4 : 0) | \
|
||||
(((open_drain) != NA) ? ONE_BIT << 3 : 0) | \
|
||||
(((int_type) != NA) ? THREE_BIT : 0)), \
|
||||
.community = community_offset, \
|
||||
.mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
|
||||
((mmio_offset != NA) ? (IO_BASE_ADDRESS + \
|
||||
community_offset + mmio_offset) : 0), \
|
||||
.name = 0, \
|
||||
.misc = ((((gpe) != NA) ? (gpe << 0) : 0) | \
|
||||
(((wake_mask) != NA) ? (wake_mask << 2) : 0) | \
|
||||
(((int_mask) != NA) ? (int_mask << 3) : 0)) | \
|
||||
(((wake_mask_bit) != NA) ? (wake_mask_bit << 4) : (NA << 4)) \
|
||||
}
|
||||
|
||||
#endif /* _BRASWELL_GPIO_H_ */
|
||||
Loading…
Reference in a new issue