Commit graph

3425 commits

Author SHA1 Message Date
Simon Glass
96dfc0633a x86: Remove unused real mode code
This code is pretty old and we want to support only 32-bit systems now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-02-14 20:19:03 -08:00
Simon Glass
588a13f742 x86: Rename CONFIG_NO_X86_RESET_VECTOR to CONFIG_X86_RESET_VECTOR
Invert the polarity of this option to simplify the Makefile logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Gabe Black <gabeblack@chromium.org>
2013-02-14 20:18:58 -08:00
Simon Glass
1f3a581495 x86: Remove sc520 cpu
This x86 CPU variant is no longer required as the boards that use it have
been removed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-02-14 20:18:58 -08:00
Tom Rini
9c748e02d9 Merge branch 'next' of git://git.denx.de/u-boot-mips 2013-02-12 19:03:59 -05:00
Gabor Juhos
04380c651a MIPS: add dynamic relocation support
The code handles relocation entries with the
following relocation types only:
  mips32: R_MIPS_REL32
  mips64: R_MIPS_REL+R_MIPS_64
  xburst: R_MIPS_REL32

Other relocation entries are skipped without
processing. The code must be extended if other
relocation types must be supported.

Add -pie to LDFLAGS_FINAL to generate the .rel.dyn
fixup table, which will be applied to the relocated
image before transferring control to it.

The CONFIG_NEEDS_MANUAL_RELOC is not needed
after the patch, so remove that as well.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:13 +01:00
Gabor Juhos
0ba8926e08 MIPS: u-boot.lds: add relocation specific sections
This section contain the table needed for dynamic
relocation. Also provide symbols for the relocation
code to access the table.

Discard all sections which are not needed in the final
ELF binary and U-Boot image. Section .dynsym cannot be
discarded or GNU ld crashes otherwise. This section
will be stripped by GNU objcpy in a later patch.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:13 +01:00
Daniel Schwierzeck
28875e2c47 MIPS: start.S: use symbol __image_copy_end for U-Boot image relocation
Use the newly introduced symbol __image_copy_end as end address for
relocation of U-Boot image. This is needed for dynamic relocation added
in later patches. This patch obsoletes the symbols uboot_end and
uboot_end_data which are removed.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:13 +01:00
Daniel Schwierzeck
696a3b2a53 MIPS: start.S: optimize BSS initialization
Get the start and end address for clearing BSS from the newly
introduced symbols __bss_start and __bss_end. After GOT is
relocated, those symbols are already pointing to the correct
addresses.

Also optimize the loop by moving the address incrementation
to the delay slot to avoid the initial sub instruction.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:13 +01:00
Daniel Schwierzeck
eea8a320e1 MIPS: board.c: switch to new symbols __bss_end and __image_copy_end
Use the newly introduced symbols __image_copy_end and __bss_end
for setting up the memory area for the relocated U-Boot.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:12 +01:00
Daniel Schwierzeck
3420bf1ca0 MIPS: u-boot.lds: introduce symbol __image_copy_end
This symbol is used in later patches as end address
for relocation of the U-Boot image into RAM.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:12 +01:00
Daniel Schwierzeck
a52852c5a6 MIPS: u-boot.lds: merge all BSS sections and introduce symbols __bss_[start|end]
These symbols are used in later patches for as addresses for
clearing the BSS area in the relocated U-Boot image.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:12 +01:00
Gabor Juhos
45397816b2 MIPS: compute num_got_entries from .got section's size
The '__got_start' and '__got_end' symbols are used
only in the linker script to compute the value of
the 'num_got_entries' symbol.

Remove the symbols and use the SIZEOF(.got) command
to get the size of the .got section.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-02-12 22:22:12 +01:00
Daniel Schwierzeck
8b1c7345c6 MIPS: start.S: unify and simplify reset vector handling
Adopt reset vector handling from Yamon.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:12 +01:00
Daniel Schwierzeck
4dc7412afa MIPS: start.S: remove obsolete 64 bit handling in setup_c0_status
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:12 +01:00
Daniel Schwierzeck
97b920dab1 MIPS: xburst: fix broken access to global_data
Fix access to global_data which is broken since commits:

commit 035cbe99cd
Author: Simon Glass <sjg@chromium.org>
Date:   Thu Dec 13 20:49:08 2012 +0000

    mips: Move per_clk and dev_clk to arch_global_data

    Move these field into arch_global_data and tidy up. The other
    CONFIG_JZSOC fields are used by various architectures, so just remove
    the #ifdef bracketing for these.

    Signed-off-by: Simon Glass <sjg@chromium.org>

commit 582601da2f
Author: Simon Glass <sjg@chromium.org>
Date:   Thu Dec 13 20:48:35 2012 +0000

    arm: Move lastinc to arch_global_data

    Move this field into arch_global_data and tidy up.

    Signed-off-by: Simon Glass <sjg@chromium.org>

commit 66ee692347
Author: Simon Glass <sjg@chromium.org>
Date:   Thu Dec 13 20:48:34 2012 +0000

    arm: Move tbl to arch_global_data

    Move this field into arch_global_data and tidy up.

    Signed-off-by: Simon Glass <sjg@chromium.org>

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2013-02-12 22:22:12 +01:00
Otavio Salvador
291b3dcd49 build: imx: Fix 'u-boot.imx' build without full OBJTREE reference
When calling 'make u-boot.imx' the build were failing as it were
expecting the full path for the file; this regression has been
included by commit 71a988a (imximage.cfg: run files through C
preprocessor).

The direct references for u-boot.imx were replaced by $(obj) as
config.mk handles the proper setting of it making it set to $(OBJTREE)
when required.

The build has been test using:

 - ./MAKEALL -s mx5 -s mx6
 - make u-boot.imx
 - make O=/tmp/build

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-02-12 18:39:08 +01:00
Tom Rini
951c6baaf4 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-02-12 10:18:31 -05:00
Fabio Estevam
76c91e668a mx6: Disable Power Down Bit of watchdog
On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted
and it is not able to reach the Linux prompt.

Comparing the watchdog behaviour on a revB versus revC board:

- On a mx6qsabresd revB:

U-Boot > reset
resetting ...

U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)

CPU:   Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: WDOG
...

- On a mx6qsabresd revC:

U-Boot > reset
resetting ...

U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)

CPU:   Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: POR

So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR.

Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and
is also safe for all mx6 boards.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-02-12 13:54:34 +01:00
Lucas Stach
fd8e1c3866 arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the README
No one expects to end up in a delayed environment if
CONFIG_DELAY_ENVIRONMENT isn't defined.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Allen Martin <amartin@nvidia.com>
2013-02-11 10:35:26 -07:00
Tom Warren
8aff009585 Tegra114: Dalmore: Add DT files
These are stripped down for bringup, They'll be filled out later
to match-up with the kernel DT contents, and/or as devices are
brought up (mmc, usb, spi, etc.).

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Tom Warren
e23bb6a438 Tegra114: Add common CPU (shared) files
These files are used by both SPL and main U-Boot.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Tom Warren
ec1885cee1 Tegra114: Add CPU (armv7) files
These files are for code that runs on the CPU (A15) on T114 boards.
At this time, there is no A15-specific code here.
As T114-specific run-time code is added, it'll go here.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Tom Warren
4040ec10df Tegra114: Add AVP (arm720t) files
This provides SPL support for T114 boards - AVP early init, plus
CPU (A15) init/jump to main U-Boot.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Tom Warren
2fc65e2834 Tegra114: Add arch-tegra114 include files
Common Tegra files are in arch-tegra, shared between T20/T30/T114.
Tegra114-specific headers are in arch-tegra114. Note that some of
these will be filled in as more T114 support is added (drivers,
WB/LP0 support, etc.).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Allen Martin
b19f57491a tegra: add SPI SLINK driver
Add driver for tegra SPI "SLINK" style driver.  This controller is
similar to the tegra20 SPI "SFLASH" controller.  The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices.  In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH.  Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.

This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings.  Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.

To enable this driver, use CONFIG_TEGRA_SLINK

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Allen Martin
91673e2adf tegra: add addresses of SPI SLINK controllers
Add I/O addresses of SPI SLINK controllers 1-6

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Allen Martin
23e3158f34 tegra30: fdt: add SPI SLINK nodes
Add tegra30 SPI SLINK nodes to fdt.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Allen Martin
7d54f022bb tegra30: add SBC1 to periph id mapping table
SBC1 is SPI controller 1 on tegra30

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Allen Martin
c98f03fae0 tegra20: fdt: add SPI SFLASH node
Add node for tegra20 SPI SFLASH controller to fdt.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Stephen Warren
4727a13bde tegra: rename FUNCMUX_UART2_UARTB
FUNCMUX_ defines should be named after the pin groups they affect, not
after the module they're muxing onto those pin groups.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Tom Warren
f29f086a09 Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c
This 'commonizes' much of the clock/pll code. SoC-dependent code
and tables are left in arch/cpu/tegraXXX-common/clock.c

Some T30 tables needed whitespace fixes due to checkpatch complaints.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Tom Warren
d83152d8e4 Tegra: T20: Remove unused 'SLOW' SoC ID and PLLX table entry
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:23 -07:00
Gerald Van Baren
58864ddc72 Clean up libfdt.h includes
The libfdt.h file is the definition file for libfdt.  It is unnecessary
to include other fdt header files (the necessary ones are pulled in
by libfdt.h).

Signed-off-by: Gerald Van Baren <gvb@unssw.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
2013-02-08 22:32:38 -05:00
Kim Phillips
8aa5ec6e16 common/fdt_support.c: sparse fixes
trivial:

fdt_support.c:89:64: warning: Using plain integer as NULL pointer
fdt_support.c:325:65: warning: Using plain integer as NULL pointer
fdt_support.c:352:65: warning: Using plain integer as NULL pointer

For the following bad constant expression, We hardcode the max. number of
memory banks to four for the foreseeable future, and add an error with
instructions on what to do once it's exceeded:

fdt_support.c:397:22: error: bad constant expression

For the rest below, sparse found a couple of wrong endian conversions
in of_bus_default_translate() and fdt_get_base_address(), but
otherwise the rest is mostly annotation fixes:

fdt_support.c:64:24: warning: cast to restricted __be32
fdt_support.c:192:21: warning: incorrect type in assignment (different base types)
fdt_support.c:192:21:    expected unsigned int [unsigned] [usertype] tmp
fdt_support.c:192:21:    got restricted __be32 [usertype] <noident>
fdt_support.c:201:21: warning: incorrect type in assignment (different base types)
fdt_support.c:201:21:    expected unsigned int [unsigned] [addressable] [usertype] tmp
fdt_support.c:201:21:    got restricted __be32 [usertype] <noident>
fdt_support.c:304:13: warning: incorrect type in assignment (different base types)
fdt_support.c:304:13:    expected unsigned int [unsigned] [usertype] val
fdt_support.c:304:13:    got restricted __be32 [usertype] <noident>
fdt_support.c:333:13: warning: incorrect type in assignment (different base types)
fdt_support.c:333:13:    expected unsigned int [unsigned] [usertype] val
fdt_support.c:333:13:    got restricted __be32 [usertype] <noident>
fdt_support.c:359:13: warning: incorrect type in assignment (different base types)
fdt_support.c:359:13:    expected unsigned int [unsigned] [usertype] val
fdt_support.c:359:13:    got restricted __be32 [usertype] <noident>
fdt_support.c:373:21: warning: cast to restricted __be32
fdt_support.c:963:48: warning: incorrect type in argument 1 (different base types)
fdt_support.c:963:48:    expected restricted __be32 const [usertype] *p
fdt_support.c:963:48:    got unsigned int [usertype] *<noident>
fdt_support.c:971:48: warning: incorrect type in argument 1 (different base types)
fdt_support.c:971:48:    expected restricted __be32 const [usertype] *p
fdt_support.c:971:48:    got unsigned int [usertype] *<noident>
fdt_support.c:984:29: warning: incorrect type in argument 1 (different base types)
fdt_support.c:984:29:    expected restricted __be32 const [usertype] *cell
fdt_support.c:984:29:    got unsigned int [usertype] *addr
fdt_support.c:996:32: warning: incorrect type in argument 1 (different base types)
fdt_support.c:996:32:    expected restricted __be32 const [usertype] *cell
fdt_support.c:996:32:    got unsigned int [usertype] *addr
fdt_support.c:1041:41: warning: incorrect type in argument 1 (different base types)
fdt_support.c:1041:41:    expected restricted __be32 const [usertype] *cell
fdt_support.c:1041:41:    got unsigned int [usertype] *addr
fdt_support.c:1053:41: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1053:41:    expected restricted __be32 const [usertype] *range
fdt_support.c:1053:41:    got unsigned int const [usertype] *[assigned] ranges
fdt_support.c:1064:53: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1064:53:    expected restricted __be32 const [usertype] *addr
fdt_support.c:1064:53:    got unsigned int [usertype] *addr
fdt_support.c:1110:50: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1110:50:    expected restricted __be32 const [usertype] *addr
fdt_support.c:1110:50:    got unsigned int *<noident>
fdt_support.c:1121:49: warning: incorrect type in argument 1 (different base types)
fdt_support.c:1121:49:    expected restricted __be32 const [usertype] *cell
fdt_support.c:1121:49:    got unsigned int *<noident>
fdt_support.c:1147:60: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1147:60:    expected restricted __be32 const [usertype] *addr
fdt_support.c:1147:60:    got unsigned int *<noident>
fdt_support.c:1081:5: warning: symbol '__of_translate_address' was not declared. Should it be static?
fdt_support.c:1154:5: error: symbol 'fdt_translate_address' redeclared with different type (originally declared at include/fdt_support.h:95) - incompatible argument 3 (different base types)
fdt_support.c: In function 'fdt_node_offset_by_compat_reg':
fdt_support.c:1173:17: warning: initialization discards 'const' qualifier from pointer target type [enabled by default]

See also linux kernel commit 0131d897 "of/address: use proper
endianess in get_flags".

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Jerry Van Baren <gvb.uboot@gmail.com>
2013-02-07 20:38:55 -05:00
Kim Phillips
12e06fe03f treewide: include libfdt_env.h before fdt.h
and, if including libfdt.h which includes libfdt_env.h in
the correct order, don't include fdt.h before libfdt.h.

this is needed to get the fdt type definitions set from
the project environment before fdt.h uses them.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Jerry Van Baren <gvb.uboot@gmail.com>
2013-02-07 20:38:55 -05:00
Jeff Lance
13526f7157 Add DDR3 support for AM335x-EVM (Version 1.5A)
AM335x EVM 1.5A uses Micron MT41J512M8RH-125 SDRAM 4Gb (512Mx8) as the
DDR3 chip.

[Hebbar Gururaja <gururaja.hebbar@ti.com>]
	- Resolve merge conflict while rebasing. File structure is
	  changed in the mainline. So re-arrange the code accordingly.
	- Update commit message to reflect the DDR3 part number

Signed-off-by: Jeff Lance <j-lance1@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
2013-02-07 10:36:26 -05:00
Lars Poeschel
1c1b7c3739 pcm051: Add support for Phytec phyCORE-AM335x
The board is named pcm051 and has this hardware:
SOC: TI AM3359
DDR3-RAM: 2x MT41J256M8HX-15EIT:D 512MiB
ETH 1: LAN8710AI
SPI-Flash: W25Q64BVSSIG
RTC: RV-4162-C7
I2C-EEPROM: CAT32WC32
NAND: MT29F4G08_VFPGA63
PMIC: TPS65910A3
LCD

Supported:
UART 1
MMC/SD
ETH 1
USB
I2C
SPI

Not yet supported:
NAND
RTC
LCD

Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
[trini: Add #define CONFIG_PHY_ADDR 0 to config]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-07 10:36:26 -05:00
Lars Poeschel
aca0b8b4f7 am33xx: add a pulldown macro to pinmux config
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
2013-02-07 10:36:25 -05:00
Michal Simek
00ed345898 arm: zynq: Add lowlevel initialization to C
Do lowlevel initialization directly in C. Zynq do not
require to do it in asm.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-07 09:18:42 +01:00
Michal Simek
59c651f4e2 arm: zynq: Add SLCR support with system reset
The patch provides slcr base address initialization support
and a support to reset the cpu through slcr driver,
hence removed the reset_cpu() from board.c.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-07 09:18:42 +01:00
Tom Rini
2d795c9621 Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze 2013-02-04 09:14:22 -05:00
Simon Glass
43cff66e03 x86: Use generic global_data
Move x86 over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
1e5f8bd0bc sparc: Use generic global_data
Move sparc over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
a987902753 sh: Use generic global_data
Move sh over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
07d59bb243 sandbox: Use generic global_data
Move sandbox over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
2ab575e05d powerpc: Use generic global_data
Move powerpc over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
6f8b28520d openrisc: Use generic global_data
Move openrisc over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
1f7559ec38 nios2: Use generic global_data
Move nios2 over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
2013-02-04 09:05:46 -05:00
Simon Glass
ee22c1a214 nds32: Use generic global_data
Move nds32 over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
9572202026 mips: Use generic global_data
Move mips over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:45 -05:00
Simon Glass
eef5415036 microblaze: Use generic global_data
Move microblaze over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Michal Simek <monstr@monstr.eu>
2013-02-04 09:05:45 -05:00
Simon Glass
e56b250735 m68k: Use generic global_data
Move m68k over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:45 -05:00
Simon Glass
06b507b85c blackfin: Use generic global_data
Move blackfin over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:45 -05:00
Simon Glass
47a9789f25 avr32: Use generic global_data
Move avr32 over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:45 -05:00
Simon Glass
baa1e53683 arm: Use generic global_data
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:45 -05:00
Simon Glass
8ee666a76f sandbox: Move ram_buf to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:45 -05:00
Simon Glass
3d0f8c8f80 avr32: Move cpu_hz to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:45 -05:00
Simon Glass
1c865d5897 avr32: Move stack_end to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
035cbe99cd mips: Move per_clk and dev_clk to arch_global_data
Move these field into arch_global_data and tidy up. The other
CONFIG_JZSOC fields are used by various architectures, so just remove
the #ifdef bracketing for these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
7e2592fd5a m68k: Move CONFIG_EXTRA_CLOCK to arch_global_data
Move inp_clk, vco_clk and flb_clk into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
fa25c6f0cc sparc: Drop kbd_status and reset_status from global_data
These fields is not used on sparc, so punt them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
e9adeca3fc ppc: arm: Move sdhc_clk into arch_global_data
This is used by both powerpc and arm, but I think it still qualifies as
architecture-specific.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
225ca83dfe ppc: Move kbd_status to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
a0d3c820c4 ppc: Move wdt_last to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
923a662f2f ppc: Move fpga_state to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
7273ccec61 ppc: Remove console_addr from global data
This does not appear to be used, so punt it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
7e15d6dbf3 ppc: Move mirror_hack to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
3a1dc8f125 arm: Move uart_clk to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
6bb9ba7260 ppc: Move dp_alloc_base, dp_alloc_top to arch_global_data
Move these fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
43e60814b3 ppc: Move arbiter fields to arch_global_data
Move arbiter_event_attributes and arbiter_event_address into
arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
3c4c308c00 ppc: Move reset_status to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
1c356135fa ppc: Move mpc8220 clocks to arch_global_data
Move these fields into arch_global_data and tidy up. The bExtUart field
does not appear to be used, so punt it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
fefb098b18 ppc: Move mpc512x clocks to arch_global_data
Move ips_clk and csb_clk into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
b28774966c ppc: Move mpc5xxx clocks to arch_global_data
Move ipb_clk and pci_clk into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
7c80c6c51a ppc: Move used_tlb_cams to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
8670dbc953 ppc: Move used_laws to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
45bae2e3cf ppc: Move CONFIG_QE to arch_global_data
Move the quantative easing fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:42 -05:00
Simon Glass
609e6ec3f6 ppc: m68k: Move i2c1_clk, i2c2_clk to arch_global_data
Move these fields into arch_global_data and tidy up. This is needed for
both ppc and m68k since they share the i2c driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:42 -05:00
Simon Glass
67ac13b1b9 ppc: Move lbc_clk and cpu to arch_global_data
Move these fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Update for bsc9132qds.c, b4860qds.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-04 09:04:57 -05:00
David Holsgrove
2281ba5172 microblaze: Add muldi3.c which contains routines for _muldi3
Referenced arch/blackfin/lib/muldi3.c and the linux kernel.
Resolves issue seen when building u-boot for HW_MUL=0;

PLATFORM_CPPFLAGS += -mxl-soft-mul
PLATFORM_CPPFLAGS += -mno-xl-multiply-high

which resulted in error while linking to libgcc.a without mul hw (bs / m);

libgcc.a(_muldi3.o): In function `__muldi3':
.... src/gcc-4.6.2/libgcc/libgcc2.c:550: undefined reference to `_GLOBAL_OFFSET_TABLE_'

This link failure would not occur if we used gcc instead of ld directly, as
gcc will correctly use the crt's to resolve this link.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-04 12:07:09 +01:00
Rob Herring
2ff467c051 ARM: add wfi assembly macro
Since wfi instruction is only available on ARMv7, add a conditional
macro for it.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-02-03 14:43:58 +01:00
Albert ARIBAUD
e5f5c4a977 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-02-02 19:29:59 +01:00
Simon Glass
c6731fe22a ppc: Move mpc83xx clock fields to arch_global_data
Move al mpc83xx fields into arch_global_data and tidy up. Also indent
the nested #ifdef for clarity.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
748cd0591a ppc: Move clock fields to arch_global_data
Move vco_out, cpm_clk, scc_clk, brg_clk into arch_global_data and tidy
up. Leave pci_clk on its own since this should really depend only on
CONFIG_PCI and not any particular chip type.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
9fb23624a6 ppc: Remove extra pci_clk fields from global_data
PPC has several of these fields, selected by chip type, although only one
is ever compiled in.

Instead, use a single field. It would be nice if this could be selected
by CONFIG_PCI, but some chips (e.g. mpc5xxx) use pci_clk even when
CONFIG_PCI is not enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
1206c18403 ppc: Move brg_clk to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
6cb49c13f6 x86: Remove reset_status, relocoff from global_data
These fields are not used on x86, so punt them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:40:31 -05:00
Simon Glass
5a35e6c48e x86: Move gd_addr into arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add arch/x86/cpu/cpu.c changes after Graeme's comments]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-01 15:39:42 -05:00
Simon Glass
0cecc3b679 x86: Set up the global data pointer in C instead of asm
We currently assume that the global data pointer is at the start of
struct global_data. We want to remove this restriction, and it is
easiest to do this in C.

Remove the asm code and add equivalent code in C.

This idea was proposed by Graeme Russ here:
   http://patchwork.ozlabs.org/patch/199741/

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Apply Graeme Russ' comments
http://patchwork.ozlabs.org/patch/206305/ here, re-order]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-01 15:36:53 -05:00
Simon Glass
df4aa625a2 x86: Remove gdt_addr from arch_global_data
Remove this unused field.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:35:15 -05:00
Simon Glass
34fd5d253d arm: Move tlb_addr and tlb_size to arch_global_data
Move these fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Address tlb_size in this patch as well]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-01 15:21:58 -05:00
Simon Glass
37434783bb nds32: Drop tlb_addr from global data
This field doesn't appear to be used for anything important, so drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
b4d51db86b ixp: Move timestamp to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
5f70714c2f arm: Move timer_reset_value to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
582601da2f arm: Move lastinc to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
66ee692347 arm: Move tbl to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
8ff43b03e9 arm: Move tbu to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
b339051c0d arm: Move timer_rate_hz into arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:49 -05:00
Simon Glass
f47e6ecd5d at91: Move at91 global data into arch_global_data
Move these fields into arch_global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:49 -05:00
Simon Glass
5cb48582ac Add architecture-specific global data
We plan to move architecture-specific data into a separate structure so
that we can make the rest of it common.

As a first step, create struct arch_global_data to hold these fields.
Initially it is empty.

This patch applies to all archs at once. I can split it if this is really
a pain.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:49 -05:00
Lucas Stach
4e5eb45898 arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the README
No one expects to end up in a delayed environment if
CONFIG_DELAY_ENVIRONMENT isn't defined.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Allen Martin <amartin@nvidia.com>
2013-01-30 19:33:01 -05:00
Tom Rini
b6832af850 Merge branch 'master' of git://git.denx.de/u-boot-mips 2013-01-30 19:26:38 -05:00
Gabor Juhos
cb5dbca899 MIPS: add unified u-boot.lds file
The patch adds an unified linker script file which
can be used for all currently supported MIPS targets.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
Acked-by: Stefan Roese <sr@denx.de>
2013-01-31 00:26:59 +01:00
Gabor Juhos
9950b90d38 MIPS: remove OUTPUT_FORMAT from linker scripts
The OUTPUT_FORMAT command in linker scripts
was always misused due to some endianess and
toolchain problems.

Use GCC flags to ensure proper output format,
and get rid of the OUTPUT_FORMAT commands in
the board specific u-boot.lds files.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2013-01-30 23:34:10 +01:00
Gabor Juhos
6d86227880 MIPS: xburst: simplify relocation offset calculation
The current code uses four instructions and a
temporary register to calculate the relocation
offset and to adjust the gp register.

The relocation offset can be calculated directly
from the CONFIG_SYS_MONITOR_BASE constant and from
the destination address. The resulting offset can
be used to adjust the gp pointer.

This approach makes the code a bit simpler because
it needs two instructions only.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2013-01-30 23:33:27 +01:00
Gabor Juhos
025f2b3380 MIPS: simplify relocated _G_O_T_ address calculation
The difference between the address of the original
and the relocated _GLOBAL_OFFSET_TABLE_ is always
the same as the relocation offset.

The relocation offset is already computed and it is
available in the 's1/t6' register. Use that to adjust
the relocated _G_O_T_ address, instead of calculating
the offset again from the _gp value.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2013-01-30 23:32:52 +01:00
Shengzhou Liu
72bd83cd0a powerpc/t4240: Adding workaround errata A-005871
When CoreNet Fabric (CCF) internal resources are consumed by the cores,
inbound SRIO messaging traffic through RMan can put the device into a
deadlock condition.

This errata workaround forces internal resources to be reserved for
upstream transactions. This ensures resources exist on the device for
upstream transactions and removes the deadlock condition.

The Workaround is for the T4240 silicon rev 1.0.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Vakul Garg
5e95e2d84b powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto'
If property 'fsl,sec-era' is already present, it is updated.
This property is required so that applications can ascertain which
descriptor commands are supported on a particular CAAM version.

Signed-off-by: Vakul Garg <vakul@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Anatolij Gustschin
5b93394318 mpc8xxx: fix DDR init value to use CONFIG_MEM_INIT_VALUE
Configuring custom memory init value using CONFIG_MEM_INIT_VALUE in
the board config file doesn't work and memory is always initialized
to the value 0xdeadbeef. Only use this default value if a board doesn't
define CONFIG_MEM_INIT_VALUE.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Scott Wood
31d084ddda powerpc/mpc85xx: add support for MMUv2 page sizes
e6500 implements MMUv2 and supports power-of-2 page sizes rather than
power-of-4.  Add support for such pages.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Prabhakar Kushwaha
35fe948e3b powerpc/mpc85xx: Add BSC9132/BSC9232 processor support
The BSC9132 is a highly integrated device that targets the evolving
 Microcell, Picocell, and Enterprise-Femto base station market subsegments.

 The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
 core technologies with MAPLE-B2P baseband acceleration processing elements
 to address the need for a high performance, low cost, integrated solution
 that handles all required processing layers without the need for an
 external device except for an RF transceiver or, in a Micro base station
 configuration, a host device that handles the L3/L4 and handover between
 sectors.

 The BSC9132 SoC includes the following function and features:
    - Power Architecture subsystem including two e500 processors with
	512-Kbyte shared L2 cache
    - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
	cache
    - 32 Kbyte of shared M3 memory
    - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
      Processing (MAPLE-B2P)
    - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
      ECC), up to 1333 MHz data rate
    - Dedicated security engine featuring trusted boot
    - Two DMA controllers
         - OCNDMA with four bidirectional channels
         - SysDMA with sixteen bidirectional channels
    - Interfaces
        - Four-lane SerDes PHY
	    - PCI Express controller complies with the PEX Specification-Rev 2.0
        - Two Common Public Radio Interface (CPRI) controller lanes
	    - High-speed USB 2.0 host and device controller with ULPI interface
        - Enhanced secure digital (SD/MMC) host controller (eSDHC)
	    - Antenna interface controller (AIC), supporting four industry
		standard JESD207/four custom ADI RF interfaces
       - ADI lanes support both full duplex FDD support & half duplex TDD
       - Universal Subscriber Identity Module (USIM) interface that
	   facilitates communication to SIM cards or Eurochip pre-paid phone
	   cards
       - Two DUART, two eSPI, and two I2C controllers
       - Integrated Flash memory controller (IFC)
       - GPIO
     - Sixteen 32-bit timers

Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:14 -06:00
James Yang
e8ba6c503f powerpc/mpc8xxxx: FSL DDR debugger auto run of stored commands
This patch adds the ability for the FSL DDR interactive debugger to
automatically run the sequence of commands stored in the ddr_interactive
environment variable.  Commands are separated using ';'.

ddr_interactive=compute; edit c0 d0 dimmparms caslat_X 0x3FC0; go

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:14 -06:00
James Yang
5926ee3800 Add copy command to FSL DDR interactive
Add copy command which allows copying of DIMM/controller settings.
This saves tedious retyping of parameters for each identical DIMM
or controller.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:13 -06:00
James Yang
992f2fb28c Fix data stage name matching issue
This fix allows the name of the stage to be specifed after the
controler and DIMM is specified.  Prior to this fix, if the
data stage name is not the first entry on the command line,
the operation is applied to all controller and DIMMs.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:13 -06:00
James Yang
bf4189307f Move DDR command parsing to separate function
Move the FSL DDR prompt command parsing to a separate function
so that it can be reused.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:13 -06:00
York Sun
e750cfaa01 powerpc/mpc8xxx: Enable entering DDR debugging by key press
Using environmental variable "ddr_interactive" to activate interactive DDR
debugging seomtiems is not enough. For example, after updating SPD with a
valid but wrong image, u-boot won't come up due to wrong DDR configuration.
By enabling key press method, we can enter debug mode to have a chance to
boot without using other tools to recover the board.

CONFIG_FSL_DDR_INTERACTIVE needs to be defined in header file. To enter the
debug mode by key press, press key 'd' shortly after reset, like one would
do to abort auto booting. It is fixed to lower case 'd' at this moment.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:12 -06:00
Prabhakar Kushwaha
db9a807054 powerpc/mpc85xx:Fix Core cluster configuration loop
Different personalities/derivatives of SoC may have reduced cluster. But it is
not necessary for last valid DCFG_CCSR_TP_CLUSTER register to have
DCFG_CCSR_TP_CLUSTER[EOC] bit set to represent "End of Clusters".

EOC bit can still be set in last DCFG_CCSR_TP_CLUSTER register of orignal SoC
which may not be valid for the personality.
So add initiator type check to find valid cluster.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Poonam Aggrwal
e1dbdd8152 powerpc/mpc85xx:Add support of B4420 SoC
B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900
and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and
reduced target frequencies.

Key differences between B4860 and B4420
----------------------------------------
B4420 has:
1. Fewer e6500 cores: 1 cluster with 2 e6500 cores
2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
3. Single DDRC
4. 2X 4 lane serdes
5. 3 SGMII interfaces
6. no sRIO
7. no 10G

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Poonam Aggrwal
e394ceb17f powerpc/mpc85xx: Few updates for B4860 cpu changes
- Added some more serdes1 and serdes2 combinations
  serdes1= 0x2c, 0x2d, 0x2e
  serdes2= 0x7a, 0x8d, 0x98
- Updated Number of DDR controllers to 2.
- Added FMAN file for B4860, drivers/net/fm/b4860.c

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
York Sun
2d9f26b693 powerpc/mpc85xx: Reserve default boot page
The boot page in memory is already reserved so OS won't overwrite.
As long as the boot page translation is active, the default boot page
also needs to be reserved in case the memory is 4GB or more.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:08 -06:00
Tom Rini
06b02c58d2 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2013-01-29 15:36:23 -05:00
Marek Vasut
90bc2bf297 mxs: mmc: Allow overriding default card detect implementation
Some MXS based boards do not implement the card-detect signal. Allow
user to specify alternate card-detect implementation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-28 11:43:01 +01:00
Marek Vasut
f3801e2b9b mxs: ssp: Add SSP registers map for MX23
The MX23 SSP register layout differs from MX28 in certain bits,
adjust the register layout accordingly.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-28 11:43:01 +01:00
Marek Vasut
0e5c05efb4 mxs: dma: Fix APBH DMA driver for MX23
The MX23 has less channels for the APBH DMA, sligtly different register
layout and some bits in those registers are placed differently. Reflect
this in the driver. This patch fixes MMC/DMA issue on MX23.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-28 11:43:00 +01:00
Fabio Estevam
f093088214 mxs: Use __weak annotation to simplify code
Using the __weak annotation can make the code cleaner.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-01-28 06:54:19 +01:00
Marek Vasut
8303ed128a mxs: Boost the memory power supply
The memory power supply on MX23 didn't pump out enough juice into
the DRAM chip, thus caused occasional memory corruption. Fix this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2013-01-28 06:40:38 +01:00
Gabor Juhos
67d80c9f97 MIPS: start.S: don't save flush_cache parameters in advance
Saving the parameters in advance unnecessarily complicates
the code. The destination address is already saved in the
's2' register, and that register is not clobbered by the
copy loop. The size of the copied data can be computed
after the copy loop is done.

Change the code to compute the size parameter right
before calling flush_cache, and set the destination
address parameter in the delay slot of the actuall
call.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-27 16:40:15 +01:00
Gabor Juhos
248fe03f53 MIPS: start.S: simplify relocation offset calculation
The current code uses four instructions and a
temporary register to calculate the relocation
offset and to adjust the gp register.

The relocation offset can be calculated directly
from the CONFIG_SYS_MONITOR_BASE constant and from
the destination address. The resulting offset can
be used to adjust the gp pointer.

This approach makes the code a bit simpler because
it needs two instructions only.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-27 16:40:07 +01:00
Gabor Juhos
b2fe86f887 MIPS: start.S: save reused arguments earlier in relocate_code
Save the reused parameters at the beginning
of the 'relocate_code' function. This makes
the function a bit more readable.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-27 16:39:59 +01:00
Gabor Juhos
f321b0f99f MIPS: start.S: set sp register directly
The current code uses two instructions to load
the stack pointer into the 'sp' register.

This results in the following assembly code:

    468:   3c088040        lui     t0,0x8040
    46c:   251d0000        addiu   sp,t0,0

The first instuction loads the stack pointer into
the 't0' register then the value of the 'sp' register
is computed by adding zero to the value of the 't0'
register. The same issue present on the 64-bit version
as well:

    56c:   3c0c8040        lui     t0,0x8040
    570:   659d0000        daddiu  sp,t0,0

Change the code to load the stack pointer directly
into the 'sp' register. The generated code is functionally
equivalent to the previous version but it is simpler.

  32-bit:
    468:   3c1d8040        lui     sp,0x8040

  64-bit:
    56c:   3c1d8040        lui     sp,0x8040

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-27 16:39:51 +01:00
Gabor Juhos
5b7dd8163d MIPS: start.S: fix boundary check in relocate_code
The loop code copies more data with one than
necessary due to the 'ble' instuction. Use the
'blt' instruction instead to fix that.

Due to the lack of suitable hardware the Xburst
specific code is compile tested only. However the
change is quite obvious.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-27 16:39:43 +01:00
Gabor Juhos
14fdd1a8bf MIPS: start{, 64}.S: fill branch delay slots with NOP instructions
The romReserved and romExcHandle handlers are
accessed by a branch instruction however the
delay slots of those instructions are not filled.

Because the start.S uses the 'noreorder' directive,
the assembler will not fill the delay slots either,
and leads to the following assembly code:

  0000056c <romReserved>:
   56c:   1000ffff        b       56c <romReserved>

  00000570 <romExcHandle>:
   570:   1000ffff        b       570 <romExcHandle>

In the resulting code, the second branch instruction
is placed into the delay slot of the first branch
instruction, which is not allowed on the MIPS
architecture.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-22 21:09:34 +01:00
Gabor Juhos
0ef48d4c89 MIPS: convert IO port accessor functions to 'static inline'
The currently used 'extern inline' directive causes
the following compiler warnings if CONFIG_SWAP_IO_SPACE
is defined:

  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outlc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outl_p' which is not static [enabled by default]
  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outlc' which is not static [enabled by default]
  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outl' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outwc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outw_p' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outwc' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outw' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inlc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inl_p' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inlc' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inl' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inwc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inw_p' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inwc' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inw' which is not static [enabled by default]

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-22 21:07:19 +01:00
Gabor Juhos
be002d0070 MIPS: use inline directive for __in*s functions
All other IO accessor functions are using the
'inline' directive. Use that also for the __in*s
to make it consistent with the other variants.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-22 20:52:08 +01:00
Troy Kisky
71a988aa63 imximage.cfg: run files through C preprocessor
The '#' used as comments in the files cause the preprocessor
trouble, so change to /* */.

The mkimage command which uses this preprocessor output
was moved to arch/arm/imx-common/Makefile

.gitignore was updated to ignore .cfgtmp files.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-22 10:20:13 +01:00
Otavio Salvador
0023997709 mxs: Add MX23 quirks into the clock code
The MX23 has different handling of the SSP clock and GPMI NAND clock sources,
add necessary quirks into the clock code to properly handle these.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:22 +01:00
Otavio Salvador
30af6c0bca mxs: Fix the memory init for MX23
The memory init is slightly different on MX23, thus split the memory
init for mx23 and mx28 into different functions.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:22 +01:00
Marek Vasut
7788bf067d mxs: Add function to ungate the power block on MX23
The power block on MX23 must first be ungated before it can be operated.
Add function to MXS power init that ungates it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:22 +01:00
Otavio Salvador
e6d93c26c7 mx23: config: Enable building of u-boot.sb binary
For i.MX23 we need to pass imx23 as elftosb param.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:21 +01:00
Otavio Salvador
1ddf386e23 mx23: SPL: Initialize DDR at 133MHz
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:21 +01:00
Otavio Salvador
f942f7d962 mx23: SPL: Add boot mode support
This adds the boot mode support for i.MX23 processors.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:21 +01:00
Otavio Salvador
a8b2884d94 mx23: Add boot mode description
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:21 +01:00
Otavio Salvador
f69077e420 mx23: Add support on print_cpuinfo()
Add information to identify i.MX23 chips and its known revisions.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Marek Vasut
95e873d601 mx23: ssp: Fix ssp-regs.h for MX23
Disable SSP2 and SSP3 ports on MX23.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Marek Vasut
06dc8160a0 mx23: Add POWER and CLKCTRL register definitions
Add register definitions for the i.MX23 power control block and
clock control block. These are essential for the basic bootstrap
of the i.MX23. Also, properly include them in imx-regs.h .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Otavio Salvador
180f47a8df mx23: Add iomux-mx23.h
This has been copied from Linux source at revision 786f02b719f.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Otavio Salvador
3fd7f365e1 mx23: Add register base addresses
This adds the base addresses of i.MX23 and easy the detection of wrong
order in board setup, in case no SoC has been set, an error is raised
during build.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Otavio Salvador
bf48fcb61b mxs: clock: Use 'mxs' prefix for methods
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Marek Vasut
14e26bcfa7 mxs: ssp: Pull out the SSP bus to regs conversion
Create function which converts SSP bus number to SSP register pointer.
This functionality is reimplemented multiple times in the code, thus
make one common implementation. Moreover, make it a switch(), since the
SSP ports are not mapped in such nice linear fashion on MX23, therefore
having it a switch will simplify things there.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:19 +01:00
Allen Martin
64e6ec1d4e tegra: fdt: add apbdma node
Add apbdma node for tegra20 and tegra30, copied directly from tegra
Linux dtsi files.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-17 09:07:51 -07:00
Allen Martin
b7723f3f30 tegra: fdt: sort dts files
Sort nodes in dts files according the the following rules:

1) Any nodes that already exist in any /include/d file, in the order
they appear in the /include/d file.

2) Any nodes with a reg property, in order of their address.

3) Any nodes without a reg property, alphabetically by node name.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-17 09:07:34 -07:00
Allen Martin
d3f8752ed6 tegra: fdt: remove clocks nodes
These nodes are unused.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-17 09:07:23 -07:00
Kim Phillips
a6187dccd8 Merge remote-tracking branch 'mpc83xx/next' 2013-01-16 18:34:09 -06:00
Allen Martin
d08b9e9c7e tegra: remove IRDA pinmux synonym
IRDA is a synonym for UARTB in tegra pinmux, remove all usage of this
synonym and replace with UARTB to disambiguate.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-16 13:40:08 -07:00
Tom Warren
083bbbbe77 Tegra30: fdt: Update DT files with I2C info for T30/Cardhu
Note that T30 does not have a separate/different DVC (power I2C)
controller like T20 - all 5 I2C controllers are identical, but
DVC_I2C is still used to designate the controller intended for
power control (PWR_I2C in the schematics). On Cardhu, it's used
to access the PMU and EEPROM, as well as the audio codec, temp
sensor, and fuel gauge devices from the OS.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-16 13:40:08 -07:00
Tom Warren
619bd99e5c Tegra30: clocks: Fix clock tables for I2C and other periphs
Add 16-bit divider support (I2C) to periph table, annotate and
correct some entries, and fix clk_id lookup function.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-16 13:40:08 -07:00
Tom Warren
6d6c0baebe Tegra30: Add generic Tegra30 build support
This patch adds basic Tegra30 (T30) build support - no specific
board is targeted.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-01-16 13:40:08 -07:00
Tom Warren
79ce91bade Tegra30: Cardhu: Add DT files
These are stripped down for bringup, They'll be filled out later
to match-up with the kernel DT contents, and/or as devices are
brought up (mmc, usb, spi, etc.).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-01-16 13:40:08 -07:00
Tom Warren
b2871037d2 Tegra30: Add common CPU (shared) files
These files are used by both SPL and main U-Boot.
Also made minor changes to shared Tegra code to support
T30 differences.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-01-16 13:40:07 -07:00
Tom Warren
5576aab517 Tegra30: Add CPU (armv7) files
These files are for code that runs on the CPU (A9) on T30 boards.
At this time, there are no T30-specific ARMV7 files. As T30-specific
run-time code is added, it'll go here.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidai.com>
2013-01-16 13:40:07 -07:00
Tom Warren
1b245fee91 Tegra30: Add AVP (arm720t) files
This provides SPL support for T30 boards - AVP early init, plus
CPU (A9) init/jump to main U-Boot.

Some changes were made to Tegra20 cpu.c to move common routines
into tegra-common/cpu.c and reduce code duplication.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-01-16 13:40:07 -07:00
Tom Warren
dc89ad1438 Tegra30: Add arch-tegra30 include files
Common Tegra files are in arch-tegra, shared between T20 and T30.
Tegra30-specific headers are in arch-tegra30. Note that some of
these will be filled in as more T30 support is added (drivers,
WB/LP0 support, etc.). A couple of Tegra20 files were changed
to support common headers in arch-tegra, also.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-01-16 13:40:07 -07:00
Marc Dietrich
716d943983 tegra: display: add board pinmux
Boards may require a different pinmux setup for DISPALY than the default one.
Add a way to call into board specific code to set this up.

Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-16 13:40:07 -07:00
Gabor Juhos
9c170e2ef4 MIPS: bootm.c: add support for 'prep' and 'go' subcommands
The bootm command supports subcommands since long time
however those subcommands are not yet usable on MIPS.

The patch is based on the ARM implementation, and it adds
support for the 'prep' and 'go' subcommands only.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-16 10:52:07 +01:00
Gabor Juhos
0ea7213f63 MIPS: bootm.c: separate environment initialization
Move the environment initialization code into a
separate function. This make the code reusable
for bootm subcommands.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-16 10:52:07 +01:00
Gabor Juhos
e08634c7bf MIPS: bootm.c: separate linux jump code
Move the actual jump code into a separate function.
This make the code reusable for bootm subcommands.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-16 10:52:07 +01:00
Gabor Juhos
75a279c8f2 MIPS: bootm.c: use debug macro to print debug message
The '## Transferring control ...' message is printed
only if DEBUG is enabled. Get rid of the 'ifdef DEBUG'
statement and use the debug macro instead.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
2013-01-16 10:52:07 +01:00
Łukasz Dałek
df3ad6c81d pxa: Save lr register in relocate_code function
When u-boot is compiled for PXA25x processor, pxa/start.S is calling
cpu_init_crit by BL instruction. BL is overwriting lr register so
relocate_code is going into infinite loop. This patch preservs lr
register in r12 before calling cpu_init_crit and after function returns
restores it.

Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-01-14 16:22:00 -07:00
Albert ARIBAUD
a17617d655 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-01-14 17:00:02 +01:00
Albert ARIBAUD
1199c377cf Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-01-14 15:21:00 +01:00
Troy Kisky
abbab70363 mx31/mx35/mx51/mx53/mx6: add watchdog
Use a common watchdog driver for all these cpus.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-01-13 11:39:57 +01:00
angelo
fd70aa4146 m68k/lib: fix serial driver relocation
Fix coldfire serial driver bindings no more relocated to ram after last
changes to drivers/serial/serial.c (regression).
Serial initialization in ram has to be called after that gd->reloc_off is
calculated.

Signed-off-by: Angelo Dureghello <sysamfw@gmail.com>
Cc: Jason Jin <jason.jin@freescale.com>
Acked-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Tested-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
2013-01-11 14:41:14 -07:00
Tom Rini
7a8e739cd5 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-01-11 14:38:24 -07:00
Jaehoon Chung
5374d386f8 Exynos: clock: add CLK_DIV_FSYS3 at set_mmc_clk
Mobile storage is used the CLK_DIV_FSYS3 value.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-11 16:56:31 +09:00
Jaehoon Chung
c39e969e8e Exynos: clock: support get_mmc_clk for exynos
To get exactly clock value for mmc, support the get_mmc_clk() like
set_mmc_clk().

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-11 16:56:31 +09:00
Taylor Hutt
80e409508b arm: Tabify code for MMC initialization
The two modified lines were indented with spaces.
They are now indented with tabs.

Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-10 22:28:36 +01:00
Simon Glass
2f8d8d6b3a arm: Move bootstage record for board_init_f() to after arch_cpu_init()
The timer may be inited in arch_cpu_init() so it is not safe to make a
bootstage mark before this is called. Arrange the code to fix this.

Note: The question was raised as to why we don't keep all archs in sync.
PowerPC doesn't have specific bootstage markers at present (although it
does use boot progress). I hope that the generic board series will solve
this problem in general, but in the meantime this is a real problem, and
only in ARM.

We now get a correct time for board_init_f:

Timer summary in microseconds:
       Mark    Elapsed  Stage
          0          0  reset
    100,000    100,000  spl_start
    848,530    748,530  board_init_f
    907,301     58,771  board_init_r
    910,478      3,177  board_init

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-10 22:27:41 +01:00
Tom Wai-Hong Tam
fe34f8dc8c arm: Make interrupts.o and reset.o in libarm also appear in SPL
SPL u-boot may call do_reset() which depends on interrupts.o and reset.o.
So make them also appear in SPL.

Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-10 22:22:15 +01:00
Simon Glass
e2e3e2b1be arm: Add CONFIG_DISPLAY_BOARDINFO_LATE to display board info on LCD
This option displays board info after stdio is running, so that it will
appear on the LCD. If it is displayed earlier, the board info will appear
on the serial console but not on the LCD.

Here follows a blow-by-blow description.

1a. Without CONFIG_DISPLAY_BOARDINFO_LATE, on serial:

U-Boot 2011.12-02550-g037e1c5-dirty (Nov 15 2012 - 14:29:42) for SMDK5250

CPU:   S5PC520 @ 1700MHz

Board: Google Snow, rev 0
I2C:   ready
DRAM:  2 GiB Elpida DDR3 @ 800MHz
MMC:   S5P MSHC0: 0, S5P MSHC1: 1
SF: Detected W25Q32 with page size 4 KiB, total 4 MiB
*** Warning - bad CRC, using default environment

In:    mkbp-keyb
Out:   lcd
Err:   lcd
Net:   No ethernet found.
Hit any key to stop autoboot:  0
SMDK5250 #

1b. Without CONFIG_DISPLAY_BOARDINFO_LATE, on LCD (note machine info
is missing):

In:    mkbp-keyb
Out:   lcd
Err:   lcd
Net:   No ethernet found.
Hit any key to stop autoboot:  0
SMDK5250 #

2a. With CONFIG_DISPLAY_BOARDINFO_LATE, on serial:

U-Boot 2011.12-02550-g037e1c5 (Nov 15 2012 - 14:27:40) for SMDK5250

CPU:   S5PC520 @ 1700MHz
I2C:   ready
DRAM:  2 GiB Elpida DDR3 @ 800MHz
MMC:   S5P MSHC0: 0, S5P MSHC1: 1
SF: Detected W25Q32 with page size 4 KiB, total 4 MiB
*** Warning - bad CRC, using default environment

Model: Google Snow
In:    mkbp-keyb
Out:   lcd
Err:   lcd
Net:   No ethernet found.
Hit any key to stop autoboot:  0
SMDK5250 #

2b. With CONFIG_DISPLAY_BOARDINFO_LATE, on LCD (note machine info is present):

Model: Google Snow
In:    mkbp-keyb
Out:   lcd
Err:   lcd
Net:   No ethernet found.
Hit any key to stop autoboot:  0
SMDK5250 #

Since the LCD is all that a typical user sees, it is useful to display
the model there.

We may be able to rearrange things some other way one day, but at
present this seems like a convenient way of getting the required
behaviour.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-10 22:22:01 +01:00
Simon Glass
06fd853890 arm: Add CONFIG_DELAY_ENVIRONMENT to delay environment loading
This option delays loading of the environment until later, so that only the
default environment will be available to U-Boot.

This can address the security risk of untrusted data being used during boot.

Any time you load untrusted data you expose yourself to a bug in the
code. The attacker gets to choose the data so can sometimes carefully
craft it to exploit a bug. We try to avoid touching user-controlled
data during a verified boot unless strictly necessary. Since the
default environment is good enough in this case (or you would just
change it), this gets around the problem by just not loading the
environment.

When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a
run-time way of enabling loading of the environment. Add this to the
fdt as /config/delay-environment.

Note: This patch depends on http://patchwork.ozlabs.org/patch/194342/

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
2013-01-10 22:21:47 +01:00
Simon Glass
eae78c3406 arm: Move fdt check earlier so that board_early_init_f() can use it
We want to use the fdt inside board_early_init_f(), so check for its
presence earlier in the pre-reloc init sequence.

So far ARM and microblaze are the only only ones that use
CONFIG_OF_CONTROL. Microblaze does not have the same init loop, and in
particular does not have the board_early_init_f() call. So a patch for
microblaze would have no meaning.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-10 22:21:44 +01:00
Gabe Black
724cdffca1 arm: Keep track of the tlb size as well as its location
It may be necessary to know where the TLB area ends as well as where it
starts. This allows board code to complete a secure memory erase without
destroying the page tables.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-10 22:21:32 +01:00
Arun Mankuzhi
44df5e8d30 arm: move flush_dcache_all() to just before disable cache
In Cortex-A15 architecture, when we run cache invalidate
the cache clean operation executes automatically.
So if there are any dirty cache lines before disabling the L2 cache
these will be synchronized with the main memory when
invalidate_dcache_all() runs in the last part of U-boot

The two functions after flush_dcache_all is using the stack. So this
data will be on the cache. After disable when invalidate is called the
data will be flushed from cache to memory. This corrupts the stack in
invalida_dcache_all. So this change is required to avoid the u-boot
hang.

So flush has to be done just before clearing CR_C bit

Signed-off-by: Arun Mankuzhi <arun.m@samsung.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-10 22:21:27 +01:00
Ajay Kumar
7b4bd121b6 EXYNOS: Add dummy definition to fix compilation dependency on CONFIG_EXYNOS_MIPI_DSIM
When only DP is used, we need not enable CONFIG_EXYNOS_MIPI_DSIM.
But if we do not select CONFIG_EXYNOS_MIPI_DSIM, exynos_fb.c throws
error saying exynos_mipi_dsi_init() not defined. So, we add
dummy definition for exynos_mipi_dsi_init when CONFIG_EXYNOS_MIPI_DSIM
is not defined.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-10 10:19:47 +09:00
Ajay Kumar
1673f199d9 EXYNOS5: Change parent clock of FIMD to MPLL
With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to MPLL resolves this issue.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-10 10:19:47 +09:00
Ajay Kumar
9b572852c0 EXYNOS5: Add support for FIMD and DP
Add panel_info structure required by LCD driver
and DP panel platdata for SMDK5250.
Add GPIO configuration for LCD.
Enable FIMD and DP support on SMDK5250.
DP Panel size: 2560x1600.
We use 16BPP resolution to get LCD console.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chomium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-10 10:19:47 +09:00
Albert ARIBAUD
612404c28a Merge 'u-boot-atmel/master' into 'u-boot-arm/master' 2013-01-09 20:01:48 +01:00
Fabio Estevam
2b16e51c2f mx6: Add workaround for ARM errata
Add workaround for the following ARM errata: 743622 and 751472.

The motivation for this change is the following kernel commit 62e4d357a
(ARM: 7609/1: disable errata work-arounds which access
secure registers), which removes the errata from multiplatform kernel.

Since imx has been converted to multiplatform in the kernel, we need to apply
such workarounds into the bootloader.

Workaround code has been taken from arch/arm/mm/proc-v7.S from 3.7.1 kernel.

Explanation of each erratum is provided at "Chip Errata for the i.MX 6Dual/6Quad"
document available at: cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-01-09 19:22:06 +01:00
Albert ARIBAUD
ea33fb1a32 Merge branch 'u-boot-marvell/master' into 'u-boot-arm/master' 2013-01-09 16:57:03 +01:00
Tom Rini
642ef40bdc Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-01-09 08:13:22 -07:00
Luke Lowrey
3e75e69668 arch-kirkwood: Ethernet port macro returning incorrect address
Modified the arch-kirkwood header so KWGBE_PORT_SERIAL_CONTROL1_REG(x)
returns the correct address.

Originally calling KWGBE_PORT_SERIAL_CONTROL1_REG(1) returned the
address for port 0 and vice versa.

Doesn't have any knock on effects to the u-boot code as the only
time they're used is to do the same function to both addresses

Signed-off-by: Luke Lowrey <luke@chamsys.co.uk>
Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>
Acked-by: Heiko Schocher <hs@denx.de>
2013-01-09 04:12:11 +05:30
Albert ARIBAUD
9d86f0c30b kirkwood: make MPP arrays static const
This saves stack and code memory for local copy, and
consumes initialized data memory. For 22 of the 29
kirkwood-based boards, this results in a global saving
of about 30 bytes. For 7 of them, it results in an
increase of 6 to 14 bytes.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-01-09 04:12:10 +05:30
Tom Rini
91c038f087 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-01-08 14:26:42 -07:00
Albert ARIBAUD
61bdb91335 arm: remove useless code in start.S files
Remove code such as unneeded includes or labels.
These removals have no functional effect.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-01-08 22:14:54 +01:00
Albert ARIBAUD
e05e5de7fa arm: move C runtime setup code in crt0.S
Move all the C runtime setup code from every start.S
in arch/arm into arch/arm/lib/crt0.S. This covers
the code sequence from setting up the initial stack
to calling into board_init_r().

Also, rewrite the C runtime setup and make functions
board_init_*() and relocate_code() behave according to
normal C semantics (no jumping across the C stack any
more, etc).

Some SPL targets had to be touched because they use
start.S explicitly or for some reason; the relevant
maintainers and custodians are cc:ed.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-01-08 22:14:50 +01:00
Albert ARIBAUD
79f3877794 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
This required manual merging drivers/mtd/nand/Makefile
and adding am335x_evm support for CONFIG_SPL_NAND_DRIVERS
2013-01-08 13:15:45 +01:00
Rajeshwari Shinde
69c6f976a1 EXYNOS5: Add device node for USB.
This patch adds the device node required for USB

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-08 21:14:34 +09:00
Rajeshwari Shinde
cb9b23cda9 EXYNOS5: FDT: Add SPI device node data
Add SPI device node data for exynos.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-08 10:54:34 +09:00
Rajeshwari Shinde
f0b1619118 EXYNOS5: FDT: Add sound device node data
Add sound device node data for exynos

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-08 10:54:33 +09:00
Rajeshwari Shinde
d055911887 EXYNOS5: FDT : Decode peripheral id
Api is added to decode peripheral id based on the interrupt number
of the peripheral.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-08 10:54:32 +09:00
Rajeshwari Shinde
c2425b66c3 EXYNOS5: FDT: Add I2C device node data
Add I2C device node data for exynos

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-08 10:54:32 +09:00
Piotr Wilczek
7a84e1fa22 arm:exynos4:pinmux: Modify the gpio function for mmc
This patch add pinmux settings for Exynos4 for mmc0 and mmc2

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-08 10:47:45 +09:00
Chander Kashyap
a527757316 EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequency
Adds functions to extract clock frequency of Exynos4x12 IPs.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-12-26 21:12:43 +09:00
Hatim RV
3ea93948cf exynos5: Add DT based driver for SMC911X ethernet
Add device tree based ethernet driver for SMC911X controller on
SMDK5250 boards.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-12-26 19:26:25 +09:00
Hatim RV
1b652071d0 EXYNOS5: FDT: add initial dts file for EXYNOS5250, SMDK5250
This patch adds initial dts file for EXYNOS5250 SoC. This dts
file currently include only ethernet devices and properties. More
devices to be added in subsequent patches.
Also add the dts file for SMDK5250 board which uses the EXYNOS5250
dts file.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-12-26 19:26:25 +09:00
Chander Kashyap
fa442bbb3f EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12
This patch adds gpio structure for Exynos4x12.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-12-26 16:16:02 +09:00
Chander Kashyap
07235ef8a3 EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12
This patch adds clock structure for Exynos4x12.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-12-26 16:16:02 +09:00
Chander Kashyap
b189a83a08 EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses
This patch populates base addresses of Exynos4x12 registers.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-12-26 16:16:02 +09:00
Tom Rini
da77a0e593 Merge branch 'master' of git://git.denx.de/u-boot-arm 2012-12-22 05:55:19 -07:00
Albert ARIBAUD
96764df1b4 Merge samsung, imx, tegra into u-boot-arm/master
This commit merges branches from samsung, imx and tegra
meant to fix merge issues between u-boot/master and
u-boot-arm/master, as well as a few manual merge fixes.
2012-12-22 11:59:14 +01:00
Yoshihiro Shimoda
1a2621bab8 sh: add support for sh7752evb board
The R0P7752C00000RZ board has SH7752, 512MB DDR3-SDRAM, SPI ROM,
Gigabit Ethernet, and eMMC.

This patch supports the following functions:
 - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-12-20 13:20:17 +09:00
Scott Wood
06f60ae3e4 powerpc/mpc83xx: add support for new SPL
This adds arch support for PPC mpc83xx to boot "minimal" (4K) SPLs
using the new infrastructure.

Existing nand_spl targets are updated to deal with the name change
from nand_init.c to spl_minimal.c (as in theory this isn't limited
to NAND anymore).

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-12-19 17:45:44 -06:00
Allen Martin
a098cf41fd Merge remote-tracking branch 'u-boot/master' into u-boot-arm-merged
Conflicts:
	README
	arch/arm/cpu/armv7/exynos/clock.c
	board/samsung/universal_c210/universal.c
	drivers/misc/Makefile
	drivers/power/power_fsl.c
	include/configs/mx35pdk.h
	include/configs/mx53loco.h
	include/configs/seaboard.h
2012-12-19 13:02:36 -08:00
Joe Hershberger
ec8a252cd4 env: Use getenv_yesno() more generally
Move the getenv_yesno() to env_common.c and change most checks for
'y' or 'n' to use this helper.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-12-13 11:46:55 -07:00
Tom Rini
caddc17f30 Merge branch 'master' of git://git.denx.de/u-boot-mips 2012-12-12 06:51:02 -07:00
Joe Hershberger
f88e09de8d mips: serial: Fix busted manual relocation
serial_initialize() must be called after relocation to adjust the
pointers to putc(), getc(), etc.  This is busted ever since the
serial driver-model-ification series.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-12-12 13:20:24 +01:00
Daniel Schwierzeck
f0c27993e4 MIPS: constify mips_io_port_base
mips_io_port_base is exported as 'extern const unsigned long mips_io_port_base;'
in arch/mips/include/asm/io.h. Thus make the variable const too.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-12-12 13:14:16 +01:00
Simon Glass
b1f17bf5ff Add strcasecmp() and strncasecmp()
strncasecmp() is present as strnicmp() but disabled. Make it available
and define strcasecmp() also. There is a only a small performance penalty
to having strcasecmp() call strncasecmp(), so do this instead of a
standalone function, to save code space.

Update the prototype in arch-specific headers as needed to avoid warnings.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-11 13:17:34 -07:00
Piotr Wilczek
89bd58a1e9 exynos:pinmux: Add pinmux support for i2c
This patch add pinmux for I2C for Exynos4

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
2012-12-11 13:17:31 -07:00
Piotr Wilczek
847ab8f6e2 exynos:cpu: Add Exynos4 I2C spacing
This patch add the spacing for i2c for Exynos4

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
2012-12-11 13:17:31 -07:00
Piotr Wilczek
83d745dd88 exynos:clock: Add i2c clock
This patch adds i2c clock for Exynos4

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
2012-12-11 13:17:31 -07:00
Marek Vasut
fa5e2845a8 mxs: i2c: Implement algorithm to set up arbitrary i2c speed
This algorithm computes the values of TIMING{0,1,2} registers for the
MX28 I2C block. This algorithm was derived by using a scope, but the
result seems correct.

The resulting values programmed into the registers do not correlate
with the contents in datasheet. When using the values from the datasheet,
the I2C clock were completely wrong.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
2012-12-11 13:17:30 -07:00
Nikita Kiryanov
dcee1ab320 gpio: add gpio_is_valid() to omap_gpio API
Add gpio_is_valid() to omap_gpio API

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2012-12-10 12:45:35 -07:00
Davide Bonfanti
21f11c7b49 davinci: fixed cpu reset
The reset procedure works on watchdog timer while before it was modifying
TIMER_1 registers.
Tested on DM365.

Signed-off-by: Davide Bonfanti <davide.bonfanti@bticino.it>
2012-12-10 08:56:38 -07:00
Lokesh Vutla
86021143a3 omap: emif: configure emif only when required
DMM_LISA_MAP registers program whether memory is mapped
on particular EMIF or not. Irrespective of these registers
EMIF is getting configured. Correcting the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-12-10 08:55:25 -07:00
Robert P. J. Day
c7f1cf5f29 OMAP: Tweak omap-common/Makefile since reset.S -> reset.c
Git commit d417d1db5f replaced the
omap-common file reset.S with reset.c, but the Makefile was not
adjusted for that.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2012-12-10 08:55:25 -07:00
Robert P. J. Day
f281f299df omap4: Add comments on some "#endif"s for readability.
No functional changes, simply for readability.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2012-12-10 08:55:25 -07:00
Robert P. J. Day
e3fe62574d omap3: Add a few comments to "#endif"s for readability.
No functional changes, just more comments for readability when a
preprocessor check spans more than a few lines, and for consistency.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2012-12-10 08:55:25 -07:00
Peter Barada
8c4445d266 Pass sdrc timing values through board_sdrc_timings structure
Instead of passing individual registers by value to board_get_mem_timings,
pass a board_mem_timings structure pointer for the board files to fill in.
Pass same structure pointer to write_sdrc_timings.  This saves about
90 bytes of space in SPL.

Signed-off-by: Peter Barada <peter.barada@logicpd.com>
2012-12-10 08:54:02 -07:00
Mansoor Ahamed
04c3757829 am33xx: add ELM support
AM33XX has Error Location Module (ELM) that can be used in conjuction
with GPMC controller to implement BCH codes fully in hardware.
This code is mostly taken from arago tree.

Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com>
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-12-10 08:54:02 -07:00
Ilya Yanok
8eb16b7f73 am33xx: NAND support
TI AM33XX has the same GPMC controller as OMAP3 so we could just use the
existing omap_gpmc driver. This patch adds adds required
definitions/intialization.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-12-10 08:54:01 -07:00
Ilya Yanok
1befaffbfb OMAP: include sys_proto.h from boot-common
Include asm/arch/sys_proto.h for gpmc_init prototype.
Without this we get a warning while building for AM335x.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-12-10 08:54:01 -07:00
Andreas Bießmann
4af9e675fa omap3/mem.c: remove unused defines
These GPMC_CS defines are a leftover from prior gpmc_init(). Commit 187af954
removed the need for these definitions but missed to remove them.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
2012-12-10 08:54:01 -07:00
Minkyu Kang
2c601c7208 Merge branch 'master' of git://git.denx.de/u-boot into resolve
Conflicts:
	README
	board/samsung/universal_c210/universal.c
	drivers/misc/Makefile
	drivers/power/power_fsl.c
	include/configs/mx35pdk.h
	include/configs/mx53loco.h
	include/configs/seaboard.h
2012-12-10 14:13:27 +09:00
Richard Genoud
bcfc8976e5 at91sam9x5: enable USB support for 9x5ek board.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-12-09 22:38:27 +01:00
Daniel Schwierzeck
ea40a05422 MIPS: constify address pointer in test_bit()
Fix several warnings when enabling UBIFS on MIPS:

In file included from ubifs.h:2137:0,
                 from ubifs.c:26:
misc.h: In function 'ubifs_zn_dirty':
misc.h:38:2: warning: passing argument 2 of 'test_bit' discards 'const' qualifier from pointer target type [enabled by default]
../include/asm/bitops.h:569:23: note: expected 'volatile void *' but argument is of type 'const long unsigned int *'

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-12-08 21:48:19 +01:00
Zhi-zhou Zhang
0d69d918ab MIPS: fix a latent bug on initialize $gp
If bal is 8 bytes aligned, the _gp will not be 8 bytes aligned.
then the following ld insntrustion generates a Adel exception.
So here make _gp be always aligned in 8 bytes.

Signed-off-by: Zhi-zhou Zhang <zhizhou.zh@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-12-08 21:33:07 +01:00
Stefano Babic
05a860c228 Merge branch 'master' of git://git.denx.de/u-boot into master
Conflicts:
	drivers/power/power_fsl.c
	include/configs/mx35pdk.h
	include/configs/mx53loco.h
	include/configs/woodburn_common.h
	board/woodburn/woodburn.c

These boards still use the old old PMIC framework, so they
do not merge properly after the power framework was merged into
mainline.

Fix all conflicts and update woodburn to use Power Framework.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-12-08 12:02:45 +01:00
Otavio Salvador
393ff47ba3 mxs: SPL: Generalize memory initialization
Use a generic 'dram_vals[]' array that has the full initialization
sequence and rename the initialization method so it doesn't has a
frequency on its name.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-12-07 14:50:02 +01:00
Simon Glass
058d59b08d x86: Build vga video code only if CONFIG_VIDEO_VGA is defined
When running from coreboot we don't want this code, so make it
optional.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Simon Glass
a94e9d70e3 x86: Remove video_init() prototype from u-boot-x86.h
This function is not intended to be exported from the video drivers, so
remove the prototype. This fixes an error:

cfb_console.c:1793:12: error: static declaration of 'video_init' follows non-static declaration

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Stefan Reinauer
c94663170b x86: drop unused code in coreboot.c
The function setup_pcat_compatibility() is weak and implemented as empty
function in board.c hence we don't have to override that with another
empty function.

monitor_flash_len is unused, drop it.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Stefan Reinauer
2b9d2252aa x86: Remove coreboot_ from file name
... because that information is already "encoded" in the directory name.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Vadim Bendebury
1350f1cce1 x86: Provide a way to throttle port80 accesses
Some systems (like Google Link device) provide the ability to keep a
history of the target CPU port80 accesses, which is extremely handy
for debugging. The problem is that the EC handling port 80 access is
orders of magnitude slower than the AP. This causes random loss of
trace data.

This change allows to throttle port 80 accesses such that in case the
AP is trying to post faster than the EC can handle, a delay is
introduced to make sure that the post rate is throttled. Experiments
have shown that on Link the delay should be at least 350,000 of tsc
clocks.

Throttling is not being enabled by default: to enable it one would
have to set MIN_PORT80_KCLOCKS_DELAY to something like 400 and rebuild
the u-boot image. With upcoming EC code optimizations this number
could be decreased (new new value should be established
experimentally).

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Vadim Bendebury
7c71034d3c x86: Provide tick counter and frequency reference for Intel core architecture
Some u-boot modules rely on availability of get_ticks() and
get_tbclk() functions, reporting a free running clock and its
frequency respectively. Traditionally these functions return number
and frequency of timer interrupts.

Intel's core architecture processors however are known to run the
rdtsc instruction at a constant rate of the so called 'Max Non Turbo
ratio' times the external clock frequency which is 100MHz. This is
just as good for the timer tick functions in question.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Duncan Laurie
b83058cd23 x86: Issue SMI to finalize Coreboot in final stage
This will write magic value to APMC command port which
will trigger an SMI and cause coreboot to lock down
the ME, chipset, and CPU.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Duncan Laurie
488b8b242b x86: Fix MTRR clear to detect which MTRR to use
Coreboot was always using MTRR 7 for the write-protect
cache entry that covers the ROM and U-boot was removing it.
However with 4GB configs we need more MTRRs for the BIOS
and so the WP MTRR needs to move.  Instead coreboot will
always use the last available MTRR that is normally set
aside for OS use and U-boot can clear it before the OS.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Stefan Reinauer
300081aa68 x86: Emit port 80 post codes in show_boot_progress()
This helps us monitor boot progress and determine where U-Boot dies if
there are any problems.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Simon Glass
2712f08898 x86: fdt: Create basic .dtsi file for coreboot
This contains just the minimum information for a coreboot-based board.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:42 -08:00
Gabe Black
ba74a0ffcb x86: coreboot: Set CONFIG_ARCH_DEVICE_TREE correctly
We will use coreboot.dtsi as our fdt include file.

Signed-off-by: Gabe Black <gabeblack@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:42 -08:00
Gabe Black
b208c7f1d0 x86: Add support for CONFIG_OF_CONTROL
Allow a device tree to be provided through the standard mechanisms.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:42 -08:00
Stefan Reinauer
05b71646a9 x86: Add CONFIG_DELAY_ENVIRONMENT to delay environment loading
This option delays loading of the environment until later, so that only the
default environment will be available to U-Boot.

This can address the security risk of untrusted data being used during boot.

When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a
run-time way of enabling loadinlg of the environment. Add this to the
fdt as /config/delay-environment.

Note: This patch depends on http://patchwork.ozlabs.org/patch/194342/

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
2012-12-06 14:30:42 -08:00
Gabe Black
91d82a29e7 x86: Add back cold- and warm-boot flags
These were removed, but actually are useful.

Cold means that we started from a reset/power on.
Warm means that we started from another U-Boot.

We determine whether u-boot on x86 was warm or cold booted (really if
it started at the beginning of the text segment or at the ELF entry point).
We plumb the result through to the global data structure.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:42 -08:00
Gabe Black
112a575e49 x86: Override calculate_relocation_address to use the e820 map
Because calculate_relocation_address now uses the e820 map, it will be able
to avoid addresses over 32 bits and regions that are at high addresses but
not big enough for U-Boot. It also means we can remove the hack which
limitted U-Boot's idea of the size of memory to less than 4GB.

Also take into account the space needed for the heap and stack, so we avoid
picking a very small region those areas might overlap with something it
shouldn't.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:42 -08:00
Gabe Black
d65297b64d x86: Make calculate_relocation_address an overridable function
Different systems may have different mechanisms for picking a suitable place
to relocate U-Boot to.

Signed-off-by: Gabe Black <gabeblack@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:41 -08:00
Gabe Black
842d33874f x86: Make the upper bound on relocated symbols closed instead of open
This seems to be a bug.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:41 -08:00
Gabe Black
32f98735f9 x86: Reorder x86's post relocation memory layout
This changes the layout in decreasing addresses from:

1. Stack
2. Sections in the image
3. Heap

to

1. Sections in the image
2. Heap
3. Stack

This allows the stack to grow significantly more since it isn't constrained by
the other u-boot areas. More importantly, the generic memory wipe code assumes
that the stack is the lowest addressed area used by the main part of u-boot.
In the original layout, that means that u-boot tramples all over itself. In
the new layout, it works.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:41 -08:00
Gabe Black
8313315b9a x86: Initialise SPI if enabled
If we have SPI support, make sure that we init it.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vic Yang <victoryang@chromium.org>
2012-12-06 14:30:41 -08:00
Gabe Black
ac31a7b81c x86: Implement arch_phys_memset so that it can wipe memory above 4GB
Implement arch_phys_memset so that it can set memory at physical addresses
above 4GB using PAE paging. Because there are only 5 page tables in PAE mode,
1 PDPT and 4 PDTs, those tables are statically allocated in the BSS. The
tables must be 4K page aligned and are declared that way, and because U-Boot
starts as 4K aligned and the relocation code relocates it to a 4K aligned
address, the tables work as intended.

While paging is turned on, all 4GB are identity mapped except for one 2MB
page which is used as the window into high memory. This way, U-Boot will
continue to work as expected when running code that expects to access memory
freely, but the code can still get at high memory through its window.

The window is put at 2MB so that it's 2MB page aligned, low in memory to be
out of the way of things U-Boot is likely to care about, and above the lowest
1MB where lots of random things live.

Signed-off-by: Gabe Black <gabeblack@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:41 -08:00
Gabe Black
ec516c4899 x86: Increase the size of the phys_size_t and phys_addr_t types
These types should be 64 bits long to reflect the fact that physical
addresses and the size of physical areas of memory are more than 32 bits
long.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Duncan Laurie
0c3929092d x86: Fix off-by-one error in do_elf_reloc_fixups()
The use of post-increment with a do-while loop results in
the loop going one step too far when handling relocation fixups.

In about 1/100 cases this would cause it to hang.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Duncan Laurie
984d8b09fb x86: Ignore memory >4GB when parsing Coreboot tables
U-boot is unable to actually use that memory and it can
cause problems with relocation if it tries to.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Simon Glass
1484311286 x86: Fix indirect jmp warning in zimage.c
This fixes the following warning:

zimage.c:312: Warning: indirect jmp without `*'

Also fixed these warnings to keep checkpatch quiet:

warning: arch/x86/lib/zimage.c,311: unnecessary whitespace before a quoted newline
warning: arch/x86/lib/zimage.c,312: unnecessary whitespace before a quoted newline
warning: arch/x86/lib/zimage.c,313: unnecessary whitespace before a quoted newline

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Stefan Reinauer
17de114f9f x86: Clean up MTRR 7 right before jumping to the kernel
This cleans up the rom caching optimization implemented in coreboot (and
needed throughout U-Boot runtime).

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Graeme Russ
98568f0fa9 x86: Import MSR/MTRR code from Linux
Imported from Linux 3.1 with a few modifications to suit U-Boot

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Stefan Reinauer
61e0ea900a x86: Provide a function to clean up just before booting a zimage
This function can be used by boards which want to do some clean-up
before booting a zImage.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Stefan Reinauer
095593c030 x86: Add basic cache operations
Add functions to enable/disable the data cache.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Gabe Black
9a7da182fa x86: Fill in the dram info using the e820 map on coreboot/x86
This way when that dram "banks" are displayed, there's some useful information
there. The number of "banks" we claim to have needs to be adjusted so that it
covers the number of RAM e820 regions we expect to have/care about.

This needs to be done after "RAM" initialization even though we always run
from RAM. The bd pointer in the global data structure doesn't automatically
point to anything, and it isn't set up until "RAM" is available since, I
assume, it would take too much space in the very constrained pre-RAM
environment.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Vadim Bendebury
3cdc18a8de x86: Add a CBMEM timestamp generated right before the kernel startup.
To maintain the initialization state of the timestamp facility, thesq
pointer to the CBMEM section containing the timestamp table should be
kept in the .data section (so that it is maintained across u-boot
relocation).

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Vadim Bendebury
6dbe0cce3f x86: Enable coreboot timestamp facility support in u-boot.
This change turns on the code which allows u-boot to add
timestamps to the timestamp table created by coreboot.

Since u-boot does not use the tsc_t like structure to represent
HW counter readings, this structure is being replaced by 64 bit
integer.

The timestamp_init() function is now initializing the base timer
value used by u-boot to calculate the HW counter increments.

Timestamp facility is initialized as soon as the timestamp table
pointer is found in the coreboot table. The u-boot generated
timer events' ID will start at 1000 to clearly separate u-boot
events from coreboot events in the timer trace.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:38 -08:00
Vadim Bendebury
2f899e03a9 x86: Add function to read time stamp counter
Put this function in the u-boot-x86.h header file. We could instead create
timer.h perhaps.

We support setting a base time, and reading the time relative to this base.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:38 -08:00
Bill Richardson
55ae10f8db x86: gpio: Add GPIO driver for Intel ICH6 and later.
Implement <asm-generic/gpio.h> functions for Intel ICH6 and later.
Only GPIOs 0-31 are handled by this code.

Signed-off-by: Bill Richardson <wfrichar@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:38 -08:00
Stefan Roese
083f2e08d2 mpc5200: Add SPL support
This patch adds SPL booting support (NOR flash) for the
MPC5200 platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05 17:30:51 +01:00
Stefan Roese
ea8256f072 SPL: Port SPL framework to powerpc
This patch enables the SPL framework to be used on powerpc platforms
and not only ARM.

timer_init() does not exist on PPC systems. The timer (decrementer) is
initialized and enabled in interrupt_init() here. And currently
interrupt_init() is called after relocation to SDRAM. Since the only
powerpc SPL implementation (a3m071) doesn't need a timer, let's remove
this timer_init() call for PPC systems.

Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05 17:30:22 +01:00
Stefan Roese
966b11c749 powerpc: Extract EPAPR_MAGIC constants into processor.h
By extracting these defines into a header, they can be re-used by other
C sources as well. This will be done by the SPL framework OS boot
support.

Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05 17:27:02 +01:00
Marek Vasut
a918a53c36 mxs: Staticize SPL functions
The MXS SPL didn't mark local functions "static". Fix it. This also makes the
SPL smaller by roughly 300 bytes.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-12-04 09:29:11 +01:00
Marek Vasut
1230e7bc2d mxs: Properly setup VDDD in power supply setup code
The memory setup code adjusted the VDDD voltage. Remove this adjustment
and configure the VDDD voltage correctly in the power supply setup code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-12-04 09:27:21 +01:00
Marek Vasut
77cb33bd25 mxs: Implement common function to setup VDDx
Implement common function to setup the VDDIO, VDDD and VDDA voltage.
Right now, there are two almost identical functions to setup VDDIO
and VDDD, which is prone to breakage. Pull out the differences into
constant structure and pass them as an argument to the common function.

Moreover, the function has almost identical loops for setting higher
and lower VDDx voltage. Merge these two loops.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-12-04 09:26:54 +01:00
Marek Vasut
893aabbead mx28: Rename regs-power.h to regs-power-mx28.h
The i.MX23 has different register layout and bit placement in the
power supply. Thus, in order to be able to add support for MX23,
rename the MX28's regs-power.h to regs-power-mx28.h . Moreover,
add ifdef around inclusion of regs-*-mx28.h in imx-regs.h so the
MX23 boards will include proper set of registers.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2012-12-04 09:01:04 +01:00
Marek Vasut
3642b1c147 mx28: Remove SET, CLR, TOG ops from PLLxCTRL1 registers
These registers don't have _SET, _CLR and _TOG at the respective offsets
available, these registers has to be toggled via R-M-W if needed. Thus do
not export these offsets anymore.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2012-12-04 08:52:05 +01:00
Tom Rini
ce12a8c1a9 Merge branch 'master' of git://git.denx.de/u-boot-x86 2012-12-03 06:47:05 -07:00
Stefan Reinauer
339c511106 x86: Don't spam POST80 codes with slow IO functions
This patch prevents u-boot from "spamming" random progress codes on
a port 80 "post card".
The previous version of this patch just removed the delays in the "slow"
IO functions, as they do not need to be slow, however, this patch is
less intrusive.

It uses another unused port that is often used by BIOSes (and the Linux
Kernel) for small delay timing purposes.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:05 -08:00
Stefan Reinauer
5b1be1bd01 x86: Fix typo in pcat_timer.c
Fix a small comment typo.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:05 -08:00
Gabe Black
687c108b10 x86: Include types.h explicitly in the i386 version of io.h
The i386 version of io.h depends on the phys_addr_t type which is defined in
types.h. It wasn't including that explicitly, and was working presumably
because the other files including it had already included types.h themselves
directly or indirectly. This change fixes that.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:05 -08:00
Gabe Black
452b80ef8c x86: Add a dummy implementation for timer_get_us
The microsecond timer is not currently implemented, but add a dummy
implementation for now.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:05 -08:00
Gabe Black
f30fc4de41 x86: Add a default implementation for cleanup_before_linux()
This function provides an opportunity for some last minute cleanup and
reconfiguration before control is handed over to Linux. It's possible this
may need to do something in the future, but for now it's left empty. It's set
up as a weak symbol so it can be overridden if necessary on a case by case
basis.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:04 -08:00
Gabe Black
028a56289a x86: Add an fdt pointer to the global data structure
This change adds a pointer to the global data structure in x86 to point to
the device tree. This mirrors an identical pointer in ARM.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:04 -08:00
Gabe Black
5b5ece9ef4 x86: Allow compiling out realmode/bios code
We don't want this for coreboot, so provide a way of compiling it out.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:04 -08:00
Simon Glass
402ed0048a x86: coreboot: Decode additional coreboot sysinfo tags
Add support for decoding tags for GPIOs, compile/build info, cbmem and
other features.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:03 -08:00
Stefan Reinauer
93c1735f41 x86: coreboot: Drop sysinfo.c
sysinfo.c only contains the lib_sysinfo data structure which
is used/filled by tables.c. This split was introduced by importing
code from libpayload originally, but to keep the code simple, add
the single line of actual code to tables.c

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:03 -08:00
Yoshihiro Shimoda
867da0d4fe sh: fix trigger_address_error()
The function should set BL bit, but it should not clear other flags.
So, the patch uses set_bl_bit() instead of a local asm code.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-11-30 15:06:04 +09:00
Tom Rini
e57d9d15ee Merge branch 'master' of git://www.denx.de/git/u-boot-x86 2012-11-28 13:44:40 -07:00
Gabe Black
82e73f0e3d x86: coreboot: Implement recursively scanning PCI busses
A hook is installed to configure PCI bus bridges as they encountered by u-boot.
The hook extracts the secondary bus number from the bridge's config space and
then recursively scans that bus.

On Coreboot, the PCI bus address space has identity mapping with the
physical address space, so declare it as such to ensure that the "pci_map_bar"
function used by some PCI drivers is behaving properly. This fixes the
EHCI PCI driver initialization on Stumpy.

This was tested as follows:

Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on
bus 1, and empty busses 2 through 5. This matches the bridges
reported on bus 0 and the PCI configuration output from coreboot.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:05 -08:00
Gabe Black
452f50f7cf x86: coreboot: Tell u-boot about PCI bus 0 when initializing
U-boot needs a host controller or "hose" to interact with the PCI busses
behind them. This change installs a host controller during initialization of
the coreboot "board" which implements some of X86's basic PCI semantics. This
relies on some existing generic code, but also duplicates a little bit of code
from the sc520 implementation. Ideally we'd eliminate that duplication at some
point.

It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's
generic PCI configuration code what to do if it encounters a bridge,
specifically to scan the bus on the other side of it.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2012-11-28 11:40:04 -08:00
Stefan Reinauer
badcb343d7 x86: coreboot: Move non-board specific files to coreboot arch directory
coreboot.c and coreboot_pci.c don't contain board specific but only
coreboot specific code. Hence move it to the coreboot directory in
arch/x86/cpu (which should probably be moved out of cpu/ in another
commit)

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:04 -08:00
Gabe Black
c953fbee54 x86: Add some missing includes
I suspect these includes were usually available because something else
included them earlier or because they were brought in transitively.

Change-Id: I6aae2ac94dc792eac6febb4345e8125f69f70988
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:04 -08:00
Gabe Black
b16f521a5e x86: Allow excluding reset vector code from u-boot
When running from coreboot we don't want this code.

This version works by ifdef-ing out all of the code that would go
into those sections and all the code that refers to it. The sections are
then empty, and the linker will either leave them empty for the loader
to ignore or remove them entirely.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:03 -08:00
Simon Glass
8a487a4417 x86: Add initial memory barrier macros
These are available on other architectures, so add them on x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:03 -08:00
Graeme Russ
8abebe3ead x86: Add ilog2 to bitops
ilog2 is required by AHCI driver

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:03 -08:00
Graeme Russ
c73c6de60c x86: Remove duplicate PCI init
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:03 -08:00
Graeme Russ
8d61625d6a x86: Put global data on the stack
Putting global data on the stack simplifies the init process (and makes it
slightly quicker). During the 'flash' stage of the init sequence, global
data is in the CAR stack. After SDRAM is initialised, global data is copied
from CAR to the SDRAM stack

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:03 -08:00
Graeme Russ
e4fb611649 x86: Forward declare gd_t
So it can be used as a type in struct global_data and remove an ugly typecast

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
2012-11-28 11:40:03 -08:00
Tom Rini
a86fcff695 Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx 2012-11-28 08:30:21 -07:00
Tom Rini
d41b3cc16f Merge branch 'master' of git://git.denx.de/u-boot-mips 2012-11-27 20:34:51 -07:00
York Sun
afbfdf5450 powerpc/mpc85xx: Fix a bug introduced by CONFIG_PPC_SPINTABLE_COMPATIBLE
Fix a bug introduced by this patch
powerpc/mpc85xx: Temporary fix for spin table backward compatibility

Should have checked both CONFIG_PPC_SPINTABLE_COMPATIBLE and CONFIG_MP in
cpu_init.c.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:08 -06:00
Timur Tabi
b25f6de7c0 powerpc/85xx: update the work-around for P4080 erratum SERDES-9
The documented work-around for P4080 erratum SERDES-9 has been updated.
It is now compatible with the work-around for erratum A-4580.

This requires adding a few bitfield macros for the BnTTLCRy0 register.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
Yuanquan Chen
c0a4e6b889 powerpc/p4080ds: fix PCI-e x8 link training down failure
Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.

Signed-off-by: Yuanquan Chen <B41889@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
Zang Roy-R61911
9760b274df powerpc/corenet_ds: move SATA config to board configuration
board configuration file is included before asm/config_mpc85xx.h.
however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h.
it will never take effective in the board configuration file for
this kind of code :

 #ifdef CONFIG_FSL_SATA_V2
 ...
 #endif

To solve this problem, move CONFIG_FSL_SATA_V2 to board
configuration header file.

This patch reverts Timur's
commit:3e0529f742e893653848494ffb9f7cd0d91304bf

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
Timur Tabi
d607b9684b powerpc/85xx: implement check for erratum A-004580 work-around
The work-around for erratum A-004580 ("Internal tracking loop can falsely
lock causing unrecoverable bit errors") is implemented via the PBI
(pre-boot initialization code, typically attached to the RCW binary).
This is because the work-around is easier to implement in PBI than in
U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004580, we can do this by verifying
that the values in the specific registers that the work-around says to
update.

This change requires access to the SerDes lane sub-structure in
serdes_corenet_t, so we make it a named struct.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
Kim Phillips
345d6efdc7 powerpc/mpc8xxx: take fdt_fixup_crypto_node() off the checkstack list
by moving compat_strlist into the .bss section.

0xfe004d80 fdt_fixup_crypto_node [u-boot]:		264

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
York Sun
2a5fcb835f powerpc/mpc85xx: Temporary fix for spin table backward compatibility
Once u-boot sets the spin table to cache-enabled memory, old kernel which
uses cache-inhibit mapping without coherence will not work properly. We
use this temporary fix until kernel has updated its spin table code.
For now this fix is activated by default. To disable this fix for new
kernel, set environmental variable "spin_table_compat=no". After kernel
has updated spin table code, this default shall be changed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:06 -06:00
Timur Tabi
0118033b67 powerpc/85xx: implement check for erratum A-004849 work-around
The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a
deadlock under certain traffic patterns causing the system to hang") is
implemented via the PBI (pre-boot initialization code, typically attached
to the RCW binary).  This is because the work-around is easier to implement
in PBI than in U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004849, we can do this by verifying
that the values in the specific registers that the work-around says to
update.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:06 -06:00
Timur Tabi
1956e431f8 powerpc/85xx/p5040: add CONFIG_SYS_PPC64, del CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
The P5040 has an e5500 core, so CONFIG_SYS_PPC64 should be defined in
config_mpc85xx.h.  This macro was absent in the initial P5040 patch because
it crossed paths with the patch that introduced the macro.

Also delete CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC, since it's not used in the
upstream U-Boot.  It's a holdover from the SDK.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:05 -06:00
Andy Fleming
e76cd5d4cf 8xxx: Change all 8*xx_DDR addresses to 8xxx
There were a number of shared files that were using
CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.

This patch does:

s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g

All 85xx, 86xx, and 83xx have been built with this change.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Andy Fleming <afleming@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-27 17:45:17 -06:00
Jaehoon Chung
d0ebbb8dfa EXYNOS: mmc: support DesignWare Controller for Samsung-SoC
Support DesignWare MMC Controller for Samsung Specific.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Rajeshawari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 17:26:47 -06:00
Tom Rini
dfe161032d Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2012-11-26 14:53:33 -07:00
Scott Wood
c97cd1ba48 spl/85xx: new SPL support
Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL
and CONFIG_SPL_BUILD, respectively.  CONFIG_NAND_SPL can be removed once
the last mpc85xx nand_spl target is gone.

CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't
seem right to overload it for meaning SPL as well as nand_spl does.  Even
if it's somewhat appropriate for the main u-boot, the SPL itself isn't
(necessarily) ramboot, and we don't have separate configs for SPL and
main u-boot.  It was also inconsistent, as other platforms such as
mpc83xx didn't use CONFIG_RAMBOOT in this way.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:25 -06:00
Scott Wood
4b919725b6 spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL
cpu_init_nand.c is renamed to spl_minimal.c as it is not really NAND-specific.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
v2: factor out START, and change cpu_init_nand.c to spl_minimal.c
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:24 -06:00
Scott Wood
a179eb0a4b powerpc/mpc85xx: consistently use COBJS-y
A subsequent patch will conditionalize some of the files that are
currently unconditional.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:24 -06:00
Scott Wood
b9735cbaeb spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.c
There is nothing really NAND-specific about this file.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:24 -06:00
Scott Wood
59629c2897 spl/mpc85xx: move udelay to cpu code
It applies to non-Freescale 85xx boards as well as Freescale boards,
so it doesn't belong in board/freescale.  Plus, it needs to come out
of nand_spl if it's to be used by the new SPL.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:23 -06:00
Scott Wood
8bc50f0b6d powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxx
It's arch code and not a driver, so move it where it belongs.  When it
originally went into drivers/misc there was no 8xxx CPU directory.

This will make new-SPL support a little easier since we can keep the CPU
stuff together and not need to pull stuff in from drivers/misc.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:22 -06:00
Scott Wood
7f0a22ff25 powerpc/mpc85xx: fix TLB alignment
In the RAMBOOT/SPL case we were creating a TLB entry starting at
CONFIG_SYS_MONITOR_BASE, and just hoping that the base was properly
aligned for the TLB entry size.  This turned out to not be the case
with NAND SPL because the main U-Boot starts at an offset into the image
in order to skip the SPL itself.

Fix the TLB entry to always start at a proper alignment.  We still assume that
CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary
thus requiring multiple TLB entries.

Signed-off-by: Scott Wood <scottwood@frescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:22 -06:00
Scott Wood
6ec63f411e powerpc: change .fixup test to a GCC version test
This was introduced by commit 2446151974, but it
fails in a minimal SPL build where the only thing in arch/powerpc/lib is
cache.c, which apparently doesn't generate any fixup records.

The problem is reported to occur with GCC 3.x, so insist on GCC 4.0 or newer.
Patterned after checkthumb as suggested by Tom Rini.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Tom Rini <trini@ti.com>
--
v2: test gcc version instead of testing nothing
2012-11-26 15:41:22 -06:00
Scott Wood
9a511bd6a3 powerpc/mpc85xx: add comma before "already enabled"
Now outputs like this:

L2:    512 KB already enabled, moving to 0xf8f80000

rather than this:

L2:    512 KB already enabledmoving to 0xf8f80000

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
2012-11-26 15:41:20 -06:00
Scott Wood
f545d300b0 powerpc/mpc85xx: move debug tlb entry after TLB is in known state
Previously, in many if not all configs we were creating overlapping TLB entries
which is illegal.  This caused a crash during boot when moving p2020rdb NAND SPL
into L2 SRAM.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
--
Prabhakar, please test that debug still works.
2012-11-26 15:41:20 -06:00
Zhi-zhou Zhang
8ab36d2e54 MIPS: do not initialize timestamp variable before relocate_code
Because timestamp is declared as `static', we needn't initialize
it by writing it a zero. If we do it before relocate_code, we
will write into a flash address(0xffffffffbfc0xxxx).

Signed-off-by: Zhi-zhou Zhang <zhizhou.zh@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-11-25 21:50:43 +01:00
Albert ARIBAUD
b8a7c46796 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2012-11-25 13:01:58 +01:00
Marek Vasut
1d4fd0dc3b mx28: Fix typo in POWER_DCLIMITS_NEGLIMIT_OFFSET
The POWER_DCLIMITS_NEGLIMIT_OFFSET bit in mx28 power supply block is
not called POWER_DCLIMITS_NETLIMIT_OFFSET, but POWER_DCLIMITS_NEGLIMIT_OFFSET.
Correct the name in the header file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2012-11-24 16:21:37 +01:00
Marek Vasut
90a21030e3 mx28: Fix typo in POWER_MINPWR_VBG_OFF
The POWER_MINPWR_VBG_OFF bit in mx28 power supply block is not called
POWER_MINPWR_FBG_OFF, but POWER_MINPWR_VBG_OFF. Correct the name in the
header file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2012-11-24 16:21:10 +01:00
Ilya Yanok
673a524b6a musb-new: omap2plus backend driver
Backend driver for MUSB OTG controllers found on TI OMAP2/3/4
(tested only on OMAP3 Beagle).

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:08 +01:00
Ilya Yanok
08fc71711a OMAP3: am35x: add musb functions
AM35XX specific functions for integrated USB PHY/MUSB IP.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:07 +01:00
Ilya Yanok
272165f6a9 OMAP3: am35x_def.h: add USB defines
Add defines for MUSB IP block on AM35X SoCs.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:07 +01:00
Ilya Yanok
833a53c627 musb-new: am35x backend driver
Backend driver for MUSB OTG controllers found on TI AM35x.

It seems that on AM35X interrupt status registers can be updated
_before_ core registers. As we don't use true interrupts in U-Boot
and poll interrupt status registers instead this can result in
interrupt handler being called with non-updated core registers.
This confuses the code and result in hanged transfers.
Add a small delay in am35x_interrupt as a workaround.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:07 +01:00
Ilya Yanok
7df5cf35de am33xx: init OTG hardware and new musb gadget driver
AM33xx has support for dual port MUSB OTG controller. This patch
adds initialization for the controller using new MUSB gadget
driver and ether gadget.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:07 +01:00
Ilya Yanok
37931f02c2 musb-new: dsps backend driver
Backend driver for MUSB OTG controllers found on TI AM33xx and
TI81xx SoCs (tested with AM33xx only).

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:06 +01:00
Ilya Yanok
c60795f41d usb: use linux/usb/ch9.h instead of usbdescriptors.h
Linux usb/ch9.h seems to have all the same information (and more)
as usbdescriptors.h so use the former instead of the later one.

As a consequense of this change USB_SPEED_* values don't correspond
directly to EHCI speed encoding anymore, I've added necessary
recoding in EHCI driver. Also there is no point to put speed into
pipe anymore so it's removed and a bunch of host drivers fixed to
look at usb_device->speed instead.

Old usbdescriptors.h included is not removed as it seems to be
used by old USB device code.

This makes usb.h and usbdevice.h incompatible. Fortunately the
only place that tries to include both are the old MUSB code and
it needs usb.h only for USB_DMA_MINALIGN used in aligned attribute
on musb_regs structure but this attribute seems to be unneeded
(old MUSB code doesn't support any DMA at all).

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:06 +01:00
Tom Rini
178d0cc1a4 Merge branch 'master' of git://git.denx.de/u-boot-video 2012-11-19 09:28:04 -07:00
Tom Rini
bb367b95f9 Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging 2012-11-19 09:27:18 -07:00
Simon Glass
0dde7f5379 arm: Add control over cachability of memory regions
Add support for adjusting the L1 cache behavior by updating the MMU
configuration. The mmu_set_region_dcache_behaviour() function allows
drivers to make these changes after the MMU is set up.

It is implemented only for ARMv7 at present.

This is needed for LCD support, where we want to make the LCD frame buffer
write-through (or off) rather than write-back.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:38 -07:00
Wei Ni
87540de3af tegra: Add SOC support for display/lcd
Add support for the LCD peripheral at the Tegra2 SOC level. A separate
LCD driver will use this functionality to configure the display.

Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Mayuresh Kulkarni:
- changes to remove bitfields and clean up for submission

Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass:
- simplify code, move clock control into here, clean-up
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:37 -07:00
Simon Glass
e1ae0d1f71 tegra: Add support for PWM
The pulse width/frequency modulation peripheral supports generating
a repeating pulse. It is useful for controlling LCD brightness.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:36 -07:00
Simon Glass
eefe3e598e tegra: fdt: Add LCD definitions for Tegra
Add LCD definitions and also a proposed binding for LCD displays.

The PWM is as per what will likely be committed to linux-next soon.

The displaymode binding comes from a proposal here:

http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html

The panel binding is new, and fills a need to specify the panel
timings and other tegra-specific information. Should a binding appear
that allows the pwm to handle this automatically, we can revisit
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:36 -07:00
Simon Glass
beca1fdeff tegra: fdt: Add pwm binding and node
This binding will apparently soon be in linux-next. Bring it in now
since we need to do something, and may as well try to target what
Linux will have.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:35 -07:00
Simon Glass
b344496110 tegra: Add display support to funcmux
Add support for a default pin mapping for display1.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:35 -07:00
Simon Glass
95be58c988 tegra: Use const for pinmux_config_pingroup/table()
These two functions don't actually modify their arguments so add a const
keyword.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:35 -07:00
Benoît Thébaudeau
39e8576164 mx5: Mark lowlevel_init board-specific code
The mx5 lowlevel_init.S contains board-specific code based on the reference
design. Let's keep it since it avoids creating new lowlevel_init files and it
may be used by many boards. But add a config to make it optional in order not to
cause issues on boards not following this part of the reference design.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-11-19 08:56:27 +01:00
Fabio Estevam
cc446726de mx6: clock: Only show CSPI clock if CSPI is enabled
If a board does not enable CSPI, there is no need to show the CSPI clock
frequency as part of the 'clock' command.

Reported-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
2012-11-19 08:49:00 +01:00
Fabio Estevam
081237c1f7 mx5: Print CSPI clock in 'clock' command
Print CSPI clock in 'clock' command.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2012-11-19 08:49:00 +01:00
Fabio Estevam
d84f56f48f mx5: Align SPI CS naming with i.MX53 reference manual
Align SPI chip select naming with i.MX53 reference manual.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-11-19 08:48:59 +01:00