This patch adds the possiblity to choose the media where the environment will
be located. This allow to choose this fundamental configuration without editing
config files.
Documentation file added.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Stelian Pop <stelian@popies.net>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
The default DDR freq is 400MHz or 800M data rate,
the old settings is pure wrong for the default case.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
The BR_PHYS_ADDR macro is useful on all machines that have local bus
which is pretty much all 83xx/85xx/86xx chips.
Additionally most 85xx & 86xx will need it if they want to support
36-bit physical addresses.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Prevent further viral propogation of the unused
symbol CONFIG_L1_INIT_RAM by just removing it.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
The DDR controller of 8548/8544/8568/8572/8536 processors
have the ECC data init feature, and the new DDR code is
using the feature, and we don't need the way with DMA to
init memory any more.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Introducing 64-bit (36-bit) support for the MPC8641HPCN
failed to accomodate the other two 86xx boards.
Introduce definitions for CONFIG_SYS_CCSRBAR_PHYS_{LOW,HIGH}
CONFIG_SYS_CCSR_DEFAULT_DBAT{U,L} and CONFIG_SYS_CCSR_DEFAULT_IBAT{U,L}
with nominal 32-bit values.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Becky Bruce <becky.bruce@freescale.com>
This patch disables some unused features from the PCI405 configuration
to keep U-Boot image size below 192k.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch extracts the identical config options for the
keymile boards mgcoge, mgsuvd and kmeter1 in a new
common config file keymile-common.h.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Check the presence of the PIGGY on the keymile boards mgcoge,
mgsuvd and kmeter1. If the PIGGY is not present, dont register
this Ethernet device.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch fix the broken boot from NOR Flash on AT91RM9200 boards, if
CONFIG_AT91RM9200 is defined and nor preloader is used.
Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
This patch enables support for EXT2, and increases the
CONFIG_SYS_BOOTMAPSZ size for the default configuration
of the katmai boards to use them as the RAID-reference
AMCC setups.
EXT2 enabling allows one to boot kernels from the EXT2
formatted Compact Flash cards.
CONFIG_SYS_BOOTMAPSZ increasing allows one to boot the
Linux kernels, which use PAGE_SIZE of 256KB. Otherwise,
the memory area with DTB file (which is placed at the
end of the bootmap area) will turn out to be overlapped
with the BSS segment of the 256KB kernel, and zeroed
in early_init() of Linux.
Actually, increasing of the bootmap size could be done
via setting of the bootm_size U-Boot variable, but it looks
like the current U-Boot implementation have some bootm_size-
related functionality lost. In many places through the U-Boot
code the CONFIG_SYS_BOOTMAPSZ definition is used directly
(instead of trying to read the corresponding value from the
environment). The same is truth for the boot_jump_linux()
function in lib_ppc/bootm.c, where U-Boot transfers control
to Linux passing the CONFIG_SYS_BOOTMAPSZ (not bootm_size)
value to the booting kernel.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Expanded OCM TLB to allow access to 64K OCM as well as 256K of
internal SRAM.
Adjusted internal SRAM initialization to match updated user
manual recommendation.
OCM & ISRAM are now mapped as follows:
physical virtual size
ISRAM 0x4_0000_0000 0xE300_0000 256k
OCM 0x4_0004_0000 0xE304_0000 64k
A single TLB was used for this mapping.
Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
At least some (old ?) versions of the AT91Bootstrap do not set up the
PLLB correctly to 48 MHz in order to make USB host function correctly.
This patch sets up the PLLB to the same values Linux uses, and makes USB
work ok on the following CPUs:
- AT91CAP9
- AT91SAM9260
- AT91SAM9263
This patch also defines CONFIG_USB_STORAGE and CONFIG_CMD_FAT for all
the relevant AT91CAP9/AT91SAM9 atmel boards.
Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Introduce AT91_CPU_CLOCK and use it for displaying the CPU
speed in the LCD driver.
Also make AT91_MAIN_CLOCK and AT91_MASTER_CLOCK reflect the
corresponding board clocks.
Signed-off-by: Stelian Pop <stelian@popies.net>
This patch adds support for the kmeter1 board from Keymile,
based on a Freescale MPC8360 CPU.
- serial console on UART 1
- 256 MB DDR2 RAM
- 64 MB NOR Flash
- Ethernet RMII Mode over UCC4
- PHY SMSC LAN8700
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
modify the CAS timings. my understanding is that these
settings decrease various wait times in the DDR interface.
Because these wait times are in clock cycles, and the DDR
clock on the 8315 RDB runs slower than on some other 83xx
platforms, we can dial down these values without a problem,
thereby decreasing the latency of memory a little.
Signed-off-by: Howard Gregory <Greg.Howard@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
To enable UBI on Apollon you need to uncomment the CONFIG_SYS_USE_UBI
macro.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Since we've changed the memory map of the board, be nice and
add some checking to try to catch out-of-date .dts files. We do
this by checking the CCSRBAR location in the .dts and comparing
it to the CCSRBAR location in u-boot. If they don't match, a
warning msg is printed. This isn't foolproof, but it's simple and
will catch most of the cases where an out-of-date .dts is present,
including all of the cases where a new u-boot is used with an old
standard MPC8641 .dts file as supplied with Linux.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
This patch creates a memory map with all the devices
in 36-bit physical space, in addition to the 32-bit map.
The CCSR relocation is moved (again, sorry) to
allow for the physical address to be 36 bits - this
requires translation to be enabled. With 36-bit physical
addressing enabled, we are no longer running with VA=PA
translations. This means we have to distinguish between
the two in the config file. The existing region name is
used to indicate the virtual address, and a _PHYS variety
is created to represent the physical address.
Large physical addressing is not enabled by default.
Set CONFIG_PHYS_64BIT in the config file to turn this on.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
The memory map on the 8641hpcn is modified to look more like
the 85xx boards; this is a step towards a more standardized
layout going forward. As part of this change, we now relocate
the flash.
The regions for some of the mappings were far larger than they
needed to be. I have reduced the mappings to match the
actual sizes supported by the hardware.
In addition I have removed the comments at the head
of the BAT blocks in the config file, rather than updating
them. These get horribly out of date, and it's a simple
matter to look at the defines to see what they are set to
since everything is right here in the same file.
Documentation has been changed to reflect the new map, as this
change is user visible, and affects the OS which runs post-uboot.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
We define CONFIG_MONITOR_BASE_EARLY to define the initial location
of the bootpage in flash. Use this to create an early mapping
definition for the FLASH, and change the early_bats code to use this.
This change facilitates the relocation of the flash since the early
mappings are no longer tied to the final location of the flash.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
There's a lot of setup and foo for the second flash
bank. The problem is, this board doesn't actually have one.
Clean this up. Also, the flash is 8M in size. Get rid
of the confusing aliased overmapping, and just map 8M.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
It's currently defined twice inside in an if/else block, but
both halves set the same value. Move the define outside
the if.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
All in-tree IBM/AMCC PPC4xx boards using the EMAC get this new CONFIG
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
This patch provides support for AFEB9260 board, a product of
OpenSource hardware and software. Some commertial projects
are made with this design. A board is basically AT91SAM9260-EK
with some modifications and different peripherals and different
parts used. Main purpose of this project is to gain experience in
hardware design.
More info: http://groups.google.com/group/arm9fpga-evolution-board
(In Russian only, sorry).
Subversion repository: svn://194.85.238.22/home/users/george/svn/arm9eb
Signed-off-by: Sergey Lapin <slapin@ossfans.org>
We put the bootpg for the secondary cpus into memory and use
BPTR to get to it. This is a step towards converting to the
ePAPR boot methodology. Also, the code is written to
deal properly with more than 4GB of RAM.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
There are several items in the config file that were hardcoded
but that should really be based on other config options, since
the regions are contiguous and depend on being so. This cleans
that up a bit. Also, add BR_PHYS_ADDR() macro to convert
addresses into the proper format for BR registers.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Currently, the CCSR gets relocated while translation is
enabled, meaning we need 2 BAT translations to get to both the
old location and the new location. Also, the DEFAULT
CCSR location has a dependency on the BAT that maps the
FLASH region. Moving the relocation removes this unnecessary
dependency. This makes it easier and more intutive to
modify the board's memory map.
Swap BATs 3 and 4 on 8610 so that all 86xx boards use the same
BAT for CCSR space.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
You can't actually have both, and with some coming changes to
change the memory map for the board and support 36-bit physical,
we need the extra BAT that is being consumed by having both.
I also make non-PCI configs build cleanly, for the sake of sanity.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG,
MDHA, SKHA, INTC, and FlexBus structures and
definitions in immap_5xxx.h to more unify modules
header files. Append DSPI support for m547x_8x.
SSI cleanup. Remove USB Host structure from immap_539.h.
Apply changes to use FlexBus structures in mcf52x2's
cpu_init.c and platform configuration files.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
This patch defines 1M TLB&LAW size for NAND on MPC8536DS, assigns 0xffa00000
for CONFIG_SYS_NAND_BASE and adds other NAND supports in config file.
It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image.
Singed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CONFIG_ENV_ADDR should be (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE).
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Xilinx ppc440 and ppc405 have many similarities. This patch merge the
config files of both infrastuctures
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch defines 1M TLB&LAW size for NAND on MPC8572DS, assigns
0xffa00000 for CONFIG_SYS_NAND_BASE and adds other NAND supports in
config file.
It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image, to
make room for the increased code size with NAND enabled.
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Converted MPC8610HCPD, MPC8641HPCN, and SBC8641D to use
fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup().
With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS,
MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows()
and ft_fsl_pci_setup().
With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
This patch adds support for the avnet fx12 minimodul.
It needs the "ppc4xx: Generic architecture for xilinx ppc405"
patch from Ricardo.
Signed-off-by: Georg Schardt <schardt@team-ctech.de>
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx
ppc440 boards, this patch presents a common architecture for all the
xilinx ppc405 boards.
Any custom xilinx ppc405 board can be added very easily with no code
duplicity.
This patch also adds a simple generic board, that can be used on almost
any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h
This patch is prepared to work with the latest version of EDK (10.1)
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
Since the new autocalibration still has some problems on some Kilauea
boards with 200MHz DDR2 frequency we disable the autocalibration and
use the hardcoded values as done before. This seems to work reliably
on all known DDR2 frequencies.
After the autocalibration issue is fixed we will enable it again.
Signed-off-by: Stefan Roese <sr@denx.de>
With this patch u-boot can fixup the dr_mode and phy_type properties
for the Dual-Role USB controller.
While at it, also remove #ifdefs around includes, they are not needed.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Though NAND chip is replaceable on the MPC837XE-MDS boards, the
current settings don't work with the default chip on the board.
Nevertheless Freescale's U-Boot sets the option register correctly,
so I just dumped the register from the working u-boot. My guess is
that the old settings were applicable for some pilot boards, not
found in the production.
This patch also enables FSL ELBC driver so that we could access
the NAND storage in the u-boot.
The NAND support costs about 45KB, so the u-boot no longer fits
into two 128KB NOR flash sectors, thus we also have to adjust
environment location: add another 128KB to the monitor length.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
It is due to hardware design and logic defect, that is the
I/O[0:7] of NAND chip is connected to LAD[7:0], so when
the NAND chip connected to nLCS3, you have to set up the
OR3[BCTLD] = '1' for normal operation, otherwise it will have
bus contention due to the pin 48/25 of U60 is enabled.
Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not
asserted upon access to the NAND chip, keep the default state.
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB,
standalone or acting as a PCI agent. User's Guide says:
- When the CPLD recognizes its location on the PIB it automatically
configures RCW to the PCI Host.
- If the CPLD fails to recognize its location then it is automatically
configured as an Agent and the PCI is configured to an external arbiter.
This sounds good. Though in the standalone setup the CPLD sets PCI_HOST
flag (it's ok, we can't act as PCI agents since we receive CLKIN, not
PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without
any arbiter bad things will happen (here the board hangs during any config
space reads).
In this situation we must disable the PCI. And in case of anybody really
want to use an external arbiter, we provide "pci_external_aribter"
environment variable.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This involves configuring the SerDes and fixing up the flags and
PHY addresses for the TSECs.
For Linux we also fix up the device tree.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes
it difficult to use (b/c then the memory is discontinuous and
there is quite big memory hole between the DDR/SDRAM regions).
This patch reworks LBC SDRAM setup so that now we dynamically
place the LBC SDRAM near the DDR (or at 0x0 if there isn't any
DDR memory).
With this patch we're able to:
- Boot without external DDR memory;
- Use most "DDR + SDRAM" setups without need to support for
sparse/discontinuous memory model in the software.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
I reorganized my config files, putting the common stuff into netstal-common.h
(got the idea by looking a amcc-common.h from Stefan).
Added stuff to boot the new powerpc linux via NFS (only tested with HCU4).
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The Arches Evaluation board is based on the AMCC 460GT SoC chip.
This board is a dual processor board with each processor providing
independent resources for Rapid IO, Gigabit Ethernet, and serial
communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR
FLASH, UART, EEPROM and temperature sensor, along with a shared debug
port. The two 460GT's will communicate with each other via shared
memory, Gigabit Ethernet and x1 PCI-Express.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Several customers have reported problems with the environment in
EEPROM, including corrupted content after board reset. Probably the
code to prevent I2C Enge Conditions is not working sufficiently.
We move the environment to flash now, which allows to have a backup
copy plus gives much faster boot times.
Also, change the default console initialization to 115200 bps as used
on most other boards.
Signed-off-by: Wolfgang Denk <wd@denx.de>
The pixis sgmii command depend on the FPGA support on the board, some 85xx
boards support SGMII riser card but did not support this command, define
CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command.
Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits
are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and
PIXIS_VCFGEN1_MASK in header file for both boards.
Signed-off-by: Liu Yu <yu.liu@freescale.com>
* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay, 2T based on board ddr frequency and n_ranks.
* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
* Set memory controller interleaving mode to bank interleaving, and disable
bank(chip select) interleaving mode by default, because the default on-board
DDR DIMMs are 2x512MB single-rank.
* Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
The EEprom contains some Manufacturerinformation,
which are read from u-boot at boot time, and saved
in same hush shell variables.
Signed-off-by: Heiko Schocher <hs@denx.de>
With this Command it is possible to add new I2C Busses,
which are behind 1 .. n I2C Muxes. Details see README.
Signed-off-by: Heiko Schocher <hs@denx.de>
As documented in doc/I2C_Edge_Conditions, adding a
board specific deblocking mechanism via CFG_I2C_INIT_BOARD
for the mgcoge and mgsuvd board.
This code was originally written by Keymile in association
with Anatech and Atmel in 1998. The Code toggels the SCL
until the SCA line goes to HIGH (max. 16 times).
And after this, a start condition is sent.
This is another approach to deblock the I2C Bus. The
soft I2C driver actually sends 9 clocks with SDA High,
and then a stop at the end, to deblock the I2C Bus.
Maybe we should use the approach from Keymile as
the new standard?
Signed-off-by: Heiko Schocher <hs@denx.de>
Change UEC phy interface from GMII to RGMII on MPC8568MDS board
Because on MPC8568MDS, GMII interface is only recommended for 1000Mbps speed,
but RGMII interface can work at 10/100/1000Mbps, and RGMII interface works more stable.
Now both UEC1 and UEC2 can work properly under u-boot.
It is also in consistent with the kernel setting for 8568 UEC phy interface.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Currently this is not creating any problem. But it will result
in compilation error when used as below.
printf("CFG_SDRAM_CFG2 - %08x\n", CFG_SDRAM_CFG2);
Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
continuation of the theme based on git grep "^#define CFG_.*;$" include/
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Commit 445a7b3830 introduced the following
compile warnings:
cmd_i2c.c:112: warning: missing braces around initializer
cmd_i2c.c:112: warning: (near initialization for 'i2c_no_probes[0]')
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Switch to the standard CFG_HZ=1000 value, while at it, minor white-space
cleanup, remove CFG_CLKS_IN_HZ from config-headers. Tested on mx31ads,
provides 2% or 0.4% precision depending on the
CONFIG_MX31_TIMER_HIGH_PRECISION flag. Measured with stop-watch on 100s
boot-delay.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
The ID EEPROM on MPC8572DS board locates on I2C bus 1. Its the storage for
system information like mac addresses etc. This patch enables it.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1
according to the board spec, and adds the 2nd i2c bus offset.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
The display is still sync mode DDR freq. This patch try to fix
this. The display DDR freq is now the actual freq in both
sync and async mode.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
bootdelay set to -1 'permanently' disables autobooting, even if
bootcmd is specified. Change to a positive value to allow
autobooting when a bootcmd is set.
Reported-by: Coray Tate <Coray.Tate@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
the operating system may leave flash in a h/w locked state after writing.
This allows u-boot to continue to write flash by enabling h/w unlocking
by default.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Running mtest command on socrates without specifying
an address range crashes the board. This patch changes
default mtest address range to prevent this behavior.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Commit be0bd8234b
changed SPD EEPROM address to 0x51 and DDR SDRAM
detection stopped working. Change this address
back to 0x50.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
After switching to using the CFI flash driver, the correct remapping
of the flash banks was forgotten.
Also, some boards were not adapted, and the old legacy flash driver
was not removed yet.
Signed-off-by: Wolfgang Denk <wd@denx.de>
This patch fixes a problem introdiced with patch
bbeff30c [ppc4xx: Remove superfluous dram_init() call or replace it by
initdram()].
The boards affected are:
- PCI405
- PPChameleonEVB
- quad100hd
- taihu
- zeus
Signed-off-by: Stefan Roese <sr@denx.de>
- Correct Invalid #define of MPUTIM_PTV_MASK for
omap1510 & omap730 register definition
MPUTIM_PTV_MASK is defined as
#define MPUTIM_PTV_MASK (0x7<<PTV_BIT)
while it should have been
#define MPUTIM_PTV_MASK (0x7<<MPUTIM_PTV_BIT)
- Below Patch corrects the same
Signed-off-by: Gururaja Hebbar <gururajakr@sanyo.co.in>
The i.MX31 has three SPI buses and each bus has several chip selects
and the MC13783 chip can be connected to any of these. The current
RTC driver for MC13783 is hardcoded for CSPI2/SS2.
This patch makes make MC13783 SPI bus and chip select configurable
via CONFIG_MC13783_SPI_BUS and CONFIG_MC13783_SPI_CS.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
Pantelis Antoniou stated:
AFAIK, it is still used but the products using PPC are long gone.
Nuke it plz (from orbit).
So remove it since it cleans up a usage of env_get_char outside of
the environment code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch adds Lime GDC support together with support for the PWM
backlight control through the w83782d chip. The reset pin of the
latter is attached to GPIO, so we need to reset it in
early_board_init_r.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
- Update the local bus ranges in the FDT for Linux for the various
devices connected to the local bus via chip-select.
- Set the LCRR_DBYP bit in the LCRR for local bus frequencies
lower than 66 MHz and uses I/O accessor functions consequently.
- UPM data update.
- Update of default environment and configuration. Use I2C multibus
as we do have two I2C buses. Also enable sdram and ext2 commands.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
The new sys_eeprom.c supports both the old CCID EEPROM format and the new NXID
format, and so it obsoletes board/freescale/common/cds_eeprom.c. Freescale
86xx boards already use sys_eeprom.c, so this patch migrates the remaining
Freescale 85xx boards to use it as well. cds_eeprom.c is deleted.
Signed-off-by: Timur Tabi <timur@freescale.com>
This patch add FDT support and command line editing capabilities
for CPCI405 and CPCI405AB boards.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Since this define is only used on one board that was never really in
production, removing this compile time option doesn't hurt and makes
the code more readable.
Signed-off-by: Stefan Roese <sr@denx.de>
Some of multi-function USB controllers (e.g. ISP1562) allow root hub
resetting only via EHCI registers. So, this patch adds the
corresponding kind of reset to OHCI's hc_reset() if the newly
introduced CONFIG_PCI_EHCI_DEVNO option is set (e.g. for Socrates
board).
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Acked-by: Markus Klotzbuecher <mk@denx.de>
This patch provides an unificated way of handling xilinx v5 ppc440 boards.
It unificates 3 different things:
1) Source code
A new board called ppc440-generic has been created. This board includes
a generic tlb initialization (Maps the whole memory into virtual) and
defines board_pre_init, checkboard, initdram and get_sys_info weakly,
so, they can be replaced by specific functions.
If a new board needs to redefine any of the previous functions
(specific initialization) it can create a new directory with the
specific initializations needed. (see the example ml507 board).
2) Configuration file
Common configurations are located under configs/xilinx-ppc440.h, this
header file interpretes the xparameters file generated by EDK and
configurates u-boot in correspondence. Example: if there is a Temac,
allows CMD_CONFIG_NET
Specific configuration are located under specific configuration file.
(see the example ml507 board)
3) Makefile
Some work has been done in order to not duplicate work in the Main
Makefile. Please see the attached code.
In order to support new boards they can be implemented in the next way:
a) Simple Generic Board (90% of the time)
Using EDK generates a new xparameters.h file, replace
ppc440-generic/xparameters.h and run make xilinx-ppc440-generic_config
&& make
b) Simple Boards with special u-boot parameters (9 % of the time)
Create a new file under configs for it (use ml507.h as example) and
change your paramaters. Create a new Makefile paragraph and compile
c) Complex boards (1% of the time)
Create a new folder for the board, like the ml507
Finally, it adds support for the Avnet FX30T Evaluation board, following
the new generic structure:
Cheap board by Avnet for evaluating the Virtex5 FX technology.
This patch adds support for:
- UartLite
- 16MB Flash
- 64MB RAM
Prior using U-boot in this board, read carefully the ERRATA by Avnet
to solve some memory initialization issues.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch enables the PCI-OHCI controller on PLU405 board.
Also the default CPU frequency is updated to 266 MHz and
command line editing is enabled.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The 8544DS and 8572DS platforms support an optional SGMII riser card to
expose ethernet over an SGMII interface. Once the card is in, it is also
necessary to configure the board such that it uses the card, rather than
the on-board ethernet ports. This can either be done by flipping dip switches
on the motherboard, or by modifying registers in the pixis. Either way
requires a reboot.
This adds a command to allow users to choose which ports are routed through
the SGMII card, and which through the onboard ports. It also allows users
to revert to the current switch settings.
This code does not work on the 8572, as the PIXIS is different.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The 8544DS and 8572DS systems have an optional SGMII riser card which
exposes new ethernet ports which are connected to the eTSECs via an
SGMII interface. The SGMII PHYs for this board are offset from the standard
PHY addresses, so this code modifies the passed in tsec_info structure to
use the SGMII PHYs on the card, instead.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This boards used old type preprocessor.
This patch fix compile error.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This boards used old type preprocessor.
This patch fix compile error.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
AP325RXA is SH7723's reference board.
This has SCIF, NOR Flash, Ethernet, USB host, LCDC, SD Host, Camera and other.
In this patch, support SCIF, NOR Flash, and Ethernet.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This adds initial support for the RTE RSK+ SH7203 board.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This board has SH7785, 512MB DDR2-SDRAM, NOR Flash,
Graphic, Ethernet, USB, SD, RTC, and I2C controller.
This patch supports the following functions:
- 128MB DDR2-SDRAM (29-bit address mode only)
- NOR Flash
- USB host
- Ethernet
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
SMDK6400 can only boot U-Boot from NAND-flash. This patch adds a nand_spl
driver for it too. The board can also boot from the NOR flash, but due to
hardware limitations it can only address 64KiB on it, which is not enough
for U-Boot. Based on the original sources by Samsung for U-Boot 1.1.6.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
This is needed since now with HUSH enabled (amcc-common.h) the image
read from NAND exceeds the previous limit.
Signed-off-by: Stefan Roese <sr@denx.de>
MPC5121 rev 2 silicon has a new register for controlling how long
CS is asserted after deassertion of ALE in multiplexed mode.
The default is to assert CS together with ALE. The alternative
is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE.
The default is wrong for the NOR flash and CPLD on the ADS5121.
This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD)
it does so conditionally based on silicon rev 2.0 or greater.
Signed-off-by: Martha J Marx <mmarx@silicontkx.com>
Signed-off-by: John Rigby <jrigby@freescale.com>
Add FEC pin set and mii reset in __mii_init(). Change
legacy flash vendor from 2 to AMD LEGACY (0xFFF0),
change cfi_offset to 0, and change CFG_FLASH_CFI to
CONFIG_FLASH_CFI_LEGACY. Correct M54451EVB and
M54455EVB env settings in configuration file.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dejan Minic <minic@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
