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mgcoge, mgsuvd: add board specific I2C deblocking mechanism.
As documented in doc/I2C_Edge_Conditions, adding a board specific deblocking mechanism via CFG_I2C_INIT_BOARD for the mgcoge and mgsuvd board. This code was originally written by Keymile in association with Anatech and Atmel in 1998. The Code toggels the SCL until the SCA line goes to HIGH (max. 16 times). And after this, a start condition is sent. This is another approach to deblock the I2C Bus. The soft I2C driver actually sends 9 clocks with SDA High, and then a stop at the end, to deblock the I2C Bus. Maybe we should use the approach from Keymile as the new standard? Signed-off-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Heiko Schocher
Wolfgang Denk
parent
4ca107effe
commit
c24853644d
5 changed files with 213 additions and 2 deletions
209
board/keymile/common/common.c
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209
board/keymile/common/common.c
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/*
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* (C) Copyright 2008
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8260.h>
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#include <ioports.h>
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#include <malloc.h>
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
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#include <i2c.h>
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#endif
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extern int i2c_soft_read_pin (void);
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#if defined(CFG_I2C_INIT_BOARD)
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#define DELAY_ABORT_SEQ 62
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#define DELAY_HALF_PERIOD (500 / (CFG_I2C_SPEED / 1000))
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#if defined(CONFIG_MGCOGE)
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#define SDA_MASK 0x00010000
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#define SCL_MASK 0x00020000
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static void set_pin (int state, unsigned long mask)
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{
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volatile ioport_t *iop = ioport_addr ((immap_t *)CFG_IMMR, 3);
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if (state)
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iop->pdat |= (mask);
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else
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iop->pdat &= ~(mask);
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iop->pdir |= (mask);
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}
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static int get_pin (unsigned long mask)
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{
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volatile ioport_t *iop = ioport_addr ((immap_t *)CFG_IMMR, 3);
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iop->pdir &= ~(mask);
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return (0 != (iop->pdat & (mask)));
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}
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static void set_sda (int state)
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{
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set_pin (state, SDA_MASK);
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}
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static void set_scl (int state)
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{
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set_pin (state, SCL_MASK);
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}
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static int get_sda (void)
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{
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return get_pin (SDA_MASK);
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}
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static int get_scl (void)
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{
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return get_pin (SCL_MASK);
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}
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#if defined(CONFIG_HARD_I2C)
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static void setports (int gpio)
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{
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volatile ioport_t *iop = ioport_addr ((immap_t *)CFG_IMMR, 3);
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if (gpio) {
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iop->ppar &= ~(SDA_MASK | SCL_MASK);
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iop->podr &= ~(SDA_MASK | SCL_MASK);
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} else {
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iop->ppar |= (SDA_MASK | SCL_MASK);
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iop->pdir &= ~(SDA_MASK | SCL_MASK);
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iop->podr |= (SDA_MASK | SCL_MASK);
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}
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}
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#endif
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#endif
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#if defined(CONFIG_MGSUVD)
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static void set_sda (int state)
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{
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I2C_SDA(state);
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}
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static void set_scl (int state)
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{
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I2C_SCL(state);
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}
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static int get_sda (void)
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{
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return i2c_soft_read_pin ();
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}
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static int get_scl (void)
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{
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int val;
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*(unsigned short *)(I2C_BASE_DIR) &= ~SCL_CONF;
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udelay (1);
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val = *(unsigned char *)(I2C_BASE_PORT);
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return ((val & SCL_BIT) == SCL_BIT);
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}
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#endif
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static void writeStartSeq (void)
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{
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set_sda (1);
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udelay (DELAY_HALF_PERIOD);
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set_scl (1);
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udelay (DELAY_HALF_PERIOD);
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set_sda (0);
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udelay (DELAY_HALF_PERIOD);
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set_scl (0);
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udelay (DELAY_HALF_PERIOD);
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}
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/* I2C is a synchronous protocol and resets of the processor in the middle
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of an access can block the I2C Bus until a powerdown of the full unit is
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done. This function toggles the SCL until the SCL and SCA line are
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released, but max. 16 times, after this a I2C start-sequence is sent.
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This I2C Deblocking mechanism was developed by Keymile in association
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with Anatech and Atmel in 1998.
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*/
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static int i2c_make_abort (void)
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{
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int scl_state = 0;
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int sda_state = 0;
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int i = 0;
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int ret = 0;
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if (!get_sda ()) {
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ret = -1;
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while (i < 16) {
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i++;
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set_scl (0);
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udelay (DELAY_ABORT_SEQ);
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set_scl (1);
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udelay (DELAY_ABORT_SEQ);
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scl_state = get_scl ();
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sda_state = get_sda ();
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if (scl_state && sda_state) {
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ret = 0;
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break;
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}
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}
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}
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if (ret == 0) {
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for (i =0; i < 5; i++) {
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writeStartSeq ();
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}
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}
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get_sda ();
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return ret;
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}
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/**
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* i2c_init_board - reset i2c bus. When the board is powercycled during a
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* bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
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*/
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void i2c_init_board(void)
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{
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#if defined(CONFIG_HARD_I2C)
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volatile immap_t *immap = (immap_t *)CFG_IMMR ;
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volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
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/* disable I2C controller first, otherwhise it thinks we want to */
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/* talk to the slave port... */
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i2c->i2c_i2mod &= ~0x01;
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/* Set the PortPins to GPIO */
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setports (1);
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#endif
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/* Now run the AbortSequence() */
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i2c_make_abort ();
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#if defined(CONFIG_HARD_I2C)
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/* Set the PortPins back to use for I2C */
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setports (0);
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#endif
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}
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#endif
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@ -28,7 +28,7 @@ endif
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o
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COBJS := $(BOARD).o ../common/common.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -28,7 +28,7 @@ endif
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o
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COBJS = $(BOARD).o ../common/common.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -202,6 +202,7 @@
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#define CONFIG_I2C_MULTI_BUS 1
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#define CONFIG_I2C_CMD_TREE 1
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#define CFG_MAX_I2C_BUS 2
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#define CFG_I2C_INIT_BOARD 1
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/* EEprom support */
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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@ -373,6 +373,7 @@
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#define CONFIG_I2C_MULTI_BUS 1
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#define CONFIG_I2C_CMD_TREE 1
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#define CFG_MAX_I2C_BUS 2
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#define CFG_I2C_INIT_BOARD 1
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/* EEprom support */
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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