mirror of
https://github.com/AsahiLinux/u-boot
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85xx: Convert all fsl_pci_init users to new APIs
Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS, MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
This commit is contained in:
parent
a2aab46072
commit
2dba0dea98
16 changed files with 201 additions and 446 deletions
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@ -182,6 +182,9 @@ static struct pci_controller pcie1_hose;
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int first_free_busno=0;
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extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
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extern void fsl_pci_init(struct pci_controller *hose);
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void
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pci_init_board(void)
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{
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@ -211,10 +214,10 @@ pci_init_board(void)
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#ifdef CONFIG_PCIE1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pcie1_hose;
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int pcie_ep = (host_agent == 5);
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int pcie_configured = io_sel & 6;
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struct pci_region *r = hose->regions;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE1 connected to slot as %s (base address %x)",
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@ -227,36 +230,31 @@ pci_init_board(void)
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printf ("\n");
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/* inbound */
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pci_set_region(hose->regions + 0,
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CONFIG_SYS_PCI_MEMORY_BUS,
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CONFIG_SYS_PCI_MEMORY_PHYS,
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CONFIG_SYS_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_MEM_BASE,
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CONFIG_SYS_PCIE1_MEM_PHYS,
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CONFIG_SYS_PCIE1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_IO_BASE,
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CONFIG_SYS_PCIE1_IO_PHYS,
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CONFIG_SYS_PCIE1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
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/* outbound memory */
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pci_set_region(hose->regions + 3,
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_MEM_BASE2,
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CONFIG_SYS_PCIE1_MEM_PHYS2,
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CONFIG_SYS_PCIE1_MEM_SIZE2,
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PCI_REGION_MEM);
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hose->region_count++;
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#endif
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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@ -279,8 +277,8 @@ pci_init_board(void)
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#ifdef CONFIG_PCI1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pci1_hose;
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struct pci_region *r = hose->regions;
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uint pci_agent = (host_agent == 6);
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uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
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@ -300,26 +298,22 @@ pci_init_board(void)
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);
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/* inbound */
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pci_set_region(hose->regions + 0,
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CONFIG_SYS_PCI_MEMORY_BUS,
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CONFIG_SYS_PCI_MEMORY_PHYS,
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CONFIG_SYS_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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pci_set_region(r++,
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CONFIG_SYS_PCI1_MEM_BASE,
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CONFIG_SYS_PCI1_MEM_PHYS,
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CONFIG_SYS_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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pci_set_region(r++,
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CONFIG_SYS_PCI1_IO_BASE,
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CONFIG_SYS_PCI1_IO_PHYS,
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CONFIG_SYS_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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@ -340,26 +334,23 @@ pci_init_board(void)
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pci2_hose;
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struct pci_region *r = hose->regions;
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if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
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pci_set_region(hose->regions + 0,
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CONFIG_SYS_PCI_MEMORY_BUS,
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CONFIG_SYS_PCI_MEMORY_PHYS,
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CONFIG_SYS_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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r += fsl_pci_setup_inbound_windows(r);
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pci_set_region(hose->regions + 1,
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pci_set_region(r++,
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CONFIG_SYS_PCI2_MEM_BASE,
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CONFIG_SYS_PCI2_MEM_PHYS,
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CONFIG_SYS_PCI2_MEM_SIZE,
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PCI_REGION_MEM);
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pci_set_region(hose->regions + 2,
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pci_set_region(r++,
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CONFIG_SYS_PCI2_IO_BASE,
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CONFIG_SYS_PCI2_IO_PHYS,
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CONFIG_SYS_PCI2_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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@ -385,39 +376,21 @@ int last_stage_init(void)
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
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struct pci_controller *hose);
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void
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ft_board_setup(void *blob, bd_t *bd)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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int node, tmp[2];
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const char *path;
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ft_cpu_setup(blob, bd);
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node = fdt_path_offset(blob, "/aliases");
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tmp[0] = 0;
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if (node >= 0) {
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#ifdef CONFIG_PCI1
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path = fdt_getprop(blob, node, "pci0", NULL);
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if (path) {
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tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
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do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
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}
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ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
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#endif
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#ifdef CONFIG_PCI2
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path = fdt_getprop(blob, node, "pci1", NULL);
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if (path) {
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tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
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do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
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}
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ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
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#endif
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#ifdef CONFIG_PCIE1
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path = fdt_getprop(blob, node, "pci2", NULL);
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if (path) {
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tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
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do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
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}
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ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
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#endif
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}
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}
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#endif
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@ -155,6 +155,9 @@ static struct pci_controller pcie2_hose;
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static struct pci_controller pcie3_hose;
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#endif
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extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
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extern void fsl_pci_init(struct pci_controller *hose);
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int first_free_busno=0;
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void
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@ -181,10 +184,10 @@ pci_init_board(void)
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#ifdef CONFIG_PCIE3
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pcie3_hose;
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int pcie_ep = (host_agent == 1);
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int pcie_configured = (io_sel == 7);
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struct pci_region *r = hose->regions;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE3 connected to Slot3 as %s (base address %x)",
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@ -197,27 +200,23 @@ pci_init_board(void)
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printf ("\n");
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/* inbound */
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pci_set_region(hose->regions + 0,
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CONFIG_SYS_PCI_MEMORY_BUS,
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CONFIG_SYS_PCI_MEMORY_PHYS,
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CONFIG_SYS_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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pci_set_region(r++,
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CONFIG_SYS_PCIE3_MEM_BASE,
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CONFIG_SYS_PCIE3_MEM_PHYS,
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CONFIG_SYS_PCIE3_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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pci_set_region(r++,
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CONFIG_SYS_PCIE3_IO_BASE,
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CONFIG_SYS_PCIE3_IO_PHYS,
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CONFIG_SYS_PCIE3_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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@ -239,11 +238,11 @@ pci_init_board(void)
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#ifdef CONFIG_PCIE1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pcie1_hose;
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int pcie_ep = (host_agent == 5);
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int pcie_configured = (io_sel == 2 || io_sel == 3
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|| io_sel == 5 || io_sel == 7);
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struct pci_region *r = hose->regions;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE1 connected to Slot1 as %s (base address %x)",
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@ -256,36 +255,31 @@ pci_init_board(void)
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printf ("\n");
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/* inbound */
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pci_set_region(hose->regions + 0,
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CONFIG_SYS_PCI_MEMORY_BUS,
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CONFIG_SYS_PCI_MEMORY_PHYS,
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CONFIG_SYS_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_MEM_BASE,
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CONFIG_SYS_PCIE1_MEM_PHYS,
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CONFIG_SYS_PCIE1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_IO_BASE,
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CONFIG_SYS_PCIE1_IO_PHYS,
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CONFIG_SYS_PCIE1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
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/* outbound memory */
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pci_set_region(hose->regions + 3,
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_MEM_BASE2,
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CONFIG_SYS_PCIE1_MEM_PHYS2,
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CONFIG_SYS_PCIE1_MEM_SIZE2,
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PCI_REGION_MEM);
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hose->region_count++;
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#endif
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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@ -308,10 +302,10 @@ pci_init_board(void)
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#ifdef CONFIG_PCIE2
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pcie2_hose;
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int pcie_ep = (host_agent == 3);
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int pcie_configured = (io_sel == 5 || io_sel == 7);
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struct pci_region *r = hose->regions;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)",
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@ -324,36 +318,31 @@ pci_init_board(void)
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printf ("\n");
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/* inbound */
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pci_set_region(hose->regions + 0,
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CONFIG_SYS_PCI_MEMORY_BUS,
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CONFIG_SYS_PCI_MEMORY_PHYS,
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CONFIG_SYS_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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pci_set_region(r++,
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CONFIG_SYS_PCIE2_MEM_BASE,
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CONFIG_SYS_PCIE2_MEM_PHYS,
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CONFIG_SYS_PCIE2_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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pci_set_region(r++,
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CONFIG_SYS_PCIE2_IO_BASE,
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CONFIG_SYS_PCIE2_IO_PHYS,
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CONFIG_SYS_PCIE2_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
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/* outbound memory */
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pci_set_region(hose->regions + 3,
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pci_set_region(r++,
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CONFIG_SYS_PCIE2_MEM_BASE2,
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CONFIG_SYS_PCIE2_MEM_PHYS2,
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CONFIG_SYS_PCIE2_MEM_SIZE2,
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PCI_REGION_MEM);
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hose->region_count++;
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#endif
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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@ -375,8 +364,8 @@ pci_init_board(void)
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#ifdef CONFIG_PCI1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pci1_hose;
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struct pci_region *r = hose->regions;
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uint pci_agent = (host_agent == 6);
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uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
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@ -397,35 +386,31 @@ pci_init_board(void)
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);
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/* inbound */
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pci_set_region(hose->regions + 0,
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CONFIG_SYS_PCI_MEMORY_BUS,
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CONFIG_SYS_PCI_MEMORY_PHYS,
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CONFIG_SYS_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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pci_set_region(r++,
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CONFIG_SYS_PCI1_MEM_BASE,
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CONFIG_SYS_PCI1_MEM_PHYS,
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CONFIG_SYS_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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pci_set_region(r++,
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CONFIG_SYS_PCI1_IO_BASE,
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CONFIG_SYS_PCI1_IO_PHYS,
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CONFIG_SYS_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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#ifdef CONFIG_SYS_PCI1_MEM_BASE2
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/* outbound memory */
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pci_set_region(hose->regions + 3,
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pci_set_region(r++,
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CONFIG_SYS_PCI1_MEM_BASE2,
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CONFIG_SYS_PCI1_MEM_PHYS2,
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CONFIG_SYS_PCI1_MEM_SIZE2,
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PCI_REGION_MEM);
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hose->region_count++;
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#endif
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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@ -660,45 +645,24 @@ int board_eth_init(bd_t *bis)
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int node, tmp[2];
|
||||
const char *path;
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
node = fdt_path_offset(blob, "/aliases");
|
||||
tmp[0] = 0;
|
||||
if (node >= 0) {
|
||||
#ifdef CONFIG_PCI1
|
||||
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE2
|
||||
path = fdt_getprop(blob, node, "pci1", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE2
|
||||
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE1
|
||||
path = fdt_getprop(blob, node, "pci2", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE3
|
||||
path = fdt_getprop(blob, node, "pci3", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -103,6 +103,9 @@ static struct pci_controller pcie2_hose;
|
|||
static struct pci_controller pcie3_hose;
|
||||
#endif
|
||||
|
||||
extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
|
||||
int first_free_busno=0;
|
||||
|
||||
void
|
||||
|
@ -126,10 +129,10 @@ pci_init_board(void)
|
|||
#ifdef CONFIG_PCIE3
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie3_hose;
|
||||
int pcie_ep = (host_agent == 1);
|
||||
int pcie_configured = io_sel >= 1;
|
||||
struct pci_region *r = hose->regions;
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
printf ("\n PCIE3 connected to ULI as %s (base address %x)",
|
||||
|
@ -142,36 +145,31 @@ pci_init_board(void)
|
|||
printf ("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE3_MEM_BASE,
|
||||
CONFIG_SYS_PCIE3_MEM_PHYS,
|
||||
CONFIG_SYS_PCIE3_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE3_IO_BASE,
|
||||
CONFIG_SYS_PCIE3_IO_PHYS,
|
||||
CONFIG_SYS_PCIE3_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 3,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE3_MEM_BASE2,
|
||||
CONFIG_SYS_PCIE3_MEM_PHYS2,
|
||||
CONFIG_SYS_PCIE3_MEM_SIZE2,
|
||||
PCI_REGION_MEM);
|
||||
hose->region_count++;
|
||||
#endif
|
||||
hose->region_count = r - hose->regions;
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
||||
|
@ -198,10 +196,10 @@ pci_init_board(void)
|
|||
#ifdef CONFIG_PCIE1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie1_hose;
|
||||
int pcie_ep = (host_agent == 5);
|
||||
int pcie_configured = io_sel & 6;
|
||||
struct pci_region *r = hose->regions;
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
|
||||
|
@ -214,36 +212,31 @@ pci_init_board(void)
|
|||
printf ("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE1_MEM_BASE,
|
||||
CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
CONFIG_SYS_PCIE1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE1_IO_BASE,
|
||||
CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
CONFIG_SYS_PCIE1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 3,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE1_MEM_BASE2,
|
||||
CONFIG_SYS_PCIE1_MEM_PHYS2,
|
||||
CONFIG_SYS_PCIE1_MEM_SIZE2,
|
||||
PCI_REGION_MEM);
|
||||
hose->region_count++;
|
||||
#endif
|
||||
hose->region_count = r - hose->regions;
|
||||
hose->first_busno=first_free_busno;
|
||||
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
@ -266,10 +259,10 @@ pci_init_board(void)
|
|||
#ifdef CONFIG_PCIE2
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie2_hose;
|
||||
int pcie_ep = (host_agent == 3);
|
||||
int pcie_configured = io_sel & 4;
|
||||
struct pci_region *r = hose->regions;
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
|
||||
|
@ -282,36 +275,31 @@ pci_init_board(void)
|
|||
printf ("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE2_MEM_BASE,
|
||||
CONFIG_SYS_PCIE2_MEM_PHYS,
|
||||
CONFIG_SYS_PCIE2_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE2_IO_BASE,
|
||||
CONFIG_SYS_PCIE2_IO_PHYS,
|
||||
CONFIG_SYS_PCIE2_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 3,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE2_MEM_BASE2,
|
||||
CONFIG_SYS_PCIE2_MEM_PHYS2,
|
||||
CONFIG_SYS_PCIE2_MEM_SIZE2,
|
||||
PCI_REGION_MEM);
|
||||
hose->region_count++;
|
||||
#endif
|
||||
hose->region_count = r - hose->regions;
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
||||
|
@ -333,8 +321,8 @@ pci_init_board(void)
|
|||
#ifdef CONFIG_PCI1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pci1_hose;
|
||||
struct pci_region *r = hose->regions;
|
||||
|
||||
uint pci_agent = (host_agent == 6);
|
||||
uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
|
||||
|
@ -355,35 +343,31 @@ pci_init_board(void)
|
|||
);
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCI1_MEM_BASE,
|
||||
CONFIG_SYS_PCI1_MEM_PHYS,
|
||||
CONFIG_SYS_PCI1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCI1_IO_BASE,
|
||||
CONFIG_SYS_PCI1_IO_PHYS,
|
||||
CONFIG_SYS_PCI1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
hose->region_count = 3;
|
||||
|
||||
#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 3,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE3_MEM_BASE2,
|
||||
CONFIG_SYS_PCIE3_MEM_PHYS2,
|
||||
CONFIG_SYS_PCIE3_MEM_SIZE2,
|
||||
PCI_REGION_MEM);
|
||||
hose->region_count++;
|
||||
#endif
|
||||
hose->region_count = r - hose->regions;
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
||||
|
@ -503,46 +487,25 @@ int board_eth_init(bd_t *bis)
|
|||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int node, tmp[2];
|
||||
const char *path;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
node = fdt_path_offset(blob, "/aliases");
|
||||
tmp[0] = 0;
|
||||
if (node >= 0) {
|
||||
|
||||
#ifdef CONFIG_PCI1
|
||||
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE2
|
||||
path = fdt_getprop(blob, node, "pci1", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE1
|
||||
path = fdt_getprop(blob, node, "pci2", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE3
|
||||
path = fdt_getprop(blob, node, "pci3", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -285,6 +285,9 @@ static struct pci_controller pci2_hose;
|
|||
static struct pci_controller pcie1_hose;
|
||||
#endif /* CONFIG_PCIE1 */
|
||||
|
||||
extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
|
||||
int first_free_busno=0;
|
||||
|
||||
void
|
||||
|
@ -298,9 +301,9 @@ pci_init_board(void)
|
|||
#ifdef CONFIG_PCI1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pci1_hose;
|
||||
struct pci_config_table *table;
|
||||
struct pci_region *r = hose->regions;
|
||||
|
||||
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
|
||||
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
|
||||
|
@ -322,27 +325,22 @@ pci_init_board(void)
|
|||
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCI1_MEM_BASE,
|
||||
CONFIG_SYS_PCI1_MEM_PHYS,
|
||||
CONFIG_SYS_PCI1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCI1_IO_BASE,
|
||||
CONFIG_SYS_PCI1_IO_PHYS,
|
||||
CONFIG_SYS_PCI1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
hose->region_count = 3;
|
||||
hose->region_count = r - hose->regions;
|
||||
|
||||
/* relocate config table pointers */
|
||||
hose->config_table = \
|
||||
|
@ -393,9 +391,9 @@ pci_init_board(void)
|
|||
#ifdef CONFIG_PCIE1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie1_hose;
|
||||
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
|
||||
struct pci_region *r = hose->regions;
|
||||
|
||||
int pcie_configured = io_sel >= 1;
|
||||
|
||||
|
@ -411,27 +409,23 @@ pci_init_board(void)
|
|||
printf ("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE1_MEM_BASE,
|
||||
CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
CONFIG_SYS_PCIE1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE1_IO_BASE,
|
||||
CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
CONFIG_SYS_PCIE1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
hose->region_count = r - hose->regions;
|
||||
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
@ -484,29 +478,16 @@ int last_stage_init(void)
|
|||
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int node, tmp[2];
|
||||
const char *path;
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
|
||||
node = fdt_path_offset(blob, "/aliases");
|
||||
tmp[0] = 0;
|
||||
if (node >= 0) {
|
||||
void ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#ifdef CONFIG_PCI1
|
||||
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE1
|
||||
path = fdt_getprop(blob, node, "pci1", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -323,6 +323,9 @@ static struct pci_controller pci1_hose = {
|
|||
static struct pci_controller pcie1_hose;
|
||||
#endif /* CONFIG_PCIE1 */
|
||||
|
||||
extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
|
||||
int first_free_busno = 0;
|
||||
|
||||
/*
|
||||
|
@ -380,8 +383,8 @@ pci_init_board(void)
|
|||
pib_init();
|
||||
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pci1_hose;
|
||||
struct pci_region *r = hose->regions;
|
||||
|
||||
uint pci_32 = 1; /* PORDEVSR[15] */
|
||||
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
|
||||
|
@ -402,27 +405,23 @@ pci_init_board(void)
|
|||
);
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCI1_MEM_BASE,
|
||||
CONFIG_SYS_PCI1_MEM_PHYS,
|
||||
CONFIG_SYS_PCI1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCI1_IO_BASE,
|
||||
CONFIG_SYS_PCI1_IO_PHYS,
|
||||
CONFIG_SYS_PCI1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
hose->region_count = r - hose->regions;
|
||||
|
||||
hose->first_busno = first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
@ -441,9 +440,9 @@ pci_init_board(void)
|
|||
#ifdef CONFIG_PCIE1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie1_hose;
|
||||
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
|
||||
struct pci_region *r = hose->regions;
|
||||
|
||||
int pcie_configured = io_sel >= 1;
|
||||
|
||||
|
@ -459,27 +458,23 @@ pci_init_board(void)
|
|||
printf ("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE1_MEM_BASE,
|
||||
CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
CONFIG_SYS_PCIE1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE1_IO_BASE,
|
||||
CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
CONFIG_SYS_PCIE1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
hose->region_count = r - hose->regions;
|
||||
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
@ -500,31 +495,18 @@ pci_init_board(void)
|
|||
#endif /* CONFIG_PCI */
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int node, tmp[2];
|
||||
const char *path;
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
node = fdt_path_offset(blob, "/aliases");
|
||||
tmp[0] = 0;
|
||||
if (node >= 0) {
|
||||
#ifdef CONFIG_PCI1
|
||||
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE1
|
||||
path = fdt_getprop(blob, node, "pci1", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -147,6 +147,9 @@ static struct pci_controller pcie2_hose;
|
|||
static struct pci_controller pcie3_hose;
|
||||
#endif
|
||||
|
||||
extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
|
||||
int first_free_busno=0;
|
||||
#ifdef CONFIG_PCI
|
||||
void pci_init_board(void)
|
||||
|
@ -172,11 +175,11 @@ void pci_init_board(void)
|
|||
#ifdef CONFIG_PCIE3
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie3_hose;
|
||||
int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
|
||||
(host_agent == 5) || (host_agent == 6);
|
||||
int pcie_configured = io_sel >= 1;
|
||||
struct pci_region *r = hose->regions;
|
||||
u32 temp32;
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
|
@ -190,27 +193,23 @@ void pci_init_board(void)
|
|||
printf ("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE3_MEM_BASE,
|
||||
CONFIG_SYS_PCIE3_MEM_PHYS,
|
||||
CONFIG_SYS_PCIE3_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE3_IO_BASE,
|
||||
CONFIG_SYS_PCIE3_IO_PHYS,
|
||||
CONFIG_SYS_PCIE3_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
hose->region_count = r - hose->regions;
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
||||
|
@ -244,11 +243,11 @@ void pci_init_board(void)
|
|||
#ifdef CONFIG_PCIE2
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie2_hose;
|
||||
int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
|
||||
(host_agent == 6) || (host_agent == 0);
|
||||
int pcie_configured = io_sel & 4;
|
||||
struct pci_region *r = hose->regions;
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
|
||||
|
@ -261,27 +260,23 @@ void pci_init_board(void)
|
|||
printf ("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE2_MEM_BASE,
|
||||
CONFIG_SYS_PCIE2_MEM_PHYS,
|
||||
CONFIG_SYS_PCIE2_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE2_IO_BASE,
|
||||
CONFIG_SYS_PCIE2_IO_PHYS,
|
||||
CONFIG_SYS_PCIE2_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
hose->region_count = r - hose->regions;
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
||||
|
@ -301,11 +296,11 @@ void pci_init_board(void)
|
|||
#ifdef CONFIG_PCIE1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie1_hose;
|
||||
int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
|
||||
(host_agent == 5);
|
||||
int pcie_configured = io_sel & 6;
|
||||
struct pci_region *r = hose->regions;
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
|
||||
|
@ -318,27 +313,23 @@ void pci_init_board(void)
|
|||
printf ("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE1_MEM_BASE,
|
||||
CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
CONFIG_SYS_PCIE1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE1_IO_BASE,
|
||||
CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
CONFIG_SYS_PCIE1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
hose->region_count = r - hose->regions;
|
||||
hose->first_busno=first_free_busno;
|
||||
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
@ -568,10 +559,11 @@ int board_eth_init(bd_t *bis)
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int node, tmp[2];
|
||||
const char *path;
|
||||
ulong base, size;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
@ -581,31 +573,15 @@ void ft_board_setup(void *blob, bd_t *bd)
|
|||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size);
|
||||
|
||||
node = fdt_path_offset(blob, "/aliases");
|
||||
tmp[0] = 0;
|
||||
if (node >= 0) {
|
||||
#ifdef CONFIG_PCIE3
|
||||
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE2
|
||||
path = fdt_getprop(blob, node, "pci1", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE1
|
||||
path = fdt_getprop(blob, node, "pci2", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
@ -364,6 +364,9 @@ static struct pci_controller pcie1_hose;
|
|||
|
||||
int first_free_busno=0;
|
||||
|
||||
extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
|
||||
void
|
||||
pci_init_board(void)
|
||||
{
|
||||
|
@ -372,9 +375,9 @@ pci_init_board(void)
|
|||
#ifdef CONFIG_PCI1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pci1_hose;
|
||||
struct pci_config_table *table;
|
||||
struct pci_region *r = hose->regions;
|
||||
|
||||
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
|
||||
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
|
||||
|
@ -396,27 +399,22 @@ pci_init_board(void)
|
|||
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCI1_MEM_BASE,
|
||||
CONFIG_SYS_PCI1_MEM_PHYS,
|
||||
CONFIG_SYS_PCI1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCI1_IO_BASE,
|
||||
CONFIG_SYS_PCI1_IO_PHYS,
|
||||
CONFIG_SYS_PCI1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
hose->region_count = 3;
|
||||
hose->region_count = r - hose->regions;
|
||||
|
||||
/* relocate config table pointers */
|
||||
hose->config_table = \
|
||||
|
@ -467,9 +465,9 @@ pci_init_board(void)
|
|||
#ifdef CONFIG_PCIE1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie1_hose;
|
||||
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
|
||||
struct pci_region *r = hose->regions;
|
||||
|
||||
int pcie_configured = io_sel >= 1;
|
||||
|
||||
|
@ -485,27 +483,27 @@ pci_init_board(void)
|
|||
printf ("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE1_MEM_BASE,
|
||||
CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
CONFIG_SYS_PCIE1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE1_IO_BASE,
|
||||
CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
CONFIG_SYS_PCIE1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
hose->region_count = r - hose->regions;
|
||||
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
@ -531,41 +529,17 @@ int last_stage_init(void)
|
|||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int node, tmp[2];
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
|
||||
node = fdt_path_offset(blob, "/aliases");
|
||||
tmp[0] = 0;
|
||||
if (node >= 0) {
|
||||
#ifdef CONFIG_PCI1
|
||||
const char *path;
|
||||
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE1
|
||||
const char *path;
|
||||
path = fdt_getprop(blob, node, "pci1", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#ifdef CONFIG_PCI1
|
||||
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE1
|
||||
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -538,6 +538,9 @@ void local_bus_init (void)
|
|||
*/
|
||||
static int first_free_busno;
|
||||
|
||||
extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
|
||||
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
|
||||
static struct pci_controller pci1_hose;
|
||||
#endif /* CONFIG_PCI || CONFIG_PCI1 */
|
||||
|
@ -552,8 +555,8 @@ static inline void init_pci1(void)
|
|||
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
|
||||
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pci1_hose;
|
||||
struct pci_region *r = hose->regions;
|
||||
|
||||
/* PORDEVSR[15] */
|
||||
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
|
||||
|
@ -578,28 +581,23 @@ static inline void init_pci1(void)
|
|||
|
||||
|
||||
/* inbound */
|
||||
pci_set_region (hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region (hose->regions + 1,
|
||||
pci_set_region (r++,
|
||||
CONFIG_SYS_PCI1_MEM_BASE,
|
||||
CONFIG_SYS_PCI1_MEM_PHYS,
|
||||
CONFIG_SYS_PCI1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region (hose->regions + 2,
|
||||
pci_set_region (r++,
|
||||
CONFIG_SYS_PCI1_IO_BASE,
|
||||
CONFIG_SYS_PCI1_IO_PHYS,
|
||||
CONFIG_SYS_PCI1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
hose->region_count = r - hose->regions;
|
||||
|
||||
hose->first_busno = first_free_busno;
|
||||
pci_setup_indirect (hose, (int)&pci->cfg_addr,
|
||||
|
@ -641,10 +639,10 @@ static inline void init_pcie1(void)
|
|||
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
|
||||
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie1_hose;
|
||||
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) ||
|
||||
(host_agent == 3);
|
||||
struct pci_region *r = hose->regions;
|
||||
|
||||
int pcie_configured = io_sel >= 1;
|
||||
|
||||
|
@ -660,27 +658,23 @@ static inline void init_pcie1(void)
|
|||
puts ("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region (hose->regions + 0,
|
||||
CONFIG_SYS_PCI_MEMORY_BUS,
|
||||
CONFIG_SYS_PCI_MEMORY_PHYS,
|
||||
CONFIG_SYS_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region (hose->regions + 1,
|
||||
pci_set_region (r++,
|
||||
CONFIG_SYS_PCIE1_MEM_BASE,
|
||||
CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
CONFIG_SYS_PCIE1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region (hose->regions + 2,
|
||||
pci_set_region (r++,
|
||||
CONFIG_SYS_PCIE1_IO_BASE,
|
||||
CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
CONFIG_SYS_PCIE1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
hose->region_count = r - hose->regions;
|
||||
|
||||
hose->first_busno = first_free_busno;
|
||||
pci_setup_indirect(hose, (int)&pci->cfg_addr,
|
||||
|
@ -707,31 +701,19 @@ void pci_init_board (void)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
|
||||
void ft_board_setup (void *blob, bd_t *bd)
|
||||
{
|
||||
int node, tmp[2];
|
||||
const char *path;
|
||||
|
||||
ft_cpu_setup (blob, bd);
|
||||
|
||||
node = fdt_path_offset (blob, "/aliases");
|
||||
tmp[0] = 0;
|
||||
if (node >= 0) {
|
||||
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
|
||||
path = fdt_getprop (blob, node, "pci0", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
||||
do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
#endif /* CONFIG_PCI || CONFIG_PCI1 */
|
||||
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE1
|
||||
path = fdt_getprop (blob, node, "pci1", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
||||
do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
#endif /* CONFIG_PCIE1 */
|
||||
}
|
||||
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_OF_BOARD_SETUP */
|
||||
|
||||
|
|
|
@ -287,11 +287,6 @@
|
|||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
|
||||
/* PCI view of System Memory */
|
||||
#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
|
|
@ -307,11 +307,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
|||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
|
||||
/* PCI view of System Memory */
|
||||
#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
|
||||
|
||||
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
|
||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
|
||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
|
||||
|
|
|
@ -276,11 +276,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
|||
#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
|
||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* PCI view of System Memory */
|
||||
#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
|
||||
|
||||
/* controller 2, Slot 1, tgtid 1, Base address 9000 */
|
||||
#define CONFIG_SYS_PCIE2_MEM_BASE 0x80000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
|
||||
|
|
|
@ -420,11 +420,6 @@ extern unsigned long get_clock_freq(void);
|
|||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
|
||||
/* PCI view of System Memory */
|
||||
#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
|
||||
|
|
|
@ -389,11 +389,6 @@ extern unsigned long get_clock_freq(void);
|
|||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
/* PCI view of System Memory */
|
||||
#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
|
|
|
@ -326,11 +326,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
|||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
|
||||
/* PCI view of System Memory */
|
||||
#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
|
||||
|
||||
/* controller 3, direct to uli, tgtid 3, Base address 8000 */
|
||||
#define CONFIG_SYS_PCIE3_MEM_BASE 0x80000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE
|
||||
|
|
|
@ -403,11 +403,6 @@
|
|||
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
|
||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
|
||||
/* PCI view of System Memory */
|
||||
#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
/*
|
||||
* General PCI express
|
||||
|
|
|
@ -387,11 +387,6 @@
|
|||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
|
||||
/* PCI view of System Memory */
|
||||
#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
|
||||
#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
|
||||
|
|
Loading…
Reference in a new issue