Commit graph

24163 commits

Author SHA1 Message Date
Marek Vasut
dec699bea7 ARM: rmobile: Factor out SYS_SOC Kconfig option
Pull the SYS_SOC Kconfig option to avoid duplication of this option
in Kconfig.{32,64,rza1} . The default value is the same, so just set
it in one location.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18 12:02:38 +01:00
Marek Vasut
6f152a713c ARM: rmobile: Sort R-Car Gen3 Kconfig lists
Sort the 'imply' and 'select' lists in R-Car Gen3 Kconfig options.
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18 12:02:38 +01:00
Marek Vasut
7fe9d7d1ba ARM: rmobile: Convert ifdef in rmobile_get_prr() to IS_ENABLED()
Switch ifdef in rmobile_get_prr() to IS_ENABLED() macro.
The CONFIG_RCAR_GEN3 will never have SPL counterpart, so
the IS_ENABLED() macro is the right one here. No functional
change, except for improved build test coverage.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18 12:02:38 +01:00
Marek Vasut
143bd4e315 ARM: renesas: Enable DTO support by default on R-Car Gen3
All R-Car Gen3 defconfigs present in U-Boot do enable DTO support,
enable it for all of R-Car Gen3 by default in Kconfig instead, so
that no new boards would miss this functionality.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18 11:59:45 +01:00
Tom Rini
cefd0449d6 Xilinx changes for v2023.07-rc1
cmd:
 - Print results in hex instead of dec in smc command
 
 firmware:
 - Cover missing ZYNQMP_FIRMWARE dependencies
 
 fpga:
 - fix loads for unencrypted use case
 
 relocation
 - Add support for BE systems
 
 spi:
 - Fix xilinx_spi init reset sequence
 
 arasan nand:
 - Remove hardcoded bbt option
 - Set ofnode value
 
 xilinx:
 - Enable SMC command
 - Fix some sparse issues
 
 zynqmp:
 - Remove cdns,zynq-gem compatible string
 - Add optee node
 - Some DT cleanups
 
 zynq:
 - Some DT cleanups
 
 microblaze
 - Remove MANUAL_RELOC option
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Merge tag 'xilinx-for-v2023.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2023.07-rc1

cmd:
- Print results in hex instead of dec in smc command

firmware:
- Cover missing ZYNQMP_FIRMWARE dependencies

fpga:
- fix loads for unencrypted use case

relocation
- Add support for BE systems

spi:
- Fix xilinx_spi init reset sequence

arasan nand:
- Remove hardcoded bbt option
- Set ofnode value

xilinx:
- Enable SMC command
- Fix some sparse issues

zynqmp:
- Remove cdns,zynq-gem compatible string
- Add optee node
- Some DT cleanups

zynq:
- Some DT cleanups

microblaze
- Remove MANUAL_RELOC option
2023-03-16 12:18:30 -04:00
Tom Rini
e63828bf35 Merge tag 'fsl-qoriq-next-2023-3-14' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next
Enable DM_SERIAL for freescale ls2080a
Drop non DM_ETH code for freescale:
  lx2160a/ls2080rdb/ls2080aqds/ls1088a
2023-03-16 12:17:48 -04:00
Tom Rini
318af47668 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-coldfire 2023-03-15 12:03:17 -04:00
Tom Rini
016d414682 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
Per Andre:

[T]hese two patches containing just devicetree updates for
Allwinner boards.
I was still hoping for a review, since we cannot import the files from
the Linux tree verbatim, but managed to write some filter script that
convinced me that the changes are fine.
The files are from Linux v6.2-rc2, but are identical to the v6.2
release.
2023-03-15 12:01:55 -04:00
Angelo Dureghello
ec4322e70b m68k: add private libgcc ashrdi3
Add ashrdi3.c to private libgcc.

Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
2023-03-15 01:52:02 +01:00
Angelo Dureghello
7ff7b46e6c m68k: rename CONFIG_MCFTMR to CFG_MCFTMR
This is not a Kconfig option so changing to _CFG.

Signed-off-by: Angelo Durgehello <angelo@kernel-space.org>
2023-03-15 01:41:57 +01:00
Angelo Dureghello
12f5489297 m68k: dts: stmark2: set correct compatible field for spi nor
Fix error:

Invalid chip select 0:1 (err=-19)

update spi nor "compatible" property with "jedec,spi-nor"
to have spi nor properly bound as a child device.

Signed-off-by: Angelo Durgehello <angelo@kernel-space.org>
2023-03-15 01:38:19 +01:00
Angelo Dureghello
1e48392e32 arch: enable private libgcc for m68k
This patch fixes u-boot hanging on the first printf("%x", val).

Some toolchains built without multilib enabled may produce
u-boot freezing on first u64 shift operation, as in
lib/vsprintf.c number() function.
Using our private libgcc solves the issue.

Setting private libgcc enabled at architecture level to avoid
similar issues, it should not harm.

Signed-off-by: Angelo Durgehello <angelo@kernel-space.org>
2023-03-15 01:38:19 +01:00
Angelo Dureghello
8fde9d13b9 m68k: add global variable sdhc_per_clk for m68k
The FSL eSDHC controller supports two reference clocks. They are
platform clock and periperhal clock. The global variable sdhc_clk
has already been used for platform clock.
ColdFire also uses eSHDC controller, as in arm and powerpc,
so adding sdhc_per_clk to arch_global_data.

Signed-off-by: Angelo Durgehello <angelo@kernel-space.org>
2023-03-15 01:38:19 +01:00
Angelo Dureghello
d157a5725a m68k: use longword-based jumps
Increasing of binary size requires longword-based jumps.

Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
2023-03-15 01:38:19 +01:00
Tom Rini
a5faa4a9eb Prepare v2023.04-rc4
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Merge tag 'v2023.04-rc4' into next

Prepare v2023.04-rc4

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-14 12:06:35 -04:00
Ioana Ciornei
5a2416fd99 arch: arm: dst: fsl-ls2080a.dts: tag serial nodes with bootph-all
Tag the serial nodes with bootph-all in order to have these nodes and
the drivers available before relocation.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-14 18:56:28 +08:00
Ioana Ciornei
1d37e4a18b arch: arm: dst: fsl-ls2080a.dts: sync serial nodes with Linux
Sync the serial nodes of the LS208XA RDB/QDS boards with their
representation in Linux. We also imported the clockgen and sysclk nodes
which are dependencies.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-14 18:56:28 +08:00
Ioana Ciornei
853c3124cd arch: arm: dst: fsl-ls2080a.dtsi: move the serial nodes under soc
Move the serial nodes under the soc node. No changes are made to the
nodes, just their location is changed.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-14 18:56:28 +08:00
Ioana Ciornei
c445af6d23 arch: arm: dst: fsl-ls2080a.dtsi: add an 'soc' node
The u-boot dts for these boards do not have an soc node, unlike its
Linux counterpart. This patch just adds the soc node as seen in Linux,
the next patches will move some nodes under it.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-14 18:56:28 +08:00
Ioana Ciornei
73ba0371a1 arm: dts: ls1088a-rdb: replace 'xgmii' with '10gbase-r'
When the first device tree description was added for the ethernet nodes,
the 2 10G ports on the LS1088ARDB were wrongly described as 'xgmii'.

Fix this by replacing the two last occurrences of 'xgmii' in the device
trees of the Layerscape DPAA2 devices.

Fixes: 68c7c008e8 ("arm: dts: ls1088ardb: add DPMAC and PHY nodes")
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-14 18:56:27 +08:00
Neil Armstrong
de58694f0d ARM: meson: odroid-go-ultra: setup PMIC regulators are board init
The Odroid Go Ultra has 2 chained PMICs RK818 and RK818, and needs
an adjustment on the BUCK and LDO values.

Add the initial regulators values in -u-boot.dtsi & run the initial
regulator setup in a new odroid-go-ultra board.

Proper OTG and BOOST regulators are still missing to have USB-A
host properly working.

Link: https://lore.kernel.org/r/20230210-u-boot-odroid-go-ultra-pmics-setup-v1-1-1f16d62b76af@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-03-14 09:03:16 +01:00
Simon Glass
f62229227c efi: Support copy framebuffer
Add support for this to EFI in case it becomes useful. At present it just
slows things down. You can enable CONFIG_VIDEO_COPY to turn it on.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13 13:53:01 +01:00
Simon Glass
40b8afe6f6 x86: Add a few more items to bdinfo
Add the timer and vendor/model information.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13 13:53:01 +01:00
Simon Glass
644e61448c efi: Support a 64-bit frame buffer address
The current vesa structure only provides a 32-bit value for the frame
buffer. Many modern machines use an address outside the range.

It is still useful to have this common struct, but add a separate
frame-buffer address as well.

Add a comment for vesa_setup_video_priv() while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13 13:53:01 +01:00
Ovidiu Panait
7ac50f88f8 microblaze: drop remnants of manual reloc
Runtime relocation has been made the default for microblaze, so do the
following cleanups:
- drop all manual reloc codepaths in start.S
- drop all STATIC_RELA ifdefs, as it is now enabled unconditionally in
Kconfig

Reviewed-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20230311173838.521804-5-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-13 11:46:17 +01:00
Ovidiu Panait
3363cf96eb microblaze: drop CONFIG_NEEDS_MANUAL_RELOC
Microblaze and m68k are the only remaining architectures that still enable
CONFIG_NEEDS_MANUAL_RELOC by default.

Microblaze has had runtime relocation support using CONFIG_STATIC_RELA for
quite some time, since commit d58c007498 ("microblaze: Add support for run
time relocation"). Drop support for CONFIG_NEEDS_MANUAL_RELOC and make
runtime relocation the default, as the rest of the architectures do.

Reviewed-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20230311173838.521804-4-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-13 11:46:17 +01:00
Tam Nguyen
ae08097faa ARM: dts: renesas: Enable sysinfo on R-Car D3 Draak
Enable support for sysinfo on R-Car D3 Draak board. The sysinfo is used
e.g. to access and decode board-specific information and then in turn
used by board-info to print those information.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Drop compatible from I2C node, this is in r8a77995.dtsi already.
        Drop status = "okay" from EEPROM node.
	Add dts: tag.
	Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.]
2023-03-10 17:46:09 +01:00
Tam Nguyen
c8eaebb426 ARM: dts: renesas: Enable sysinfo on R-Car V3H Condor/Condor-I
Add new sysinfo IDs for R-Car V3H Condor/Condor-I .

Enable support for sysinfo on R-Car V3H Condor/Condor-I. The sysinfo is
used e.g. to access and decode board-specific information and then in
turn used by board-info to print those information.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Drop compatible from I2C node, this is in r8a77980.dtsi already.
        Drop status = "okay" from EEPROM node.
	Add dts: tag.
	Update the commit message, note the new sysinfo IDs.
	Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.]
2023-03-10 17:46:09 +01:00
Algapally Santosh Sagar
cc24fd7859 xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write
Add missing prototype to fix the sparse warning, warning: no
previous prototype for 'zynqmp_mmio_write' [-Wmissing-prototypes].

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230301103334.1455-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Ashok Reddy Soma
9b669ef059 arm64: dts: zynqmp: Enable nand-on-flash-bbt in DT by default
By default enable nand-on-flash-bbt DT flag, so that driver always refers
to the bad block table(bbt) present on the flash device.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230224050709.30014-5-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Ashok Reddy Soma
9207c48491 arm64: dts: zynqmp: Fix nand dt node
DC3 nand node is not correct, it is showing all partitions under
controller node directly. Create two sub nand nodes with partitions for
each.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230224050709.30014-4-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Michal Simek
dd0ebfe8a4 arm64: zynqmp: Remove comment about gem spec in kv260
The latest SOM specification doesn't enforce certain MIO lines allocated
for ethernet or ethernet controller itself. That's why remove comment about
it which is likely there from early version of specification.
Also removed the same comment from pinctrl node. It is clear that it has to
be defined for different carrier cards.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9406377bf2c391ac0200670511bd6b0edb097c96.1676880543.git.michal.simek@amd.com
2023-03-09 13:15:00 +01:00
Ilias Apalodimas
89f0f14fe2 arm64: zynqmp: Add an OP-TEE node to the device tree
Since the zynqmp boards can run upstream OP-TEE, and having the DT node
present doesn't cause any side effects add it in case someone tries to
load OP-TEE.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Link: https://lore.kernel.org/r/20230216133921.866786-1-ilias.apalodimas@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Michal Simek
cfa39857de ARM: zynq: Comment interrupt names IRQs for pl330
pl330 DT yaml description doesn't define interrupt-names property that's
why comment it but keep it as comment.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8e5a921c16efe09030fda036340186c11dd990bf.1672908030.git.michal.simek@amd.com
2023-03-09 13:15:00 +01:00
Krzysztof Kozlowski
89c3a5151c ARM: dts: zynq-7000: drop useless 'dma-channels/requests' properties
The pl330 DMA controller provides number of DMA channels and requests
through its registers, so duplicating this information (with a chance of
mistakes) in DTS is pointless.  Additionally the DTS used always wrong
property names which causes DT schema check failures - the bindings
documented 'dma-channels' and 'dma-requests' properties without leading
hash sign.

Reported-by: Rob Herring <robh@kernel.org>
Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20220430121902.59895-2-krzysztof.kozlowski@linaro.org
2023-03-09 13:15:00 +01:00
Krzysztof Kozlowski
4837ff416d ARM: dts: xilinx: align gpio-key node names with dtschema
The node names should be generic and DT schema expects certain pattern
(e.g. with key/button/switch).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220616005333.18491-31-krzysztof.kozlowski@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Michal Simek
5331845db4 ARM: zynq: Use recommended dma-controller name instead of dmac
Use standard name for dma controller. Issue is reported by dtbs_check as
dmac@f8003000: $nodename:0: 'dmac@f8003000' does not match
'^dma-controller(@.*)?$'

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5637d7e3464fbc1b2b269a7df35e24edc2c8d4ac.1672908080.git.michal.simek@amd.com
2023-03-09 13:15:00 +01:00
Michael Grzeschik
06ba3c252f arm64: zynqmp: Enable hs termination flag for USB dwc3 controller
Since we need to support legacy phys with the dwc3 controller,
we enable this quirk on the zynqmp platforms.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Link: https://lore.kernel.org/r/20221023215649.221726-1-m.grzeschik@pengutronix.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Krzysztof Kozlowski
b4b2f7bb5f arm64: dts: xilinx: align LED node names with dtschema
The node names should be generic and DT schema expects certain pattern:

  xilinx/zynqmp-zcu100-revC.dtb: leds: 'vbus-det' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221125144136.477171-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:15:00 +01:00
Michal Simek
a09d9278a5 xilinx: dts: Remove cdns,zynq-gem
cdns prefix was deprecated and replaced by xlnx one in upstream Linux. Also
U-Boot driver has been updated to support new compatible string that's why
it is time to remove it and deprecate it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09 13:14:59 +01:00
Andre Przywara
7400d34ba9 riscv: semihosting: replace inline assembly with assembly file
So far we used inline assembly to inject the actual instruction that
triggers the semihosting service. While this sounds elegant, as it's
really only about a few instructions, it has some serious downsides:
- We need some barriers in place to force the compiler to issue writes
  to a data structure before issuing the trap instruction.
- We need to convince the compiler to actually fill the structures that
  we use pointers to.
- We need a memory clobber to avoid the compiler caching the data in
  those structures, when semihosting writes data back.
- We need register arguments to make sure the function ID and the
  pointer land in the right registers.

This is all doable, but fragile and somewhat cumbersome. Since we now
have a separate function in an extra file anyway, we can do away with
all the magic and just write that in an actual assembler.
This is much more readable and robust.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2023-03-06 19:24:34 -05:00
Andre Przywara
29c579a249 arm: semihosting: replace inline assembly with assembly file
So far we used inline assembly to inject the actual instruction that
triggers the semihosting service. While this sounds elegant, as it's
really only about one instruction, it has some serious downsides:
- We need some barriers in place to force the compiler to issue writes
  to a data structure before issuing the trap instruction.
- We need to convince the compiler to actually fill the structures that
  we use pointers to.
- We need a memory clobber to avoid the compiler caching the data in
  those structures, when semihosting writes data back.
- We need register arguments to make sure the function ID and the
  pointer land in the right registers.

This is all doable, but fragile and somewhat cumbersome. Since we now
have a separate function in an extra file anyway, we can do away with
all the magic and just write that in an actual assembly file.
This is much more readable and robust.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2023-03-06 17:06:17 -05:00
Devarsh Thakkar
885198536d am62a7: dts: Enable full 4GB LPDDR4
AM62A7-SK board has 4GB LPDDR4 Micron MT53E2G32D4DE-046 AUT:B part
but only 2GB was enabled early.

Enable full 4GB memory by updating the latter 2GB memory region
which gets mapped to 0x0880000000 i.e. DDR16SS0_SDRAM as referred in
Table 2-1. AM62A Common SoC Memory of AM62Ax TRM [1].

[1] : https://www.ti.com/lit/zip/spruj16
Logs: https://gist.github.com/devarsht/e85b6af89c01ddadb3a62f3e5f196af8

Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
2023-03-06 17:06:17 -05:00
Kunihiko Hayashi
051451ad83 ARM: dts: uniphier: Sync DT with Linux v6.2
Synchronize devicetree sources with Linux v6.2.

- Use GIC interrupt definitions
- Add reg properties in USB-glue and SoC-glue node
- Fix node names to follow the generic names list in DT specification
- Add L2 cache and AHCI nodes
- Update nand and pcie nodes
- And some trivial fixes

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Marek Vasut <marex@denx.de>
2023-03-06 17:05:40 -05:00
Kunihiko Hayashi
e800263d56 ARM: dts: uniphier: Switch USB node to the original
UniPhier DT applies its own USB node for U-Boot due to the USB driver
constrains. After solving this issue, u-boot allows the original USB node.

After switching USB node, synchronization of USB node with Linux becomes
possible.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Marek Vasut <marex@denx.de>
2023-03-06 17:05:40 -05:00
Christophe Leroy
6782b81588 powerpc, mpc83xx: Remove CONFIG_ELBC_BRx_ORx
Commit fe7d654d04 ("mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to
Kconfig") converted CONFIG_SYS_{BRx/ORx}_PRELIM to Kconfig by
implementing a fine-grained selection of every bit in Kconfig.

But commit c7fad78ec0 ("Convert CONFIG_SYS_BR0_PRELIM et al to
Kconfig") reworked it so that you now just have to provide the raw
value of each register in Kconfig. However, all fine-grained
Kconfig items remained allthough they are not used anymore.

Remove them all.

Fixes: c7fad78ec0 ("Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-03-06 17:05:40 -05:00
Patrick Delaunay
c6c2fe9936 ARM: remove SPEAR entry in makefile
As the lastest spear directories are removed, delete the associated entry
in Makefile.

Fixes: 570c3dcfc1 ("arm: Remove spear600 boards and the rest of SPEAr support")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-03-06 17:03:56 -05:00
Marc Zyngier
94d30f476f arm64: Reduce PT size estimation complexity
count_required_pts()'s complexity is high if mappings are not using the
largest possible block size (due to some other requirement such as tracking
dirty pages, for example).

Let's switch to a method that follows the pattern established with
the add_map() helper, and make it almost instantaneous instead of
taking a large amount of time if 2MB mappings are in use instead of
1GB.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
[ Paul: pick from the Android tree. Fixup Pierre's commit. Rebase to the
  upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: 5d756d147e
Link: 6be9330601
2023-03-06 17:03:56 -05:00
Marc Zyngier
41e2787f5e arm64: Reduce add_map() complexity
In the add_map() function, for each level it populates, it iterates from
the root of the PT tree, making it ineficient if a mapping needs to occur
past level 1.

Instead, replace it with a recursive (and much simpler) algorithm
that keeps the complexity as low as possible. With this, mapping
512GB at level 2 goes from several seconds down to not measurable
on an A55 machine.

We keep the block mappings at level 1 for now though.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
[ Paul: pick from the Android tree. Fixup Pierre's commit. Rebase to the
  upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: 96ad729cf4
Link: 6be9330601
2023-03-06 17:03:56 -05:00
Pierre-Clément Tosi
c55c2a8565 arm64: Initialize TLB memory if CMO_BY_VA_ONLY
Memory used to hold the page tables is allocated from the top of RAM
with no prior initialization and could therefore hold invalid data. As
invalidate_dcache_all() will be called before the MMU has been
initialized and as that function relies indirectly on the page tables
when using CMO_BY_VA_ONLY, these must be in a valid state from their
allocation.

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
[ Paul: pick from the Android tree. Fix checkpatch warnings, and rebased
  to the upstream. ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: e3ceef4230
2023-03-06 17:03:55 -05:00
Marc Zyngier
46dc542870 arm: cpu: Add optional CMOs by VA
Exposing set/way cache maintenance to a virtual machine is unsafe, not
least because the instructions are not permission-checked but also
because they are not broadcast between CPUs. Consequently, KVM traps and
emulates such maintenance in the host kernel using by-VA operations and
looping over the stage-2 page-tables. However, when running under
protected KVM, these instructions are not able to be emulated and will
instead result in an exception being delivered to the guest.

Introduce CONFIG_CMO_BY_VA_ONLY so that virtual platforms can select
this option and perform by-VA cache maintenance instead of using the
set/way instructions.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Will Deacon <willdeacon@google.com>
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
[ Paul: pick from the Android tree. Fixup Pierre's commit. And fix some
  checkpatch warnings. Rebased to upstream. ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: db5507f47f
Link: 2baf54e743
2023-03-06 17:03:55 -05:00
Andre Przywara
8e2c0ee3ba sunxi: dts: arm64: update devicetree files from Linux v6.2-rc2
Sync the devicetree files from the Linux kernel repo, v6.2-rc2.
This is covering the 64-bit SoCs, from arch/arm64/boot/dts/allwinner.

This enables GPU power management in the kernel for the H6, enables
Bluetooth on the Pinebook, and adds USB to the H616 devices (just
for newer Linux kernels at the moment, U-Boot support is pending).

As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-03-05 23:33:14 +00:00
Andre Przywara
6621cc85f7 sunxi: dts: arm: update devicetree files from Linux v6.2-rc2
Sync the devicetree files from the Linux kernel repo, v6.2-rc2.
This is covering the 32-bit SoCs, from arch/arm/boot/dts.

This enables some new devices for the F1C100s family, though this is of
little relevance to U-Boot itself.
The H3 gains the "phys" property for the first USB controller, which
prevents an error message when U-Boot's USB stack comes up, and allows
using this port in host mode.

As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-03-05 23:33:13 +00:00
Simon Glass
06a1edda6c freescale: Drop old pre-DM_ETH code
This is used by ls1021atwr_sdcard_ifc_SECURE_BOOT with split config, but
is not needed anymore, since Ethernet migration is complete. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-03 09:49:02 -05:00
Simon Glass
9ee2f35628 sandbox: Use the generic VPL option to enable VPL
Avoid using CONFIG_SANDBOX_VPL since we have a generic option which works
just as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-02 17:45:58 -05:00
Simon Glass
dd8a29040d sandbox: Tidy up RTC options
At present we enable the sandbox RTC driver for all builds. Add a separate
Kconfig option to control this, so that it can be disabled in TPL, where
it is not needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-02 17:45:58 -05:00
Simon Glass
85c66dc95c sandbox: Expand size for VPL image
Allow this to get larger to accommodate more test code with LTO disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-02 17:45:58 -05:00
Tom Rini
f4ee45e2a0 s5p: Remove empty arch_misc_init
We don't need to provide an empty arch_misc_init function here, we can
just not enable the hook.

Cc: Stefan Bosch <stefan_b@posteo.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2023-03-02 15:32:25 -05:00
Tom Rini
1df23b405a mvebu: Drop empty arch_misc_init
If this hooks is needed later, it should be added and populated for
real.

Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-02 15:32:25 -05:00
Tom Rini
f47c765dbe mvebe: Drop ARCH_MISC_INIT from alleycat 5
In this platform, arch_misc_init doesn't perform any real function. The
call to get_soc_type_rev has no lasting side effects.

Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2023-03-02 15:32:25 -05:00
Tom Rini
cfc4c0c2f3 imx9: Remove ARCH_MISC_INIT
We don't need an empty function, we can just not enable the hook we
don't use.

Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-02 15:32:25 -05:00
Tom Rini
4c7df3b184 arm: rk3368: Select ARCH_EARLY_INIT_R when used
On the lion and evb-px5 platforms, we need this function, so select it.

Cc: Andy Yan <andy.yan@rock-chips.com>
Cc: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Cc: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-03-02 15:32:25 -05:00
Tom Rini
d0bfa29cdc arm: zynq: Move to select'ing ARCH_EARLY_INIT_R if we have FPGA
The function arch_early_init_r only does anything on these platforms if
we have FPGA (or SPL and SPL_FPGA) enabled, so move the logic to select
based on that.

Cc: Michal Simek <michal.simek@amd.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-02 15:32:25 -05:00
Tom Rini
efb0aa7bf5 arm: mvebu: Add select on ARCH_EARLY_INIT_R if ARM64
We need to be calling arch_early_init_r() on 64bit mvebu platforms, so
move this to a select.

Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-02 15:32:25 -05:00
Michal Suchanek
3cbaa4e1ef sandbox: Correctly define BITS_PER_LONG
SANDBOX_BITS_PER_LONG is the number of bits in long on the sandbox
platform.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
2023-03-01 11:22:27 -07:00
Tom Rini
b0eda49bc9 First set of u-boot-at91 fixes for the 2023.04 cycle
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Merge tag 'u-boot-at91-fixes-2023.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91

First set of u-boot-at91 fixes for the 2023.04 cycle:

This fixes set include one clock index fix for sama7g5 and two board
configuration alignments for pm9g45.
2023-03-01 09:39:18 -05:00
Pali Rohár
e00008939f arm: mvebu: Define SPL memory maps
In SPL are active memory maps set by the BootROM. Define them in cpu.h file
to the correct values. Some peripherals are not mapped at all.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:18 +01:00
Pali Rohár
056808a4bb arm: mvebu: Define env_sf_get_env_addr() also for Proper U-Boot
Proper U-Boot moves SPI0 CS0 Flash mapping from 0xD4000000 to 0xF4000000
and change its size from 64 MB to 8 MB. Definitions are already in
MBUS_SPI_BASE/MBUS_SPI_SIZE macros. So define these macros also for SPL
build, use them in env_sf_get_env_addr() function and move this function
from spl.c to cpu.c to be available in Proper U-Boot too.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:18 +01:00
Pali Rohár
7c406797cb arm: mvebu: Fix comment about CPU_ATTR_BOOTROM mapping
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:18 +01:00
Pali Rohár
117481d27a arm: mvebu: Remove A39x relicts
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:18 +01:00
Pali Rohár
41d52f3bd0 arm: mvebu: Fix description of MVEBU_SPL_BOOT_DEVICE_(SPI|MMC) options
MVEBU_SPL_BOOT_DEVICE_SPI is for NOR flash. Either serial or parallel. Not
for general serial/SPI devices. The correct name should be BOOT_DEVICE_NOR
but name SPI is already used in mkimage config format which we do not want
to change for compatibility reasons.

MVEBU_SPL_BOOT_DEVICE_MMC is for MMC and SD compatible devices. Not for
SDIO devices. In most cases used for eMMC or SD card.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:18 +01:00
Pali Rohár
50afad5573 arm: mvebu: Add support for generating PEX kwbimage
Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_PEX which instruct
make to generate kwbimage with PEX header. This image is used for booting
from PCI Express device which is in the Root Complex mode.

Support is very simple, SPL after finishes DDR training returns back to the
BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then start
executing U-Boot proper.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
67bd6158d4 arm: mvebu: Add support for generating NAND kwbimage
Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_NAND which instruct
make to generate kwbimage with NAND header. This image is used for booting
from NAND flash (either SPI or parallel).

Support is very simple, SPL after finishes DDR training returns back to the
BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then loads and
executes U-Boot proper.

To generate correct kwbimage NAND header, it is required to set following
Kconfig options:

CONFIG_SYS_NAND_PAGE_SIZE
CONFIG_SYS_NAND_BLOCK_SIZE
CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION

They are used only by make / mkimage when generating final kwbimage.

CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION is a new mvebu specific Kconfig
option which is set into kwbimage NAND_BADBLK_LOCATION header field.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
913d7561c0 arm: mvebu: spl: Fix support for loading U-Boot proper from SD card
Marvell BootROM loads MMC image from sector 0 (HW boot or data partition)
and SD image from sector 1.

So for SD card booting it is needed to not use constant CONFIG MMC options
and instead of them it is needed to define functions spl_mmc_boot_mode()
spl_mmc_get_uboot_raw_sector() which determinate offsets at SPL runtime
based on MMC or SD card.

Calculation of SD card sector expects following values:
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0

Fixes: 2226ca1734 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
2f27db2fbd arm: mvebu: spl: Load proper U-Boot from selected eMMC boot partition
When eMMC boot is selected then BootROM loads kwbimage header (U-Boot SPL)
from the selected eMMC boot partition. So for eMMC boot ensure that U-Boot
SPL loads U-Boot proper (from kwbimage) also from the same selected eMMC
boot partition.

Fixes: 2226ca1734 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
8b49e63e09 arm: mvebu: spl: Remove checks for BOOT_DEVICE_MMC2 and BOOT_DEVICE_MMC2_2
BOOT_DEVICE_MMC2 and BOOT_DEVICE_MMC2_2 are representing mmc dev 1 but all
Armada SoCs have only one mmc controller. So remove references to
non-existent second mmc controller.

Fixes: f830703f42 ("arm: mvebu: Check that kwbimage blockid matches boot mode")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
d4aa210432 arm: mvebu: spl: Fix parsing SATA kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SATA image as number of sectors the beginning of the hard
drive, but as number of sectors relative to the main header.

To process SATA kwbimage and load U-Boot proper from it in the same way as
Marvell BootROM, it is needed to interpret srcaddr as relative offset to
the main header. This change fixes booting of U-Boot proper from SPL code
in SATA image.

Fixes: 2226ca1734 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
353bdaecee arm: mvebu: spl: Fix parsing SDIO kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SDIO image as offset in number of sectors (like for SATA
image), but as offset in bytes (like for all other images except SATA).

To process SDIO kwbimage and load U-Boot proper from it in the same way as
Marvell BootROM, it is needed to interpret srcaddr in bytes. This change
fixes booting of U-Boot proper from SPL code stored in SDIO image.

Fixes: 2226ca1734 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Eugen Hristev
3bf8e40807 board: rockchip: add Radxa ROCK5B Rk3588 board
ROCK 5B is a Rockchip RK3588 based SBC (Single Board Computer) by Radxa.

There are tree variants depending on the DRAM size : 4G, 8G and 16G.

Specification:

    Rockchip Rk3588 SoC
    4x ARM Cortex-A76, 4x ARM Cortex-A55
    4/8/16GB memory LPDDR4x
    Mali G610MC4 GPU
    MIPI CSI 2 multiple lanes connector
    eMMC module connector
    uSD slot (up to 128GB)
    2x USB 2.0, 2x USB 3.0
    2x HDMI output, 1x HDMI input
    Ethernet port
    40-pin IO header including UART, SPI, I2C and 5V DC power in
    USB PD over USB Type-C
    Size: 85mm x 54mm

Kernel commits:
a1d3281450ab ("arm64: dts: rockchip: Add rock-5b board")
6fb13f888f2a ("arm64: dts: rockchip: Update sdhci alias for rock-5b")

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:29 +08:00
Jonas Karlman
3a539e0862 rockchip: rk3588: Read cpuid from otp
Read cpuid from otp and set ethaddr for RK3588.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:29 +08:00
Jonas Karlman
2eedb6d93f rockchip: rk3568: Read cpuid from otp
The cpuid on RK3568 is located at 0xa instead of 0x7 as all other SoCs.
Add and use a CFG_CPUID_OFFSET to define this offset.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
628fb0683b rockchip: misc: Set eth1addr mac address
Set eth1addr in addition to ethaddr.

Also allow fdt fixup of ethernet mac addresses when CMD_NET is disabled.
Set ethaddr and eth1addr based on HASH and SHA256 options.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
15b2d1fb72 board: rockchip: Add Edgeble Neural Compute Module 6
Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RK3588 from Edgeble AI.

General features:
- Rockchip RK3588
- up to 32GB LPDDR4x
- up to 128GB eMMC
- 2x MIPI CSI2 FPC

On module WiFi6/BT5 is available in the following Neu6 variants.

Neural Compute Module 6(Neu6) IO board is an industrial form factor
ready-to-use IO board from Edgeble AI.

IO board offers plenty of peripherals and connectivity options and
this patch enables basic eMMC and UART which is enough to successfully
boot Linux.

Neu6 needs to mount on top of this IO board in order to create a
complete Edgeble Neural Compute Module 6(Neu6) IO platform.

Boot log for the record,

DDR Version V1.08 20220617
LPDDR4X, 2112MHz
channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
Manufacturer ID:0x6
CH0 RX Vref:31.7%, TX Vref:21.8%,21.8%
CH1 RX Vref:30.7%, TX Vref:22.8%,23.8%
CH2 RX Vref:30.7%, TX Vref:22.8%,22.8%
CH3 RX Vref:30.7%, TX Vref:21.8%,21.8%
change to F1: 528MHz
change to F2: 1068MHz
change to F3: 1560MHz
change to F0: 2112MHz
out

U-Boot SPL 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530)
Trying to boot from MMC1
INFO:    Preloader serial: 2
NOTICE:  BL31: v2.3():v2.3-391-g856309329:derrick.huang
NOTICE:  BL31: Built : 14:15:50, Jul 18 2022
INFO:    ext 32k is not valid
INFO:    GICv3 without legacy support detected.
INFO:    ARM GICv3 driver initialized in EL3
INFO:    system boots from cpu-hwid-0
INFO:    idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
INFO:    dfs DDR fsp_params[0].freq_mhz= 2112MHz
INFO:    dfs DDR fsp_params[1].freq_mhz= 528MHz
INFO:    dfs DDR fsp_params[2].freq_mhz= 1068MHz
INFO:    dfs DDR fsp_params[3].freq_mhz= 1560MHz
INFO:    BL31: Initialising Exception Handling Framework
INFO:    BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
ERROR:   Error initializing runtime service opteed_fast
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0xa00000
INFO:    SPSR = 0x3c9

U-Boot 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530)

Model: Edgeble Neu6A IO Board
DRAM:  7.5 GiB (effective 3.7 GiB)
Core:  71 devices, 15 uclasses, devicetree: separate
MMC:   mmc@fe2c0000: 0
Loading Environment from nowhere... OK
In:    serial@feb50000
Out:   serial@feb50000
Err:   serial@feb50000
Model: Edgeble Neu6A IO Board
Net:   No ethernet found.
Hit any key to stop autoboot:  0
=>

Add support for Edgeble Neu6 Model A IO Board.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
95c8656b72 ARM: dts: rockchip: rk3588s-u-boot: Add sdmmc node
Booting from SDMMC is one of the fast and easy booting methods
for initial support of any SoC to upstream more features. 

This patch is trying to add the sdmmc node for rk3588 and added
as u-boot specific node in -u-boot.dtsi as upstream Linux is not
supporting yet.

As soon as Linux supports it, a sync of the Linux device tree
would eventually drop this node. 

Clock properties as added according to the rockchip mmc driver
but the actual definition might add scmi clocks into 0 and 1
indexes. This is due to scmi clock are not supporting in upstream
U-Boot. Properly addition of scmi clock would eventually follow
sdmmc clock definition of Linux once they upstreamed.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-02-28 18:07:28 +08:00
Jagan Teki
2a8481ec16 ARM: dts: rockchip: Add rk3588-u-boot.dtsi
Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
for Rockchip RK3588 SoC to boot the SPL.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
f5bc9929a2 arm: rockchip: Add RK3588 arch core support
The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76
and quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU,
Mali-G610 MP4, HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2,
LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0,
PCIe 3.0, SATA 3, Ethernet, SDIO3.0 I2C, UART, SPI, GPIO and PWM.

Add arch core support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
5457e15272 arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A IO
Neural Compute Module 6(Neu6) IO board is an industrial form factor
ready-to-use IO board from Edgeble AI.

IO board offers plenty of peripherals and connectivity options and
this patch enables basic eMMC and UART which is enough to successfully
boot Linux.

Neu6 needs to mount on top of this IO board in order to create a
complete Edgeble Neural Compute Module 6(Neu6) IO platform.

commit <a5079a534554> ("arm64: dts: rockchip: rk3588: Add Edgeble Neu6
Model A IO")

Add support for Edgeble Neu6 Model A IO Board.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
a0e94b877c arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A SoM
Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RK3588 from Edgeble AI.

General features:
- Rockchip RK3588
- up to 32GB LPDDR4x
- up to 128GB eMMC
- 2x MIPI CSI2 FPC

On module WiFi6/BT5 is available in the following Neu6 variants.

Neu6 needs to mount on top of associated Edgeble IO boards for
creating complete platform solutions.

Enable eMMC for now to boot Linux successfully.

commit <3d9a2f7e7c5e> ("arm64: dts: rockchip: rk3588: Add Edgeble Neu6
Model A SoM")

Add support for Edgeble Neu6 Model A SoM.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
515773ba9d arm64: dts: rockchip: Add base DT for rk3588 SoC
This initial version supports CPU, dma, interrupts, timers, UART and
SDHCI (everything necessary to boot Linux on this system on chip) as
well as Ethernet, I2C, PWM and SPI.

The DT is split into rk3588 and rk3588s, which is a reduced version
(i.e. with less peripherals) of the former.

commit <9fb232e9911f> (" arm64: dts: rockchip: Add base DT for rk3588
SoC")
commit <d68a97d501f8> ("arm64: dts: rockchip: Add rk3588 pinctrl data")

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
d8656cb647 arm: rockchip: Add ioc header for rk3588
Add IOC unit header include for rk3588.

Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
b851c006a1 clk: rockchip: pll: Add pll_rk3588 type for rk3588
Add RK3588 pll set and get rate clock support.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
73a21ebf47 arm: rockchip: Add grf header for rk3588
Add GRF header for Rockchip RK3588.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
165d258386 arm: rockchip: Add cru header for rk3588
Add clock and reset unit header include for rk3588.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Chris Morgan
e92754e20c arm64: dts: rockchip: add gpio-ranges property to gpio nodes
Add gpio-ranges property to GPIO nodes so that the bank ID can
be correctly derived for each GPIO bank.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Chris Morgan
95ef2aaedc rockchip: rk3568: enable automatic power savings
It enables automatic clock gating on idle, disables the eDP phy by
default, and sets the core pvtpll ring length. It is reported this
lowers the temperature on at least one SoC by 7C.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Chris Morgan
0d61f8e5f1 rockchip: rk3568: add boot device detection
Enable spl to detect which device it was booted from.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Chris Morgan
e2df30c6c6 arm64: dts: rockchip: Sync rk356x from Linux main
Sync rk3566 and rk3568 from the mainline Linux kernel (6.2-rc2 as of
this writing).

Note that this will rename the rk3568-evb to rk3568-evb1-v10.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Chris Morgan
02cbda2b72 dts: rockchip: px30: add gpio-ranges property to gpio nodes
Add the gpio-ranges property to each GPIO node for use in deriving
the correct bank ID. Note that invoking "gpio status -a" no longer
causes the board to hit a "Synchronous Abort".

Fixes: 537b1a2774 ("rockchip: add px30 devicetrees")

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Manoj Sai
2c99198574 rockchip: rk3568: Select DM_REGULATOR_FIXED
Select the DM_REGULATOR_FIXED on RK3568 platform.

Co-developed-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
3abfd33e57 arm64: dts: rk356x-u-boot: Drop combphy1 assigned-clocks/rates
combphy1 is failing to probe due to unhandled assigned-clocks and
assigned-clocks-rates.

=> usb start
starting USB...
Bus usb@fd000000: Failed to get PHY1 for usb@fd000000
Port not available.
Bus usb@fd800000: USB EHCI 1.00

There is no real requirement for them in U-Boot to handle, hence
mark them as deleted-properties for the  probe to success

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
3dd126155c board: rockchip: Add Radxa Compute Module 3 IO Board
Radxa Compute Module 3(CM3) IO board an application board from Radxa
and is compatible with Raspberry Pi CM4 IO form factor.

Radxa CM3 needs to mount on top of this IO board in order to create
complete Radxa CM3 IO board platform.

Add support for Radxa CM3 IO Board defconfig and -u-boot.dtsi

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
3356c67d1f arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3 IO
Radxa Compute Module 3(CM3) IO board an application board from Radxa
and is compatible with Raspberry Pi CM4 IO form factor.

Specification:
- 1x HDMI,
- 2x MIPI DSI
- 2x MIPI CSI2
- 1x eDP
- 1x PCIe card
- 2x SATA
- 2x USB 2.0 Host
- 1x USB 3.0
- 1x USB 2.0 OTG
- Phone jack
- microSD slot
- 40-pin GPIO expansion header
- 12V DC

Radxa CM3 needs to mount on top of this IO board in order to create
complete Radxa CM3 IO board platform.

linux-next commit for the same,

commit <8f19828844f2> ("arm64: dts: rockchip: Fix compatible for Radxa
CM3")

Add support for Radxa CM3 IO Board.

Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Jagan Teki
63391b198a arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3
Radxa Compute Module 3(CM3) is one of the modules from a series
System On Module based on the Radxa ROCK 3 series and is compatible
with Raspberry Pi CM4 pinout and form factor.

Specification:
- Rockchip RK3566
- up to 8GB LPDDR4
- up to 128GB high performance eMMC
- Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless,
  BT 5.0, BLE with onboard and external antenna.
- Gigabit Ethernet PHY

Radxa CM3 needs to mount on top of this IO board in order to create
complete Radxa CM3 IO board platform.

Since Radxa CM3 is compatible with Raspberry Pi CM4 pinout so it is
possible to mount Radxa CM3 on top of the Rasberry Pi CM4 IO board.

linux-next commit for the same,

commit <8f19828844f2> ("arm64: dts: rockchip: Fix compatible for Radxa
CM3")

Add support for Radxa CM3.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2023-02-28 18:07:26 +08:00
Jagan Teki
5f5b1cf3ff rockchip: rk3568: Move DM_RESET in arch kconfig
Like other rockchip SoCs, DM_RESET is useful across rk3568
platform.

Select it from arch kconfig.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Akash Gajjar
6cd6ed9da5 arm64: dts: rockchip: rk3308: Add Radxa ROCK Pi S support
Add Radxa ROCK 3 Model A support. sync rk3308-rock-pi-s.dts from
Linux 6.2.0-rc7.

ROCK Pi S is RK3308 based SBC from radxa.com. ROCK Pi S has a,
- 256MB/512MB DDR3 RAM
- SD, NAND flash (optional on board 1/2/4/8Gb)
- 100MB ethernet, PoE (optional)
- Onboard 802.11 b/g/n wifi + Bluetooth 4.0 Module
- USB2.0 Type-A HOST x1
- USB3.0 Type-C OTG x1
- 26-pin expansion header
- USB Type-C DC 5V Power Supply

Linux commit commit for the same,
<2e04c25b1320> ("arm64: dts: rockchip: add ROCK Pi S DTS support")

Signed-off-by: Akash Gajjar <gajjar04akash@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Akash Gajjar
b44c54f600 arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board support
Add Radxa ROCK 3 Model A support. sync rk3568-rock-3a.dts from Linux 6.2.0-rc7

Board Specifications
- Rockchip RK3568
- 2/4/8GB LPDDR4 3200MT/s
- eMMC socket, SD card slot
- GbE LAN
- PCIe 3.0/2.0
- M.2 Connector
- 3.5mm Audio jack with mic
- HDMI 2.0, MIPI DSI/CSI
- USB 3.0 Host/OTG, USB 2.0 Host
- 40-pin GPIO expansion ports
- USB Type C PD 2.0, 9V/2A, 12V/2A, 15V/2A, 20V/2A

Refer Linux commit <22a442e6586c>
("arm64: dts: rockchip: add basic dts for the radxa rock3 model a")

Signed-off-by: Akash Gajjar <gajjar04akash@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Jonas Karlman
4773e9d5ed rockchip: Use an external TPL binary on RK3568
Rockchip SoCs typically use U-Boot TPL to initialize DRAM, then jumps
back to BootRom to load next stage, U-Boot SPL, into DRAM. BootRom then
jumps to U-Boot SPL to continue the normal boot flow.

However, there is no support to initialize DRAM on RK35xx SoCs using
U-Boot TPL and instead an external TPL binary must be used to generate a
bootable u-boot-rockchip.bin image.

Add CONFIG_ROCKCHIP_EXTERNAL_TPL to indicate that an external TPL should
be used. Build U-Boot with ROCKCHIP_TPL=/path/to/ddr.bin to generate a
bootable u-boot-rockchip.bin image for RK3568.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-02-28 18:07:26 +08:00
Jonas Karlman
f0498b2be2 rockchip: dts: rk3328: fix sdram params
The rk3328 sdram driver read sdram parameters from the devicetree into a
struct rk3328_sdram_params using dev_read_u32_array.

After commit 5ab30c3176 ("ram: rockchip: Update ddr pctl regs for px30")
changed the size of struct ddr_pctl_regs, a member of struct
rk3328_sdram_params, U-Boot TPL can no longer initialize DRAM on RK3328.

Add ten u32 to the sdram parameter array in devicetree to align with
this size change. This fixes DRAM initialization on RK3328.

Fixes: 5ab30c3176 ("ram: rockchip: Update ddr pctl regs for px30")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3328-cc
2023-02-28 18:07:26 +08:00
Jonas Karlman
2ec15cabe9 rockchip: sdram: add dram bank with usable memory beyond 4GB
Add a second dram bank of usable memory beyond the blob of space for
peripheral near 4GB. Any memory that exists beyond the 4GB mark is added
to the second bank.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Jonas Karlman
bde73b14f0 rockchip: sdram: add basic support for sdram reg info version 3
Newer DRAM initialization blobs from vendor can encode sdram info in a
new version 3 format. The new format makes use of more bits in sys_reg3
compared to the version 2 format.

Add basic support for detecting the version 3 format and decoding the
high bits used for ddrtype.

This fixes decode of sdram size on my RK3568 boards that have LPDDR4X.

Details on the new format was deciphered from vendor u-boot commit [1].

[1] c69667e0e2

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Christian Kohlschütter
2492ba8a3b arm: dts: rockchip: rk3399: nanopi-r4s: Provide smbios sysinfo
Provide human-readable manufacturer and product names for the
FriendlyELEC NanoPi R4S.

Enable CONFIG_SYSINFO and CONFIG_SYSINFO_SMBIOS by default.

Signed-off-by: Christian Kohlschütter <christian@kohlschutter.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:26 +08:00
Mihai Sain
1415cdac77 ARM: dts: at91: sama7g5: fix clock id for ebi node
The PMC_MCK1 clock id for the ebi node is 23.

Fixes: 746b738224 ("ARM: dts: at91: sama7g5/sama7g5ek: align with Linux DT")
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2023-02-28 10:38:19 +02:00
Simon Glass
4fef657151 tpm: Separate out the TPM tests for v1 and v2
Currently there is only one test and it only works on TPM v2. Update it
to work on v1.2 as well, using a new function to pick up the required
TPM.

Update sandbox to include both a v1.2 and v2 TPM so that this works.
Split out the existing test into two pieces, one for init and one for
the v2-only report_state feature.

Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-02-28 09:44:30 +02:00
Tom Rini
5b197eee33 Prepare v2023.04-rc3
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Merge tag 'v2023.04-rc3' into next

Prepare v2023.04-rc3
2023-02-27 17:28:21 -05:00
Tom Rini
0024e7f72b Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-tegra 2023-02-23 17:40:18 -05:00
Svyatoslav Ryhel
5a8fe1ee81 ARM: tegra20: implement BCT patching
This function allows updating bootloader from u-boot
on production devices without need in host PC.

Be aware! It works only with re-crypt BCT.

Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Signed-off-by: Ramin Khonsari <raminterex@yahoo.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Ramin Khonsari
327ff8e0a4 ARM: tegra30: implement BCT patching
This function allows updating bootloader from u-boot
on production devices without need in host PC.

Be aware! It works only with re-crypted BCT.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Ramin Khonsari <raminterex@yahoo.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
bab087802a ARM: tegra: crypto: extend crypto functional
Add support for encryption, decryption and signinig with
non-zero key saving backward compatibility.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
8ed2bd1d1b ARM: tegra: expose crypto module for all Tegra SoCs
Move crypto module from T20 only into common Tegra dir.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
5668c75ce9 board: tegra30: switch to updated pre-dm i2c write
Configure PMIC voltages for early stages using updated
early i2c write.

Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
4213d52b33 ARM: tegra: create common pre-dm i2c write
This implementation allows pwr i2c writing on early SPL
stages when DM is not yet setup.

Such writing is needed to configure main voltages of PMIC
on early SPL for bootloader to boot properly.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
1a7ce63c08 ARM: tegra: add late init support
Late init function allows passing values like identifiers and
perform device specific configurations of pre-boot stage.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
23d24df34c ARM: tegra: Fix Tegra PWM parent clock
Default parent clock for the PWM on Tegra is a 32kHz clock and
is unable to support the requested PWM period.

Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
updating the parent clock for the PWM to be the PLL_P.

This commit is equivalent to Linux kernel commit:
https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
678157e212 ARM: tegra30: add PLLD to pll setup
On T30 unlike T20 dsi panels are wider used on devices
and PLLD is used as DISP1 parent more often, so lets
enable it as well for this cases.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
a81d792479 ARM: tegra: clock: add clock_decode_pair helper
Get periph clock id and its parent from device tree.
This works by looking up the peripheral's 'clocks' node and
reading out the second and fourth cells, which are the
peripheral and PLL clock numbers.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
65e02744ec ARM: tegra: clock: add clk_id_to_pll_id helper
This function allows to convert a device tree clock ID to PLL ID.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
2fafac30ef ARM: t20/t30: swap host1x and disp1 clock parents
According to mainline clock tables and TRM HOST1X
parent is PLLC, while DISP1 usually uses PLLP as
parent clock.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
fca18a2643 tegra30: clock: add EXTPERIPH
This mappings were missing for some reason.

Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Tom Rini
d85bc196cb x86: Pass -z execstack for EFI payload flags
To match how we link EFI executables elsewhere, and to silence a linker
warning, pass -z execstack here as well.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-23 13:29:20 -05:00
Paweł Anikiel
48c172c2f8 arm: dts: chameleonv3: Add 270-2 variant
Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the
Mercury+ AA1 module

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22 00:28:39 +01:00
Paweł Anikiel
9c107ab42b arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsi
This file is included by the different chameleonv3 variants. Change the
name to .dtsi.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22 00:28:39 +01:00
Paweł Anikiel
1d222089f0 arm: dts: chameleonv3: Override chameleonv3 bitstream names
Set the bitstream name per Chameleon variant. This allows the same
boot filesystem with all bitstream variants to be used on different
boards.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22 00:28:39 +01:00
Rick Chen
7574b6476a riscv: binman: Add help message for missing blobs
Add the 'missing-msg' for more detailed output
on missing system firmware.

Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-02-17 19:07:48 +08:00
Leo Yu-Chi Liang
8900e2bbec riscv: Rename Andes cpu and board names
The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
487c211ef6 configs: ae350: Enable v5l2 cache for AE350 platforms in SPL
To reduce the code size, CONFIG_V5L2_CACHE was disabled since commit:
ca06444aac

Turing on does not significantly increase the size of u-boot-spl.bin,
so we enable it by default to improve performance.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
600a708c05 riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL
This patch refines L1 cache enable/disable and v5l2-cache enable
functions.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
c1b8819680 riscv: ae350: dts: Update L2 cache compatible string
Update the compatible string of L2 cache.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
d8a146d19b riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()
As the OpenSBI v1.2 does not enable the cache [0], we enable
the i/d-cache in harts_early_init() and do not disable in
cleanup_before_linux(). This patch also simplifies the logic
and moves the CSR encoding to include/asm/arch-andes/csr.h.

[0] bd7ef41398

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Leo Yu-Chi Liang
55ca747f66 riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"
There is no need for RISCV_NDS_CACHE config to control cache switches.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Yu Chien Peter Lin
daf1312b07 riscv: global_data.h: Correct the comment for PLICSW
PLIC is used for external interrupt, while PLICSW is an Andes-specific
design for software interrupt.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
Simon Glass
8c103c33fb dm: dts: Convert driver model tags to use new schema
Now that Linux has accepted these tags, move the device tree files in
U-Boot over to use them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-14 09:43:26 -07:00
Sumit Garg
b97487db4e clocks: qcs404: Add support for I2C clocks
Co-developed-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-13 10:01:52 -05:00
Tom Rini
d7bcd6ee40 Merge tag 'i2c-updates-for-v2023.04' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c updates for v2023.04

- add new i2c driver ast2600 from Ryan Chen

- i2c-cdns: make read fifo-depth configurable through device tree
  from Pei Yue Ho

- mxc i2c driver: print base address in hex, not in decimal
  from Fabio
2023-02-13 09:57:35 -05:00
Tony Dinh
dd15284b74 arm: kirkwood: Enable uart0 dm-pre-reloc for Pogoplug V4 board
When DM_SERIAL is enabled, the device-tree tag u-boot,dm-pre-reloc is
required for this board to boot over UART with kwboot. Enable this in
kirkwood-pogoplug-series-4-u-boot.dtsi.

Added by Stefan while applying:
Please note that it's not fully understood, why this property really
is needed. Here a link to the discussion about this:

https://lore.kernel.org/r/20230201080210.ypz4nrj4y2igwxz3@pali/

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13 10:15:04 +01:00
Tony Dinh
b21f87a5a5 arm: mvebu: Add support for Synology DS116 (Armada 385)
Synology DS116 is a NAS based on Marvell Armada 385 SoC.

Board Specification:

- Marvel MV88F6820 Dual Core at 1.8GHz
- 1 GiB DDR3 RAM
- 8MB Macronix mx25l6405d SPI flash
- I2C
- 2x USB 3.0
- 1x GBE LAN port (PHY: Marvell 88E1510)
- 1x SATA (6 Gbps)
- 3x LED
- PIC16F1829 (connected to uart1)
- GPIO fan
- serial console

Note that this patch depends on the add-support for Thecus N2350 patch:
https://patchwork.ozlabs.org/project/uboot/patch/20230201231306.7010-1-mibodhi@gmail.com/

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2023-02-13 10:14:50 +01:00
Tony Dinh
3fdd09f90f arm: mvebu: Add support for Thecus N2350 (Armada 385) board
Thecus N2350 is a NAS based on Marvell Armada 385 SoC.

Specification:

- Processor: Marvel MV88F6820 Dual Core at 1GHz
- 1 GiB DDR4 RAM
- 4MB Macronix mx25l3205d SPI flash
- 512MB Hynix H27U4G8F2DTR-BC NAND flash
- I2C
- 2x USB 3.0
- 1x GBE LAN port (PHY: Marvell 88E1510)
- 2x SATA (hot swap slots)
- 3x buttons
- 10x LEDS
- serial console

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13 10:14:50 +01:00
Tony Dinh
5c73428f4a arm: kirkwood: Use CONFIG_SYS_NS16550 with DM_SERIAL for Kirkwood boards
CONFIG_SYS_NS16550 is required when DM_SERIAL is enabled for
Kirkwood boards.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-02-13 10:14:50 +01:00
Ryan Chen
87f5b5d683 arm: aspeed: dtsi: add reg for i2c
The i2c driver have global register that i2c bus use
ofnode_get_parent to get parent register address.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13 09:57:58 +01:00
Jade Lovelace
a5e490f14e socfpga: fix the serial console on DE1-SoC
Previously, the TX LED would flash but nothing would appear on the
serial port, and the board would appear dead with a build of the
socfpga_cyclone5_defconfig. I have verified that adding the frequency to
the uart will fix the serial console on my board.

Thanks to @ehoffman on the Rocketboards forum:
https://forum.rocketboards.org/t/cyclonev-programming-fpga-from-u-boot/2230/30

Signed-off-by: Jade Lovelace <lists@jade.fyi>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-12 15:47:19 -05:00
Tom Rini
386e77cda8 Merge branch 'for-2023.04' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx
- A fix for a long standing bug that has been exposed by commit
  50128aeb0f ("cyclic: get rid of cyclic_init()") preventing 8xx boards
  from booting since u-boot 2023.01
- A GPIO driver for powerpc 8xx chip
- Fixup for powerpc 8xx SPI driver
- A new powerpc 8xx board
- The two devices having that board.
2023-02-12 15:25:09 -05:00
Christophe Leroy
dac3c6f625 board: cssi: Add new board MCR3000_2G
This adds a new board from CS GROUP. The board is called
MCR3000_2G, and has a CPU board called CMPC885.

That CPU board is shared with another equipment that will
be added in a later patch.

That board stores Ethernet MAC addresses in an EEPROM which
is accessed using SPI bus.

This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
2023-02-11 08:47:58 +01:00
Christophe Leroy
0223939498 driver, gpio: Add support for MPC 8xx CPU ports
Ports A, C and D are 16 bits ports.
Ports B and E are 32 bits ports.

The "compatible" is used to determine each port type.

This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
2023-02-11 08:47:58 +01:00
Christophe Leroy
d8809bac48 board: MCR3000: Use lowercase filenames
Rename MCR3000.* to mcr3000.* to be more in line with
other boards.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-02-10 19:33:25 +01:00
Christophe Leroy
2eed0c25f6 powerpc/mpc8xx: Zero boot_flags arg for calling board_init_f()
Copied from e83a7e9453 ("powerpc/mpc83xx: Zero boot_flags arg for
calling board_init_f()")

The argument boot_flags of board_init_f() is not used at all in the
powerpc specific board.c init sequence. Now with the generic init
sequence, this boot_flags arg is used by board_init_f().

This patch sets the r3 register that is used to pass the boot_flags
argument from the start.S board_init_f() call to 0 prior to the function
call to avoid unknown content to end up in gd->flags.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Fixes: 09f3ca3dd5 ("arm, powerpc: select SYS_GENERIC_BOARD")
2023-02-10 19:31:36 +01:00
Dzmitry Sankouski
ea6fdc1359 dm: button: add support for linux_code in button-gpio.c driver
Linux event code must be used in input devices, using buttons.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-10 12:50:01 -05:00
Dzmitry Sankouski
298ffdd5d6 test: create dedicated fdt node for ofnode_for_each_prop test
Property count may change in /buttons node, if more button tests added,
and this will break ofnode_for_each_prop.
Add separate node for mentioned test.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-10 12:50:01 -05:00
Dzmitry Sankouski
2ea062265f dts: add missing linux,code in gpio-keys
gpio-keys linux driver enforces user to specify linux,code.
Add missing linux,code before implementing button input support.

- arch/arm/dts/rk3288-popmetal.dtsi -> KEY_POWER
- arch/arm/dts/rk3288-tinker.dtsi -> KEY_POWER
- arch/arm/dts/am3517-evm-ui.dtsi -> KEY_RECORD
- sandbox/dts/sandbox.dtsi -> BTN_1
- sandbox/dts/sandbox.dts -> BTN_1

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-10 12:50:01 -05:00
Sumit Garg
baf0677b74 dts: qcs404-evb: Add I2C controller nodes
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10 12:50:00 -05:00
Sumit Garg
c9ec1971c6 pinctrl: qcs404: Enable I2C pinmux options
Co-developed-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10 12:50:00 -05:00
Sumit Garg
22d3fcd337 clock-snapdragon: Add clk_rcg_set_rate() with mnd_width=0
Add clk_rcg_set_rate() which allows to configure clocks without programming
MND values. This is required for configuring I2C clocks on QCS404.

Co-developed-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10 12:50:00 -05:00
Sumit Garg
de8f42c93a dts: qcs404-evb: Add ethernet controller node
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10 12:50:00 -05:00
Sumit Garg
56443285f2 pinctrl-snapdragon: Get rid of custom drive-strength values
Use standard pinconf drive-strength values from Linux DT bindings rather
than ones based on custom u-boot header. These changes are in direction
to make u-boot DTs for Qcom SoCs to be compatible with standard Linux
DT bindings.

Also, add support for pinconf bias-pull-up.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10 12:50:00 -05:00
Sumit Garg
c9062b3988 pinctrl: qcs404: Enable ethernet pinmux options
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10 12:50:00 -05:00
Sumit Garg
71ffa23fea clocks: qcs404: Add support for ethernet clocks
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10 12:50:00 -05:00
Sumit Garg
0d6def46e0 qcs404-evb: Enable msm_gpio driver support
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10 12:50:00 -05:00
Sumit Garg
881338a0c6 qcs404: sysmap: Don't map reserved memory ranges
Currently u-boot maps whole of 1G RAM but there reserved memory ranges on
QCS404 which are reserved for TrustZone, various firmware components etc.
Any access to these reserved memory ranges causes a bus hang issue. So
disable mapping for reserved memory ranges in u-boot.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10 12:50:00 -05:00
Simon Glass
ce119a2706 Correct SPL uses of ROCKCHIP_OTP
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_ROCKCHIP_OTP defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:41 -05:00
Simon Glass
41782a9c09 Correct SPL uses of FASTBOOT
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_FASTBOOT defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:41 -05:00
Simon Glass
91b614eef6 Correct SPL uses of USB_KEYBOARD
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_USB_KEYBOARD defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:40 -05:00
Simon Glass
e7ec875dd1 Correct SPL use of SYS_FSL_ERRATUM_A010539
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_SYS_FSL_ERRATUM_A010539 defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:40 -05:00
Simon Glass
4610ae38d5 Correct SPL use of STM32MP15X_STM32IMAGE
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_STM32MP15X_STM32IMAGE defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:40 -05:00
Simon Glass
4c77608942 Correct SPL uses of SAVE_PREV_BL_INITRAMFS_START_ADDR
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_SAVE_PREV_BL_INITRAMFS_START_ADDR defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:40 -05:00
Simon Glass
10f8bc0983 Correct SPL uses of SAVE_PREV_BL_FDT_ADDR
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_SAVE_PREV_BL_FDT_ADDR defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:40 -05:00
Simon Glass
3c9adeb330 Correct SPL uses of ROCKCHIP_EFUSE
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_ROCKCHIP_EFUSE defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:40 -05:00
Simon Glass
9dcf5ee586 Correct SPL uses of PMIC_STPMIC1
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_PMIC_STPMIC1 defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:40 -05:00
Simon Glass
7032fa28fd Correct SPL use of OCTEON_SERIAL_PCIE_CONSOLE
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_OCTEON_SERIAL_PCIE_CONSOLE defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:39 -05:00
Simon Glass
60b0002e25 Correct SPL use of OCTEON_SERIAL_BOOTCMD
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_OCTEON_SERIAL_BOOTCMD defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:39 -05:00
Simon Glass
0ab3609061 Correct SPL uses of MTD
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_MTD defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:39 -05:00
Simon Glass
a867392791 Correct SPL use of MIPS_CM
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_MIPS_CM defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:39 -05:00
Simon Glass
210af54947 Correct SPL uses of LMB
This converts 9 usages of this option to the non-SPL form, since there is
no SPL_LMB defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:39 -05:00
Simon Glass
24f95e141e Correct SPL uses of IMX_MODULE_FUSE
This converts 6 usages of this option to the non-SPL form, since there is
no SPL_IMX_MODULE_FUSE defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:39 -05:00
Simon Glass
418f2173b1 Correct SPL use of EXYNOS7420
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_EXYNOS7420 defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09 16:32:26 -05:00
Simon Glass
f27a545b8f Correct SPL use of DISPLAY_CPUINFO
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_DISPLAY_CPUINFO defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09 16:32:26 -05:00
Simon Glass
7c31107249 Correct SPL uses of CPU_MICROBLAZE
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_CPU_MICROBLAZE defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09 16:32:26 -05:00
Simon Glass
799e5be706 Correct SPL use of CMD_NET
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_CMD_NET defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09 16:32:26 -05:00
Simon Glass
38223fb23f Correct SPL use of CMD_BOOTZ
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_CMD_BOOTZ defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09 16:32:25 -05:00
Simon Glass
b8bffe661f Correct SPL uses of BOOTSTAGE_REPORT
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_BOOTSTAGE_REPORT defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09 16:32:25 -05:00
Simon Glass
e1f0f8ac9f Correct SPL use of BOOTSTAGE_FDT
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_BOOTSTAGE_FDT defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09 16:32:25 -05:00
Simon Glass
611e9af07c Correct SPL uses of ARMADA_8K
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_ARMADA_8K defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09 16:32:25 -05:00
Simon Glass
c1c5538e7e Correct SPL uses of ARMADA_3700
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_ARMADA_3700 defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09 16:32:25 -05:00
Simon Glass
51864cdcbc Correct SPL uses of ALLEYCAT_5
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_ALLEYCAT_5 defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09 16:32:25 -05:00
Simon Glass
ffff21fb27 x86: Correct Chrromebook typo
Fix a typo in a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09 16:32:25 -05:00
Simon Glass
c090ffb843 rmobile: Drop unused ehci-rmobile driver
This is not used. Drop the driver and Kconfig option.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07 14:33:50 -05:00
Simon Glass
295ae34c07 sh4: Drop unused pci_sh7780 driver
This is not used. Drop the driver and Kconfig option.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07 14:33:49 -05:00
Simon Glass
69f06c8da6 rmobile: Drop CONFIG_SH73A0 and associated code
This option does not exist, so the code attached to it is not used. Drop
it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07 14:33:49 -05:00
Simon Glass
dbcbbfd725 mtd: Drop unused CONFIG_S32V234
This option does not exist, so the Makefile rule does nothing. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07 14:33:49 -05:00
Simon Glass
ba9bb035a9 rmobile: Drop CONFIG_RMOBILE
This has been renamed to CONFIG_ARCH_RMOBILE but this one was left behind.
It doesn't point to a directory that exists, so just drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07 14:33:49 -05:00
Simon Glass
408296aad9 gpio: Drop unused pca9698 driver
This is not used. Drop the driver and Kconfig option.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07 14:33:49 -05:00
Simon Glass
8697ea97bd arc: Drop CONFIG_MMU
This option is set in the Makefile but has no effect in the assembly
code, i.e. the #ifdef branch is never used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07 14:33:48 -05:00
Simon Glass
9df5011e1e arm: Drop CONFIG_MMU
This option does not exist, so the #ifdefs do nothing. Drop this code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07 14:33:48 -05:00