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riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()

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As the OpenSBI v1.2 does not enable the cache [0], we enable
the i/d-cache in harts_early_init() and do not disable in
cleanup_before_linux(). This patch also simplifies the logic
and moves the CSR encoding to include/asm/arch-andes/csr.h.

[0] bd7ef41398

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Yu Chien Peter Lin 2023-02-06 16:10:47 +08:00 committed by Leo Yu-Chi Liang
parent 51415fa634
commit d8a146d19b
2 changed files with 43 additions and 37 deletions
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49
arch/riscv/cpu/ax25/cpu.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Andes Technology Corporation
* Copyright (C) 2023 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/
@ -10,23 +10,7 @@
#include <irq_func.h>
#include <asm/cache.h>
#include <asm/csr.h>
#define CSR_MCACHE_CTL 0x7ca
#define CSR_MMISC_CTL 0x7d0
#define CSR_MARCHID 0xf12
#define V5_MCACHE_CTL_IC_EN_OFFSET 0
#define V5_MCACHE_CTL_DC_EN_OFFSET 1
#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8
#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19
#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20
#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
#define V5_MCACHE_CTL_CCTL_SUEN BIT(V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
#include <asm/arch-andes/csr.h>
/*
* cleanup_before_linux() is called just before we call linux
@ -38,38 +22,29 @@ int cleanup_before_linux(void)
{
disable_interrupts();
/* turn off I/D-cache */
cache_flush();
icache_disable();
dcache_disable();
return 0;
}
void harts_early_init(void)
{
/* Enable I/D-cache in SPL */
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN |
MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN);
if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN))
mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN;
if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN))
mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN;
csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
/*
* Check DC_COHEN_EN, if cannot write to mcache_ctl,
* we assume this bitmap not support L2 CM
* Check mcache_ctl.DC_COHEN, we assume this platform does
* not support CM if the bit is hard-wired to 0.
*/
mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) {
/* Wait for DC_COHSTA bit be set */
while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN))
mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
/* Wait for DC_COHSTA bit to be set */
while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
}
}
}

31
arch/riscv/include/asm/arch-andes/csr.h Normal file
View file

@ -0,0 +1,31 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2023 Andes Technology Corporation
*/
#ifndef _ASM_ANDES_CSR_H
#define _ASM_ANDES_CSR_H
#include <asm/asm.h>
#include <linux/const.h>
#define CSR_MCACHE_CTL 0x7ca
#define CSR_MMISC_CTL 0x7d0
#define CSR_MARCHID 0xf12
#define CSR_MCCTLCOMMAND 0x7cc
#define MCACHE_CTL_IC_EN_OFFSET 0
#define MCACHE_CTL_DC_EN_OFFSET 1
#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
#define MCACHE_CTL_DC_COHEN_OFFSET 19
#define MCACHE_CTL_DC_COHSTA_OFFSET 20
#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET)
#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET)
#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET)
#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET)
#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET)
#define CCTL_L1D_WBINVAL_ALL 6
#endif /* _ASM_ANDES_CSR_H */