Upstream linux commit 69fc01296c9281
commit a1286a1fc4 ("mtd: nand: Move Samsung specific init/detection
logic in nand_samsung.c") introduced a regression for Samsung SLC NAND
chips. Prior to this commit chip->bits_per_cell was initialized by calling
nand_get_bits_per_cell() before using nand_is_slc().
With the offending commit this call is skipped, leaving
chip->bits_per_cell cleared to zero when the manufacturer specific
'.detect' function calls nand_is_slc() which in turn interprets
bits_per_cell != 1 as indication for an MLC chip.
The effect is that e.g. a K9F1G08U0F NAND chip is falsely detected as
MLC NAND with 4KiB page size rather than SLC with 2KiB page size.
Add a call to nand_get_bits_per_cell() before calling the .detect hook
function in nand_manufacturer_detect(), so that the nand_is_slc()
calls in the manufacturer specific code will return correct results.
Reported-by: Marcin Gołaś <marcingol30@gmail.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221021060536.11747-1-michael@amarulasolutions.com
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Allocate omap_ecclayout on the heap as we have
limited .bss space on AM64 R5 SPL configuration.
Reduces .bss usage by 2984 bytes.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221011115012.6181-9-rogerq@kernel.org
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Fixes the below build warning on 64-bit platforms.
drivers/mtd/nand/raw/nand_spl_loaders.c:26:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
dst = (void *)((int)dst - page_offset);
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221011115012.6181-8-rogerq@kernel.org
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Rename omap_nand_read() to omap_nand_read_buf() to reflect
actual behaviour.
Use FIFO read address instead of raw read address for reads.
The GPMC automatically converts 32-bit/16-bit reads to NAND
device specific reads (8/16 bit). Use the largest possible
read granularity size for more efficient reads.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221011115012.6181-5-rogerq@kernel.org
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Pointer size cannot be assumed to be 32-bit, so use
use uintptr_t instead of uint32_t.
Fixes the below build warning on 64-bit builds.
drivers/mtd/nand/raw/omap_gpmc.c:439:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
head = ((uint32_t) buf) % 4;
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221011115012.6181-4-rogerq@kernel.org
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
The GPMC module is present on some K2 and K3 SoCs.
Enable building GPMC NAND driver for K2/K3 platforms.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221011115012.6181-3-rogerq@kernel.org
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
We want to get rid of <asm/arch/mem.h> so don't
enforce it for new platforms.
This also means GPMC_MAX CS doesn't have to be defined
by platform code.
Define it locally here for now.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221011115012.6181-2-rogerq@kernel.org
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Introduce the auto-generated clock tree and power domain data needed to
attach the am62a into the power-domain and clock frameworks of uboot
Signed-off-by: Bryan Brattlof <bb@ti.com>
TI's am62a family of SoCs uses a new 32bit DDR controller that shares
much of the same functionality with the existing am64 and j721e
controllers.
Select this controller by default when u-boot is build for the am62a
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The new 32bit DDR controller for TI's am62a family of SoCs shares much
of the same functionality with the existing 16bit (am64) and 32bit
(j721e) controllers, so this patch reorganizes the existing
auto-generated macros for the 16bit and 32bit controllers to make room
for the macros for the am62a's controller
This patch consists mostly of header/macro renames and additions with a
new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new
macros during compilation.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Replace 0x1b21 by macro PCI_VENDOR_ID_ASMEDIA with the same value.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Prevent access to arbitrary memory locations in gen_ndis_set_resp
via manipulation of buf->InformationBufferOffset. Original
implementation permits manipulation of InformationBufferOffset to
exploit OID_GEN_CURRENT_PACKET_FILTER to set arbitrary memory contents
within a 32byte offset as the devices packet filter. The packet filter
value may be next retrieved using gen_ndis_query_resp so it is possible
to extract specific memory regions two bytes a time.
The rndis_query_response was not modified as neither the buffer offset
nor length passed to gen_ndis_query_resp is used.
Signed-off-by: Szymon Heidrich <szymon.heidrich@gmail.com>
Commit fbce985e28 to fix CVE-2022-2347
blocks DFU usb requests.
The verification of the transfer direction was done by an equality
but it is a bit mask.
Signed-off-by: Hugo SIMELIERE <hsimeliere.opensource@witekio.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Sultan Qasim Khan <sultan.qasimkhan@nccgroup.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
As there are no more non-DM_ETH cases for networking, remove this legacy
file and update the Makefile to match current usage.
Signed-off-by: Tom Rini <trini@konsulko.com>
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code fro usb_ether itself.
Signed-off-by: Tom Rini <trini@konsulko.com>
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code. Doing this removes some board support code
which was also unused. Finally, this removes some CONFIG symbols that
otherwise needed to be migrated to Kconfig, but were unused in code now.
Signed-off-by: Tom Rini <trini@konsulko.com>
Add support of generic IIO channels binding:
./devicetree/bindings/iio/adc/adc.yaml
Keep support of st,adc-channels for backward compatibility.
Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Split stm32_adc_chan_of_init channel initialization function into
several routines to increase readability and prepare channel
generic binding handling.
Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
STM32MP13 RCC driver uses Common Clock Framework and also a
'clk-stm32-core' API. Then STM32MPx RCC driver will contain only data
configuration (gates, mux, dividers and the way to check security)
or some specific clocks.
This API will be used by all new other generations of ST Socs.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
We move the existing CONFIG_POST_* functionality over to CFG_POST and
then introduce CONFIG_POST to Kconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Given that we can use Kconfig logic directly to see if we have a program
available on the host or not, change from passing NO_SDL to instead
controlling CONFIG_SANDBOX_SDL in Kconfig directly. Introduce
CONFIG_HOST_HAS_SDL as the way to test for sdl2-config and default
CONFIG_SANDBOX_SDL on if we have that, or not.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At this point all users of this driver enable DM_ETH, so remove the
legacy code paths.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
This converts the following to Kconfig:
CONFIG_RTC_DS1337
CONFIG_RTC_DS1337_NOOSC
CONFIG_RTC_DS1338
CONFIG_RTC_DS1374
CONFIG_RTC_DS3231
CONFIG_RTC_MC13XXX
CONFIG_RTC_MXS
CONFIG_RTC_PT7C4338
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_POWER_FSL
CONFIG_POWER_FSL_MC13892
CONFIG_POWER_HI6553
CONFIG_POWER_LTC3676
CONFIG_POWER_PFUZE100
CONFIG_POWER_PFUZE3000
CONFIG_POWER_SPI
CONFIG_POWER_TPS65090_EC
CONFIG_POWER_TPS65218
CONFIG_POWER_TPS65910
Signed-off-by: Tom Rini <trini@konsulko.com>
As we have more legacy PMIC drivers to move to Kconfig, guard them all
with POWER_LEGACY or SPL_POWER_LEGACY. Do the same kind of check for
building the drivers too. This also means that we need to resort the
list slightly in the Makefile.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and
CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many
cases they likely should come from the device tree instead. Move these
out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
These RTC drivers are currently unused and reference other unused CONFIG
variables, so remove them.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_SPL_NS16550_MIN_FUNCTIONS
CONFIG_SYS_NS16550_MEM32
CONFIG_SYS_NS16550_PORT_MAPPED
CONFIG_SYS_NS16550_REG_SIZE
CONFIG_SYS_NS16550_SERIAL
To do this we also introduce CONFIG_SPL_SYS_NS16550_SERIAL so that
platforms can enable the legacy driver here for SPL.
Signed-off-by: Tom Rini <trini@konsulko.com>
This symbol is specific to the PowerPC SPL implementation, so rename
this to reflect that it's in SPL and used / tested there, so that we can
then safely migrate it to Kconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_SYS_NAND_PAGE_2K
CONFIG_SYS_NAND_PAGE_4K
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_SYS_NAND_MAX_OOBFREE
CONFIG_SYS_NAND_MAX_ECCPOS
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is the only driver, and only one platform makes use of, setting
CONFIG_SYS_NAND_ECC_BASE. Reference ATMEL_BASE_ECC directly in this
case.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_SYS_NAND_HW_ECC
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_SYS_NAND_HW_ECC_OOBFIRST
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_SYS_NAND_DBW_8
CONFIG_SYS_NAND_DBW_16
Note that all instances of the code check for CONFIG_SYS_NAND_DBW_16
being defined, and then "else" to CONFIG_SYS_NAND_DBW_8 whereas all of
the configs set CONFIG_SYS_NAND_DBW_8. So we introduce
CONFIG_SYS_NAND_DBW_16 as an option.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Consider unexpected values for frequency:
* negative frequency
* zero frequency
* frequency exceeding sampling frequency
As in these cases the sum of the samples is zero also check the count of
the samples.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
'sound play 1 100000' results in an endless loop on the sandbox.
If the frequency exceeds half the sampling rate, zero out the output
buffer.
Fixes: 511ed5fdd3 ("SOUND: SAMSUNG: Add I2S driver")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
xilinx:
- Fix MAC address selection for System Controller from FRU
- Cleanup Kconfig (ZYNQ_MAC_IN_EEPROM symbol)
versal:
- Create u-boot.elf for mini spi configurations
versal-net:
- Enable MT35XU flash
zynq:
- Add missing timer to DT for mini configurations
zynqmp:
- Do not include psu_init to U-Boot by default
- Do not enable IPI by default to mini U-Boot
- Update Luca's fragment
- Fix SPL_FS_LOAD_PAYLOAD_NAME usage
spi:
- gqspi: Fix tapdelay values
- gqspi: Fix 64bit address support
- cadence: Remove condition for calling enable linear mode
- nor-core: Invert logic to reflect sst26 flash unlocked
net:
- Add PCS/PMA phy support
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Merge tag 'xilinx-for-v2023.01-rc3-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2023.01-rc3-v2
xilinx:
- Fix MAC address selection for System Controller from FRU
- Cleanup Kconfig (ZYNQ_MAC_IN_EEPROM symbol)
versal:
- Create u-boot.elf for mini spi configurations
versal-net:
- Enable MT35XU flash
zynq:
- Add missing timer to DT for mini configurations
zynqmp:
- Do not include psu_init to U-Boot by default
- Do not enable IPI by default to mini U-Boot
- Update Luca's fragment
- Fix SPL_FS_LOAD_PAYLOAD_NAME usage
spi:
- gqspi: Fix tapdelay values
- gqspi: Fix 64bit address support
- cadence: Remove condition for calling enable linear mode
- nor-core: Invert logic to reflect sst26 flash unlocked
net:
- Add PCS/PMA phy support
flash_is_locked is changed to flash_is_unlocked with commit 513c6071ce
("mtd: spi: Convert is_locked callback to is_unlocked"). sst26_is_locked()
is also changed to sst26_is_unlocked() but the logic remained same.
Invert the logic for the flash lock/unlock to work properly.
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20221122051833.13306-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
cadence_qspi_apb_enable_linear_mode() has a weak function defined, so no
need to gaurd this under if (CONFIG_IS_ENABLED(ARCH_VERSAL)).
In cadence_qspi_apb_write_execute(), enable linear mode is called twice by
mistake, remove extra one.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20221129114134.18909-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
When we pass the 64-bit address to read/write, only lower 32-bit
address is getting updated. Program the upper 32-bit address in the
DMA destination memory address MSBs register, which can handle upto
44-bit destination address.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221125104413.26140-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
The driver was using an incorrect value for GQSPI_LPBK_DLY_ADJ_DLY_1
tapdelay for Versal for frequencies above 100MHz. Change it from 2 to 1
based on the recommended value in IP spec.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20221123090451.11409-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Both PCS/PMA PHY and the external PHY need to have a valid link status
in order to have Ethernet traffic. Check and wait this status at
setup_phy() so that we could diagnose if there is a PHY issue.
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
Link: https://lore.kernel.org/r/20221101035800.912644-3-andy.chiu@sifive.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
If we bridge an external PHY to Xilinx's PCS/PMA PHY and would like to
get and set the real status of the PHY facing the external world. Then
we should phy_connect() to the external PHY instead of the PCS/PMA one.
Thus, we add a pcs-handle DT entry, which have been merged in Linux, and
leave the configuration of it to the driver itself.
Unlike Linux, where the PCS/PMA PHY is managed by phylink, managing the
PCS/PMA PHY is only internal to the driver in U-Boot. The PCS/PMA PHY
pressents only when the phy-mode is configured as SGMII or 1000Base-X,
so it is always 1 Gbps and full-duplex and we may skip passing link
information out.
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
Link: https://lore.kernel.org/r/20221101035800.912644-2-andy.chiu@sifive.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
The TI sysc bus driver is required to allow access to the SPI bus on
am335x platforms. To support SPI boot this driver needs to be enabled in
the SPL/TPL as appropriate.
Signed-off-by: Paul Barker <paul.barker@sancloud.com>
We should only perform additional iteration steps when needed to
initialize the parent of a device. Other binding errors (such as a
missing driver) should not lead to additional iteration steps.
Unnecessary iteration steps can cause issues when memory is tightly
constrained (such as in the TPL/SPL) since device_bind_by_name()
unconditionally allocates memory for a struct udevice. On the SanCloud
BBE this led to boot failure caused by memory exhaustion in the SPL
when booting from SPI flash.
Signed-off-by: Paul Barker <paul.barker@sancloud.com>
Add a driver for the Intel XWAY GbE PHY:
- configure RGMII using dt phy-mode and standard delay properties
- use genphy_config
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The rx descriptor list is in cached memory, and there may be multiple
descriptors per cache-line. After reclaim_rx_buffers marks a descriptor
as unused it does a cache flush, which causes the entire cache-line to
be written to memory, which may override other descriptors in the same
cache-line that the controller may have written to.
The fix skips freeing descriptors that are not the last in a cache-line,
and if the freed descriptor is the last one in a cache-line, it marks
all the descriptors in the cache-line as unused.
This is similarly to what is done in drivers/net/fec_mxc.c
In my case this bug caused tftpboot to fail some times when other
packets are sent to u-boot in addition to the ongoing tftp (e.g. ping).
The driver would stop receiving new packets because it is waiting
on a descriptor that is marked unused, when in reality the descriptor
contains a new unprocessed packet but while freeing the previous buffer
descriptor & flushing the cache, the driver accidentally marked the
descriptor as unused.
Signed-off-by: Yaron Micher <yaronm@hailo.ai>
Fix a couple of typos:
- s/Acquantia/Aquantia/
- s/firmare/firmware/
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Add new desc_per_cacheline property which lets a platform run RX descriptor
cleanup after every power-of-2 - 1 received packets instead of every packet.
This is useful on platforms where (axi_bus_width EQOS_AXI_WIDTH_n * DMA DSL
inter-descriptor word skip count + DMA descriptor size) is less than cache
line size, which necessitates packing multiple DMA descriptors into single
cache line.
In case of TX descriptors, this is not a problem, since the driver always
does synchronous TX, i.e. the TX descriptor is always written, flushed and
polled for completion in eqos_send().
In case of RX descriptors, it is necessary to update their status in bulk,
i.e. after the entire cache line worth of RX descriptors has been used up
to receive data.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Separate TX and RX DMA rings to make their handling slightly clearer.
This is a preparatory patch for bulk RX descriptor flushing.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic
network device that is commonly used in LiteX designs.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Drop support for quickly deprecated DT property "snps,ref-clock-period-ns"
to prevent its proliferation.
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
GUCTL.REFCLKPER can only account for clock frequencies with integer
periods. To address this, program REFCLK_FLADJ with the relative error
caused by period truncation. The formula given in the register reference
has been rearranged to allow calculation based on rate (instead of
period), and to allow for fixed-point arithmetic.
Additionally, calculate a value for 240MHZDECR. This configures a
simulated 240Mhz clock using a counter with one fractional bit (PLS1).
This register is programmed only for versions >= 2.50a, since this is
the check also used by commit db2be4e9e30c ("usb: dwc3: Add frame length
adjustment quirk").
[ marek: Ported from Linux kernel commit
596c87856e08d ("usb: dwc3: Program GFLADJ") ]
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
Instead of using a special property to determine the reference clock
period, use the rate of the reference clock. When we have a legacy
snps,ref-clock-period-ns property and no reference clock, use it
instead. Fractional clocks are not currently supported, and will be
dealt with in the next commit.
[ marek: Ported from Linux kernel commit
5114c3ee24875 ("usb: dwc3: Calculate REFCLKPER based on reference clock") ]
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
Set reference clock period when it differs from dwc3 default hardware
set.
We could calculate clock period based on reference clock frequency. But
this information is not always available. This is the case of PCI bus
attached USB host. For that reason we use a custom property.
Tested (USB2 only) on IPQ6010 SoC based board with 24 MHz reference
clock while hardware default is 19.2 MHz.
[ baruch: rewrite commit message; drop GFLADJ code; remove 'quirk-' from
property name; mention tested hardware ]
[ marek: Ported from Linux kernel commit
7bee318838890 ("usb: dwc3: reference clock period configuration") ]
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
Cache ref_clk clock pointer in struct dwc3 . This is a preparatory
patch for subsequent backports from Linux kernel which configure
GFLADJ register content based on the ref_clk rate and therefore need
access to the ref_clk pointer.
It is possible to extract the clock pointer from existing clk_bulk
list of already claimed clock, no need to call clk_get*() again.
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
The "generic_bus_%x_dev_%x" string which is printed into this buffer
can be up to 34 characters long ("generic_bus_12345678_dev_12345678").
The buffer would be clipped by snprintf() if both %x were at maximum
range. Make sure the buffer is long enough to cover such possibility.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use macro to represent the RL and WL setting to ensure the PHY and
controller setting are aligned.
Review-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Adjust the following settings to get better timing and signal quality.
1. write DQS/DQ delay
- 1e6e2304[0]
- 1e6e2304[15:8]
2. read DQS/DQ delay
- 0x1e6e0298[0]
- 0x1e6e0298[15:8]
3. CLK/CA timing
- 0x1e6e01a8[31]
4. Read and write termination
- change RTT_ROM from 40 ohm to 48 ohm (MR1[10:8])
- change RTT_PARK from disable to 48 ohm (MR5[8:6])
- change RTT_WR from 120 ohm to disable (MR2[11:9])
- change PHY ODT from 40 ohm to 80 ohm (0x1e6e0130[10:8])
Note1: Both DDR-PHY and DDR controller have their own registers for DDR4
Mode Registers (MR0~MR6). This patch introduces macros to synchronize
the MR value on both sides.
Note2: the waveform meansurement can be found in item #21 of Aspeed
AST26x0 Application note (AP note).
Review-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
The condition "~data" in the if-statement is a typo. The original
intention is to poll if SDRAM_PHYCTRL0_INIT bit equals to 0. So use
"data == 0" for instead.
Besides, the bit[1] of "phy_status" register is hardwired to
SDRAM_PHYCTRL0_INIT (with inverse logic). Since SDRAM_PHYCTRL0_INIT has
already done, remove the unnecessary checking of phy_status[1].
Fixes: fde9314346 ("ram: aspeed: Add AST2600 DRAM control support")
Review-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
- Re-add the old PHY reset binding for nanopi-k2
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Merge tag 'u-boot-amlogic-20221122' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- Implement setbrg op to meson serial device
- Re-add the old PHY reset binding for nanopi-k2
Invoking lseek() may result in an error. Handle it.
Addresses-Coverity-ID: 376212 ("Error handling issues (CHECKED_RETURN)")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Implement setbrg in amlogic/meson serial device with driver model
similar to how the meson_uart.c driver does it in Linux. Also
configure (probe) the serial device with the new reg5 register.
Signed-off-by: Edoardo Tomelleri <e.tomell@gmail.com>
Link: https://lore.kernel.org/r/20220918161701.572814-1-e.tomell@gmail.com
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
When cadence_qspi_versal_flash_reset() function is called in mini
u-boot where there is no firmware support, it is missing defines for
macro's BOOT_MODE_POR_0 & BOOT_MODE_POR_1. Remove them and replace with
already define macro's which have same values as these.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20221116141155.14788-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add soc_xilinx_versal_net driver to identify the family & revision of
versal-net SoC. Add Kconfig option CONFIG_SOC_XILINX_VERSAL_NET to
enable/disable this driver. To enable this driver by default, add this
config to xilinx_versal_net_virt_defconfig file. This driver will be
probed using platdata U_BOOT_DEVICE structure which is specified in
mach-versal-net/cpu.c.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/613d6bcffd9070f62cf348079ed16c120f8fc56f.1668612993.git.michal.simek@amd.com
Use dot instead of comma. The fix doesn't affect anything but it is good to
be aligned with used pattern. The first is used only for string size
calculation and the second change is in the comment.
Fixes: db681d4929 ("net: phy: Add new read ethernet phy id function")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Current xilinx_timer_get_count() implementation does not take into account
the periodic 32-bit wrap arounds, as it directly returns the 32-bit counter
register value. The roll-overs cause problems in the upper timer layers, as
generic timer code expects an incrementing 64-bit value from get_count() to
work correctly.
Add the missing 64-bit up-conversion to fix random hangs/delays in
__udelay().
Fixes: a36d86720f ("microblaze: Convert axi timer to DM driver")
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221012053656.1492457-3-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Relocate timer_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled.
The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done
logic works for drivers that use DM_FLAG_PRE_RELOC.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20221012053656.1492457-2-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Align timer uclass with the other subsystems and provide a timer_get_ops()
convenience macro.
Using this instead of the generic device_get_ops() also prevents
-Wdiscarded-qualifiers warnings when used with non-const variables.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20221012053656.1492457-1-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Removing the zynq_board_read_rom_ethaddr() function as
xlnx,eeprom is not used anymore. As all board dts to use
nvmem alias instead of xlnx,eeprom.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221017094818.17996-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Since commit c2fd0ca1a8
("watchdog: Integrate watchdog triggering into the cyclic framework")
GD_FLG_WDT_READY has become write-only. This patch now removes this
flag completely.
The vacant spot in gd_flags is filled with the newly introduced
GD_FLG_CYCLIC_RUNNING flag.
Suggested-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Stefan Roese <sr@denx.de>
Checking for DM_RESET is not enough since not all watchdog
implementations use a reset lane. Such is the case for Rockchip
implementation for example. Since reset_assert_bulk will only succeed if
the resets property exists in the watchdog DT node, it needs to be
called only if a reset property is present.
This adds a condition on the resets property presence in the watchdog DT
node before assuming a reset lane needs to be fetched with
reset_assert_bulk, by calling ofnode_read_prop.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
DFU implementation does not bound the length field in USB
DFU download setup packets, and it does not verify that
the transfer direction. Fixing the length and transfer
direction.
CVE-2022-2347
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Sync the critical clocks in the U-Boot driver with those marked as
critical in Linux. The Linux driver has an explanation of why each clock
is considered to be critical, so import that too.
Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Not all "periph" clocks are children of the AHB clock, some have the AXI
clock as their parent & the mtimer clock is derived from the external
reference clock directly. Stop assuming the AHB clock to be the parent
of all "periph" clocks and define their correct parents instead.
Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
The original devicetrees for PolarFire SoC messed up & defined the
msspll's output as a fixed-frequency, 600 MHz clock & used that as the
input for the clock controller node. The msspll is not a fixed
frequency clock and later devicetrees handled this properly. Check the
devicetree & if it is one of the fixed ones, register the msspll.
Otherwise, skip registering it & pass the reference clock directly to
the cfg clock registration function so that existing devicetrees are
not broken by this change.
As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for
it, based on the one in Linux.
Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
Currently the clock driver for PolarFire SoC takes a very naive approach
to the relationship between clocks. It reads the dt to get an input
clock, assumes that that is fixed frequency, reads the "clock-frequency"
property & uses that to set up both the "cfg" and "periph" clocks.
Simplifying for the sake of incremental fixes, the "correct" parentage for
the clocks currently supported in U-Boot is that the "cfg" clocks should
be children of the fixed frequency clock in the dt. The AHB clock is one
of these "cfg" clocks and is the parent of the "periph" clocks.
Instead of passing the clock rate of the fixed-frequency clock to the
"cfg" and "periph" registration functions and the name of the parents,
pass their actual parents & use clk_get_rate() to determine their parents
rates.
The "periph" clocks are purely gate clocks and should not be reading the
AHB clocks registers to determine their rates, as they can simply report
the output of clk_get_rate() on their parent.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Add newline at the end of the printed string.
Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
A late ack is currently being sent at the end of a transfer due to
incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack
bit is being written to the controller's control reg after the last
byte has been received, causing it to sent another byte with the ack.
Instead, the AA flag should be written to the control register when
the penultimate byte is read so it is sent out for the last byte.
Reported-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Fixes: 0dc0d1e094 ("i2c: Add Microchip PolarFire SoC I2C driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Removed Tag by hs: Fixes: 0190d48488 ("i2c: microchip: fix ack sending logic")
"Master receive mode" was not correctly sending ACKs/NACKs in the
interrupt handler. Bring the handling of M_SLAR_ACK, M_RX_DATA_ACKED &
M_RX_DATA_NACKED in line with the Linux driver.
Fixes: 0dc0d1e094 ("i2c: Add Microchip PolarFire SoC I2C driver")
Reported-by: Shravan Chippa <shravan.chippa@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This reverts commit c7878a0483.
Since commit c7878a0483 ("serial: mxc: have putc use the TXFIFO"),
serial console corruption can be seen when priting inside board_init().
Revert it to avoid the regression.
Reported-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
This converts the following to Kconfig:
CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
These files reference SZ_ macros without including <linux/sizes.h>,
correct this.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This converts the following to Kconfig:
CONFIG_SYS_MMC_MAX_BLK_COUNT
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This converts the following to Kconfig:
CONFIG_SYS_MAX_NAND_DEVICE
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
