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Convert CONFIG_SYS_MAX_NAND_DEVICE to Kconfig

Browse source 
This converts the following to Kconfig:
   CONFIG_SYS_MAX_NAND_DEVICE

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini 2022-10-28 20:27:04 -04:00
parent e28e0f47f3
commit a918df21f0
116 changed files with 7 additions and 145 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
configs/CHIP_pro_defconfig
View file

@ -19,6 +19,7 @@ CONFIG_SYS_I2C_SPEED=400000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_MAX_NAND_DEVICE=8
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_SIZE=0x1000

1
configs/Nintendo_NES_Classic_Edition_defconfig
View file

@ -14,6 +14,7 @@ CONFIG_CMD_MTDPARTS=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_MAX_NAND_DEVICE=8
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_SIZE=0x800

1
configs/etamin_defconfig
View file

@ -98,6 +98,7 @@ CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_CONCAT=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_MAX_NAND_DEVICE=3
CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y

3
doc/README.nand
View file

@ -99,9 +99,6 @@ Configuration Options:
CONFIG_CMD_NAND_TORTURE
Enables the torture command (see description of this command below).
CONFIG_SYS_MAX_NAND_DEVICE
The maximum number of NAND devices you want to support.
CONFIG_SYS_NAND_MAX_ECCPOS
If specified, overrides the maximum number of ECC bytes
supported. Useful for reducing image size, especially with SPL.

4
drivers/mtd/nand/raw/Kconfig
View file

@ -26,6 +26,10 @@ config TPL_SYS_NAND_SELF_INIT
config TPL_NAND_INIT
bool
config SYS_MAX_NAND_DEVICE
int "Maximum number of NAND devices to support"
default 1
config SYS_NAND_DRIVER_ECC_LAYOUT
bool "Omit standard ECC layouts to save space"
help

1
include/configs/M5329EVB.h
View file

@ -95,7 +95,6 @@
#endif
#ifdef CONFIG_CMD_NAND
# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }

1
include/configs/M5373EVB.h
View file

@ -96,7 +96,6 @@
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }

1
include/configs/MCR3000.h
View file

@ -83,7 +83,6 @@
/* Ethernet configuration part */
/* NAND configuration part */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x0C000000
#endif /* __CONFIG_H */

1
include/configs/P1010RDB.h
View file

@ -202,7 +202,6 @@ extern unsigned long get_sdram_size(void);
#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_TARGET_P1010RDB_PA)
/* NAND Flash Timing Params */

1
include/configs/P2041RDB.h
View file

@ -119,7 +119,6 @@
#endif
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \

1
include/configs/T102xRDB.h
View file

@ -236,7 +236,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT

1
include/configs/T104xRDB.h
View file

@ -212,7 +212,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT

1
include/configs/T208xQDS.h
View file

@ -200,7 +200,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT

1
include/configs/T208xRDB.h
View file

@ -176,7 +176,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT

1
include/configs/T4240RDB.h
View file

@ -235,7 +235,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT

1
include/configs/at91sam9260ek.h
View file

@ -43,7 +43,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)

1
include/configs/at91sam9261ek.h
View file

@ -24,7 +24,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD22 */

1
include/configs/at91sam9263ek.h
View file

@ -152,7 +152,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */

1
include/configs/at91sam9m10g45ek.h
View file

@ -20,7 +20,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */

1
include/configs/at91sam9n12ek.h
View file

@ -21,7 +21,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)

1
include/configs/at91sam9rlek.h
View file

@ -25,7 +25,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */

1
include/configs/at91sam9x5ek.h
View file

@ -27,7 +27,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */

4
include/configs/bcm963158.h
View file

@ -8,8 +8,4 @@
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif /* CONFIG_MTD_RAW_NAND */
#endif

4
include/configs/bcm96855.h
View file

@ -8,8 +8,4 @@
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif /* CONFIG_MTD_RAW_NAND */
#endif

4
include/configs/bcm96856.h
View file

@ -8,8 +8,4 @@
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif /* CONFIG_MTD_RAW_NAND */
#endif

4
include/configs/bcm96858.h
View file

@ -8,8 +8,4 @@
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif /* CONFIG_MTD_RAW_NAND */
#endif

1
include/configs/bk4r1.h
View file

@ -51,7 +51,6 @@
#include <linux/sizes.h>
/* NAND support */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define IMX_FEC1_BASE ENET1_BASE_ADDR

3
include/configs/broadcom_bcm968380gerg.h
View file

@ -6,6 +6,3 @@
#include <configs/bmips_common.h>
#include <configs/bmips_bcm6838.h>
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif /* CONFIG_MTD_RAW_NAND */

1
include/configs/cm_fx6.h
View file

@ -129,7 +129,6 @@
/* NAND */
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* APBH DMA is required for NAND support */
/* Ethernet */

1
include/configs/colibri-imx6ull.h
View file

@ -122,7 +122,6 @@
#ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */
#define CONFIG_SYS_NAND_BASE -1
#endif

1
include/configs/colibri_imx7.h
View file

@ -166,7 +166,6 @@
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
#endif

1
include/configs/colibri_t20.h
View file

@ -16,7 +16,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* NAND support */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define UBOOT_UPDATE \
"update_uboot=nand erase.part u-boot && " \

1
include/configs/colibri_vf.h
View file

@ -15,7 +15,6 @@
#include <linux/sizes.h>
/* NAND support */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0

3
include/configs/comtrend_vr3032u.h
View file

@ -6,6 +6,3 @@
#include <configs/bmips_common.h>
#include <configs/bmips_bcm63268.h>
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif /* CONFIG_MTD_RAW_NAND */

1
include/configs/corvus.h
View file

@ -37,7 +37,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */

1
include/configs/da850evm.h
View file

@ -114,7 +114,6 @@
#define CONFIG_SYS_NAND_MASK_CLE 0x10
#define CONFIG_SYS_NAND_MASK_ALE 0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000

1
include/configs/devkit3250.h
View file

@ -36,7 +36,6 @@
* NAND controller
*/
#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
/*

2
include/configs/etamin.h
View file

@ -45,8 +45,6 @@
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 26
#undef CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_MAX_NAND_DEVICE 3
#define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
CONFIG_SYS_NAND_BASE2}

1
include/configs/ethernut5.h
View file

@ -37,7 +37,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */

1
include/configs/gardena-smart-gateway-at91sam.h
View file

@ -22,7 +22,6 @@
#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
/* NAND flash */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */

1
include/configs/gw_ventana.h
View file

@ -20,7 +20,6 @@
#define CONFIG_MXC_UART_BASE UART2_BASE
/* NAND */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0

1
include/configs/harmony.h
View file

@ -24,7 +24,6 @@
#endif
/* NAND support */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND (which is 512M), aligned to start of last sector */

1
include/configs/imx27lite-common.h
View file

@ -97,7 +97,6 @@
* NAND
*/
#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0xd8000000
#define CONFIG_MXC_NAND_HWECC

1
include/configs/imx6-engicam.h
View file

@ -126,7 +126,6 @@
/* NAND */
#ifdef CONFIG_NAND_MXS
# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_BASE 0x40000000
# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE

1
include/configs/imx6_logic.h
View file

@ -116,7 +116,6 @@
/* Environment organization */
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE

1
include/configs/imx6ulz_smm_m2.h
View file

@ -71,7 +71,6 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x20000000

1
include/configs/imx8mn_bsh_smm_s2.h
View file

@ -43,7 +43,6 @@
#define PHYS_SDRAM_SIZE SZ_256M
/* NAND */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x20000000

1
include/configs/imx8mp_rsb3720.h
View file

@ -171,7 +171,6 @@
#ifdef CONFIG_NAND_MXS
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x20000000
#endif /* CONFIG_NAND_MXS */

1
include/configs/km/km-mpc83xx.h
View file

@ -60,7 +60,6 @@
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_KMETER1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
#endif

1
include/configs/km/pg-wcom-ls102xa.h
View file

@ -119,7 +119,6 @@
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
/* QRIO FPGA Definitions */

1
include/configs/kmcent2.h
View file

@ -277,7 +277,6 @@
/* More NAND Flash Params */
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* QRIO on IFC CS2 */
#define CONFIG_SYS_QRIO_BASE 0xfb000000

1
include/configs/kmcoge5ne.h
View file

@ -11,7 +11,6 @@
#define CONFIG_HOSTNAME "kmcoge5ne"
#define CONFIG_NAND_ECC_BCH
#define CONFIG_NAND_KMETER1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */

1
include/configs/ls1021aqds.h
View file

@ -107,7 +107,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif
/*

1
include/configs/ls1043aqds.h
View file

@ -111,7 +111,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#endif

1
include/configs/ls1043ardb.h
View file

@ -82,7 +82,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#ifdef CONFIG_NAND_BOOT

1
include/configs/ls1046afrwy.h
View file

@ -45,7 +45,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
/* IFC Timing Params */

1
include/configs/ls1046aqds.h
View file

@ -127,7 +127,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#endif

1
include/configs/ls1046ardb.h
View file

@ -50,7 +50,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
/*

1
include/configs/ls1088aqds.h
View file

@ -102,7 +102,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66

1
include/configs/ls1088ardb.h
View file

@ -86,7 +86,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66

1
include/configs/ls2080aqds.h
View file

@ -103,7 +103,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define QIXIS_LBMAP_SWITCH 0x06

1
include/configs/ls2080ardb.h
View file

@ -100,7 +100,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define QIXIS_LBMAP_SWITCH 0x06

1
include/configs/m53menlo.h
View file

@ -44,7 +44,6 @@
* NAND
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR

1
include/configs/medcom-wide.h
View file

@ -19,7 +19,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND, aligned to start of last sector */

1
include/configs/meesc.h
View file

@ -52,7 +52,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
# define CONFIG_SYS_NAND_DBW_8
# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)

1
include/configs/mt7621.h
View file

@ -21,7 +21,6 @@
#define MMC_SUPPORTS_TUNING
/* NAND */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)

3
include/configs/mv-common.h
View file

@ -61,8 +61,5 @@
/*
* Common NAND configuration
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif
#endif /* _MV_COMMON_H */

2
include/configs/mvebu_armada-8k.h
View file

@ -25,8 +25,6 @@
/* When runtime detection fails this is the default */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* USB ethernet */
/*

1
include/configs/mx6sabreauto.h
View file

@ -36,7 +36,6 @@
#define CONFIG_SYS_FSL_USDHC_NUM 2
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* DMA stuff, needed for GPMI/MXS NAND support */

1
include/configs/mx6sxsabreauto.h
View file

@ -86,7 +86,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* DMA stuff, needed for GPMI/MXS NAND support */

1
include/configs/mx7dsabresd.h
View file

@ -93,7 +93,6 @@
*/
#ifdef CONFIG_NAND_MXS
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* DMA stuff, needed for GPMI/MXS NAND support */

1
include/configs/mxs.h
View file

@ -83,7 +83,6 @@
/* NAND */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x60000000
#endif

1
include/configs/mys_6ulx.h
View file

@ -30,7 +30,6 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* USB Configs */

1
include/configs/npi_imx6ull.h
View file

@ -31,7 +31,6 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* USB Configs */

4
include/configs/octeontx_common.h
View file

@ -46,8 +46,4 @@
/** EMMC specific defines */
#if defined(CONFIG_NAND_OCTEONTX)
#define CONFIG_SYS_MAX_NAND_DEVICE 8
#endif
#endif /* __OCTEONTX_COMMON_H__ */

1
include/configs/omap3_beagle.h
View file

@ -21,7 +21,6 @@
/* NAND */
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512

1
include/configs/omap3_evm.h
View file

@ -26,7 +26,6 @@
/* NAND */
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512

1
include/configs/omap3_logic.h
View file

@ -16,7 +16,6 @@
/* Board NAND Info. */
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
13, 14, 16, 17, 18, 19, 20, 21, 22, \

1
include/configs/omapl138_lcdk.h
View file

@ -112,7 +112,6 @@
#define CONFIG_SYS_NAND_MASK_CLE 0x10
#define CONFIG_SYS_NAND_MASK_ALE 0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K

1
include/configs/p1_p2_rdb_pc.h
View file

@ -215,7 +215,6 @@
#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \

1
include/configs/pcl063.h
View file

@ -42,7 +42,6 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* USB Configs */

1
include/configs/pcl063_ull.h
View file

@ -44,7 +44,6 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* USB Configs */

2
include/configs/pcm052.h
View file

@ -14,8 +14,6 @@
/* NAND support */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* if no target-specific extra environment settings were defined by the
target, define an empty one */
#ifndef PCM052_EXTRA_ENV_SETTINGS

1
include/configs/pcm058.h
View file

@ -15,7 +15,6 @@
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
/* Enable NAND support */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR

1
include/configs/plutux.h
View file

@ -19,7 +19,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND, aligned to start of last sector */

1
include/configs/pm9261.h
View file

@ -129,7 +129,6 @@
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
/* NAND flash */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD22 */

1
include/configs/pm9263.h
View file

@ -146,7 +146,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */

1
include/configs/pm9g45.h
View file

@ -25,7 +25,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */

1
include/configs/presidio_asic.h
View file

@ -58,7 +58,6 @@
/* nand driver parameters */
#ifdef CONFIG_TARGET_PRESIDIO_ASIC
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#endif

1
include/configs/sam9x60ek.h
View file

@ -28,7 +28,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
#define CONFIG_SYS_NAND_MASK_CLE BIT(22)

1
include/configs/sama5d2_ptc_ek.h
View file

@ -21,7 +21,6 @@
/* NAND Flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)

1
include/configs/sama5d3_xplained.h
View file

@ -29,7 +29,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x60000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)

1
include/configs/sama5d3xek.h
View file

@ -38,7 +38,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x60000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)

1
include/configs/sama5d4_xplained.h
View file

@ -17,7 +17,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x80000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)

1
include/configs/sama5d4ek.h
View file

@ -17,7 +17,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x80000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)

1
include/configs/seaboard.h
View file

@ -29,7 +29,6 @@
/* NAND support */
/* Max number of NAND devices */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#include "tegra-common-post.h"

2
include/configs/siemens-am33x-common.h
View file

@ -368,8 +368,6 @@
#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
/* to access nand at */
/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND
devices */
#endif
#endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */

1
include/configs/smartweb.h
View file

@ -54,7 +54,6 @@
*/
/* NAND flash settings */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)

1
include/configs/snapper9g45.h
View file

@ -30,7 +30,6 @@
/* NAND Flash */
#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */

1
include/configs/socfpga_common.h
View file

@ -80,7 +80,6 @@
* NAND Support
*/
#ifdef CONFIG_NAND_DENALI
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif

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