Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-09-23 08:01:59 +00:00
Code Issues Projects Releases Packages Wiki Activity

Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig

Browse source 
This converts the following to Kconfig:
   CONFIG_SYS_NAND_DBW_8
   CONFIG_SYS_NAND_DBW_16

Note that all instances of the code check for CONFIG_SYS_NAND_DBW_16
being defined, and then "else" to CONFIG_SYS_NAND_DBW_8 whereas all of
the configs set CONFIG_SYS_NAND_DBW_8. So we introduce
CONFIG_SYS_NAND_DBW_16 as an option.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini 2022-11-12 17:36:42 -05:00
parent 1c470f32f7
commit 715cce65b8
17 changed files with 12 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
drivers/mtd/nand/raw/Kconfig
View file

@ -83,6 +83,18 @@ config SPL_GENERATE_ATMEL_PMECC_HEADER
help
Generate Programmable Multibit ECC (PMECC) header for SPL image.
choice
prompt "NAND bus width (bits)"
default SYS_NAND_DBW_8
config SYS_NAND_DBW_8
bool "NAND bus width is 8 bits"
config SYS_NAND_DBW_16
bool "NAND bus width is 16 bits"
endchoice
endif
config NAND_BRCMNAND

1
include/configs/at91sam9260ek.h
View file

@ -44,7 +44,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14

1
include/configs/at91sam9261ek.h
View file

@ -25,7 +25,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD22 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */

1
include/configs/at91sam9263ek.h
View file

@ -151,7 +151,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */

1
include/configs/at91sam9m10g45ek.h
View file

@ -21,7 +21,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */

1
include/configs/at91sam9rlek.h
View file

@ -26,7 +26,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */

1
include/configs/at91sam9x5ek.h
View file

@ -28,7 +28,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */

1
include/configs/corvus.h
View file

@ -38,7 +38,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */

1
include/configs/ethernut5.h
View file

@ -38,7 +38,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */

1
include/configs/gardena-smart-gateway-at91sam.h
View file

@ -23,7 +23,6 @@
/* NAND flash */
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
/* our CLE is AD22 */

1
include/configs/meesc.h
View file

@ -53,7 +53,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
# define CONFIG_SYS_NAND_DBW_8
# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)

1
include/configs/pm9261.h
View file

@ -130,7 +130,6 @@
/* NAND flash */
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD22 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */

1
include/configs/pm9263.h
View file

@ -147,7 +147,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */

1
include/configs/pm9g45.h
View file

@ -26,7 +26,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
/* our CLE is AD22 */

1
include/configs/smartweb.h
View file

@ -55,7 +55,6 @@
/* NAND flash settings */
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14

1
include/configs/snapper9g45.h
View file

@ -31,7 +31,6 @@
/* NAND Flash */
#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14

1
include/configs/taurus.h
View file

@ -55,7 +55,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14