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Convert CONFIG_SPD_EEPROM to Kconfig
This converts the following to Kconfig: CONFIG_SPD_EEPROM Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
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d91365203c
commit
8ce59b5932
9 changed files with 12 additions and 12 deletions
7
README
7
README
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@ -1683,13 +1683,6 @@ Low Level (hardware related) configuration options:
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Sets the EBC0_CFG register for the NDFC. If not defined
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a default value will be used.
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- CONFIG_SPD_EEPROM
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Get DDR timing information from an I2C EEPROM. Common
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with pluggable memory modules such as SODIMMs
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SPD_EEPROM_ADDRESS
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I2C address of the SPD EEPROM
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- CONFIG_SYS_SPD_BUS_NUM
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If SPD EEPROM is on an I2C bus other than the first
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one, specify here. Note that the value must resolve
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@ -45,6 +45,7 @@ CONFIG_USE_BOOTFILE=y
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CONFIG_BOOTFILE="8548cds/uImage.uboot"
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CONFIG_USE_ETHPRIME=y
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CONFIG_ETHPRIME="eTSEC0"
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CONFIG_SPD_EEPROM=y
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CONFIG_CHIP_SELECTS_PER_CTRL=2
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CONFIG_DDR_ECC=y
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CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
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@ -44,6 +44,7 @@ CONFIG_USE_BOOTFILE=y
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CONFIG_BOOTFILE="8548cds/uImage.uboot"
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CONFIG_USE_ETHPRIME=y
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CONFIG_ETHPRIME="eTSEC0"
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CONFIG_SPD_EEPROM=y
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CONFIG_CHIP_SELECTS_PER_CTRL=2
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CONFIG_DDR_ECC=y
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CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
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@ -44,6 +44,7 @@ CONFIG_USE_BOOTFILE=y
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CONFIG_BOOTFILE="8548cds/uImage.uboot"
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CONFIG_USE_ETHPRIME=y
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CONFIG_ETHPRIME="eTSEC0"
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CONFIG_SPD_EEPROM=y
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CONFIG_CHIP_SELECTS_PER_CTRL=2
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CONFIG_DDR_ECC=y
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CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
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@ -57,6 +57,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
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CONFIG_ENV_ADDR_REDUND=0xFFF20000
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CONFIG_USE_ETHPRIME=y
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CONFIG_ETHPRIME="TSEC0"
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CONFIG_SPD_EEPROM=y
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CONFIG_CHIP_SELECTS_PER_CTRL=2
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CONFIG_SYS_BR0_PRELIM_BOOL=y
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CONFIG_SYS_BR0_PRELIM=0xFE001001
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@ -37,3 +37,11 @@ config SYS_SPD_BUS_NUM
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source "drivers/ddr/altera/Kconfig"
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source "drivers/ddr/imx/Kconfig"
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config SPD_EEPROM
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bool "DDR controller makes use of an SPD EEPROM for JEDEC information"
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depends on SYS_FSL_DDR || SYS_FSL_MMDC || CONFIG_ARMADA_XP
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help
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Get DDR timing information from an I2C EEPROM. Common with pluggable
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memory modules such as SODIMMs. You must define SPD_EEPROM_ADDRESS
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to the I2C address of the SPD EEPROM.
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@ -30,7 +30,6 @@
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#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
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/* DDR Setup */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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@ -45,7 +45,4 @@
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/* SPL */
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/* Defines for SPL */
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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#define CONFIG_SPD_EEPROM 0x4e
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#endif /* _CONFIG_DB_MV7846MP_GP_H */
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@ -50,7 +50,6 @@
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#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
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/* DDR Setup */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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