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ram: k3-ddrss: add auto-generated macros for am62a support
The new 32bit DDR controller for TI's am62a family of SoCs shares much of the same functionality with the existing 16bit (am64) and 32bit (j721e) controllers, so this patch reorganizes the existing auto-generated macros for the 16bit and 32bit controllers to make room for the macros for the am62a's controller This patch consists mostly of header/macro renames and additions with a new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new macros during compilation. Signed-off-by: Bryan Brattlof <bb@ti.com>
This commit is contained in:
Bryan Brattlof
Tom Rini
parent
640aecb416
commit
ee31be429b
66 changed files with 30830 additions and 344 deletions
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@ -86,6 +86,16 @@ config K3_AM64_DDRSS
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Enabling this config adds support for the DDR memory controller
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on AM642 family of SoCs.
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config K3_AM62A_DDRSS
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bool "Enable AM62A DDRSS support"
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help
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The AM62A DDR subsystem comprises of a DDR controller, DDR PHY and
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wrapper logic to integrate these blocks into once device. The DDR
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subsystem is used to provide an interface to external SDRAM devices
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which can be utilized for storing programs or any other data.
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Enabling this option adds support for the DDR memory controller for
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the AM62A family of SoCs.
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endchoice
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config IMXRT_SDRAM
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@ -1,14 +0,0 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_16BIT_OBJ_IF_H
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#define LPDDR4_16BIT_OBJ_IF_H
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#include "lpddr4_16bit_if.h"
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#endif /* LPDDR4_16BIT_OBJ_IF_H */
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@ -1,15 +0,0 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_16BIT_STRUCTS_IF_H
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#define LPDDR4_16BIT_STRUCTS_IF_H
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#include <linux/types.h>
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#include "lpddr4_16bit_if.h"
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#endif /* LPDDR4_16BIT_STRUCTS_IF_H */
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@ -1,14 +0,0 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_32BIT_OBJ_IF_H
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#define LPDDR4_32BIT_OBJ_IF_H
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#include "lpddr4_32bit_if.h"
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#endif /* LPDDR4_32BIT_OBJ_IF_H */
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@ -1,15 +0,0 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_32BIT_STRUCTS_IF_H
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#define LPDDR4_32BIT_STRUCTS_IF_H
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#include <linux/types.h>
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#include "lpddr4_32bit_if.h"
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#endif /* LPDDR4_32BIT_STRUCTS_IF_H */
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@ -1,6 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
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# Copyright (C) 2019-2022 Texas Instruments Incorporated - http://www.ti.com/
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#
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obj-$(CONFIG_K3_DDRSS) += k3-ddrss.o
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@ -8,10 +8,14 @@ obj-$(CONFIG_K3_DDRSS) += lpddr4_obj_if.o
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obj-$(CONFIG_K3_DDRSS) += lpddr4.o
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ccflags-$(CONFIG_K3_DDRSS) += -Idrivers/ram/k3-ddrss/
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obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit.o
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obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit_ctl_regs_rw_masks.o
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ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/16bit/
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obj-$(CONFIG_K3_AM62A_DDRSS) += lpddr4_am6x.o
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obj-$(CONFIG_K3_AM62A_DDRSS) += lpddr4_am62a_ctl_regs_rw_masks.o
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ccflags-$(CONFIG_K3_AM62A_DDRSS) += -Idrivers/ram/k3-ddrss/am62a/
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obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit.o
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obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o
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ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/
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obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_am6x.o
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obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_am64_ctl_regs_rw_masks.o
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ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/am64/
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obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_j721e.o
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obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_j721e_ctl_regs_rw_masks.o
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ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/j721e/
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778
drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_0_macros.h
Normal file
778
drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_0_macros.h
Normal file
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@ -0,0 +1,778 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
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#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
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#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU
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#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU
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#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
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#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U
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#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U
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#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_1024
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#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0
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#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK 0x00010000U
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#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT 16U
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#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH 1U
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#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR 0U
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#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET 0U
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#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_1024
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#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0
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#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_MASK 0x07000000U
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#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT 24U
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#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH 3U
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#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_1024
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#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0
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#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU
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#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU
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#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU
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#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U
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#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U
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#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_1025
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#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0
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#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU
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#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU
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#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
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#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U
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#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U
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#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_1026
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#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0
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#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U
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#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT 16U
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#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH 8U
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#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_1026
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#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0
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#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U
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#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 24U
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#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U
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#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_1026
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#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0
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#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU
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#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU
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#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x000007FFU
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#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U
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#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U
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#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_1027
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#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0
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#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK 0x007F0000U
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#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT 16U
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#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U
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#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027
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#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0
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#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
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#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U
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#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
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#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027
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#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0
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#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U
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#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U
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#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
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#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U
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#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U
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#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_1028
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#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0
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#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U
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#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT 8U
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#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH 3U
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#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_1028
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#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0
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#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK 0x00010000U
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#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT 16U
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#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH 1U
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#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR 0U
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#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET 0U
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#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_1028
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#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0
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#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_MASK 0x01000000U
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#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U
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#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U
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#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U
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#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOSET 0U
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#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_1028
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#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0
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#define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU
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#define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU
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#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_MASK 0x0000007FU
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#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U
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#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U
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#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_1029
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#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0
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#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_MASK 0x00007F00U
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#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_SHIFT 8U
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#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_WIDTH 7U
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#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_1029
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#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0
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#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_MASK 0x001F0000U
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#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT 16U
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#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH 5U
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#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_1029
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#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0
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#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_MASK 0x01000000U
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#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT 24U
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#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH 1U
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#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR 0U
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#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOSET 0U
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#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_1029
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#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0
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|
||||
#define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U
|
||||
#define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1030
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_MASK 0x00000300U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_1030
|
||||
#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK 0x00070000U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_1030
|
||||
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_1030
|
||||
#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_WIDTH 27U
|
||||
#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_1031
|
||||
#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_1032
|
||||
#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_1033
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_1034
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_1035
|
||||
#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_MASK 0x07FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_1035
|
||||
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_1036
|
||||
#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH 24U
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_1037
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH 24U
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_1038
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_MASK 0x03000000U
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_1038
|
||||
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U
|
||||
#define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK 0x00000003U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_1039
|
||||
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK 0x00000F00U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_1039
|
||||
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH 9U
|
||||
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_1039
|
||||
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U
|
||||
#define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_1040
|
||||
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK 0x00000100U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_1040
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_1040
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_MASK 0x07000000U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_1040
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__REG DENALI_PHY_1041
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__REG DENALI_PHY_1042
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_1043
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1044_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_1044
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_1045
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_1046
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_1047
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_1048
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_1049
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_1050
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_1051
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1052_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_1052
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1053_READ_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH 30U
|
||||
#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_1053
|
||||
#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F3F03FFU
|
||||
#define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F3F03FFU
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK 0x000003FFU
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_1054
|
||||
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_MASK 0x003F0000U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_1054
|
||||
#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_1054
|
||||
#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1055_READ_MASK 0x3F0F3F3FU
|
||||
#define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x3F0F3F3FU
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_1055
|
||||
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK 0x00003F00U
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_1055
|
||||
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_MASK 0x000F0000U
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_1055
|
||||
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_1055
|
||||
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1056_READ_MASK 0xFFFFFF03U
|
||||
#define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0xFFFFFF03U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_MASK 0x00000003U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__REG DENALI_PHY_1056
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__REG DENALI_PHY_1056
|
||||
#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_MASK 0x00FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__REG DENALI_PHY_1056
|
||||
#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__REG DENALI_PHY_1056
|
||||
#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1057_READ_MASK 0x01FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x01FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__REG DENALI_PHY_1057
|
||||
#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__REG DENALI_PHY_1057
|
||||
#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_MASK 0x00FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__REG DENALI_PHY_1057
|
||||
#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1057
|
||||
#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1058_READ_MASK 0x3F03FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x3F03FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1058
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__REG DENALI_PHY_1058
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_MASK 0x00030000U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_DC_WEIGHT_0__REG DENALI_PHY_1058
|
||||
#define LPDDR4__PHY_ADR_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__REG DENALI_PHY_1058
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1059_READ_MASK 0x0101FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x0101FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_1059
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_1059
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__REG DENALI_PHY_1059
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__REG DENALI_PHY_1059
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1060_READ_MASK 0x00003F01U
|
||||
#define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x00003F01U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_START_0__REG DENALI_PHY_1060
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_MASK 0x00003F00U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_1060
|
||||
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1061_READ_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_1061
|
||||
#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0_MASK 0x00000700U
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__REG DENALI_PHY_1061
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0_MASK 0x07FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_1061
|
||||
#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1062_READ_MASK 0x07FF1F07U
|
||||
#define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x07FF1F07U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_MASK 0x00000007U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_WIDTH 3U
|
||||
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_1062
|
||||
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK 0x00001F00U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1062
|
||||
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK 0x07FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1062
|
||||
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1063_READ_MASK 0x1F07FF1FU
|
||||
#define LPDDR4__DENALI_PHY_1063_WRITE_MASK 0x1F07FF1FU
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK 0x0000001FU
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1063
|
||||
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK 0x0007FF00U
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1063
|
||||
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK 0x1F000000U
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1063
|
||||
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1064_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1064
|
||||
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1064
|
||||
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1065_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1065
|
||||
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
|
||||
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1066_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1066
|
||||
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1066
|
||||
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1067_READ_MASK 0x000F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1067_WRITE_MASK 0x000F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1067
|
||||
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0_MASK 0x000F0000U
|
||||
#define LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_1067
|
||||
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1068_READ_MASK 0xFF3F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1068_WRITE_MASK 0xFF3F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_1068
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0_MASK 0x003F0000U
|
||||
#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_1068
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_1068
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1069_READ_MASK 0x0103FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1069_WRITE_MASK 0x0103FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_1069
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK 0x0003FF00U
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_1069
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_1069
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1070_READ_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1070_WRITE_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_1070
|
||||
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1071_READ_MASK 0x03FF010FU
|
||||
#define LPDDR4__DENALI_PHY_1071_WRITE_MASK 0x03FF010FU
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_1071
|
||||
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_1071
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0_MASK 0x03FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__REG DENALI_PHY_1071
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1072_READ_MASK 0x0000FF01U
|
||||
#define LPDDR4__DENALI_PHY_1072_WRITE_MASK 0x0000FF01U
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__REG DENALI_PHY_1072
|
||||
#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__REG DENALI_PHY_1072
|
||||
#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0
|
||||
|
||||
#endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */
|
||||
778
drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_1_macros.h
Normal file
778
drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_1_macros.h
Normal file
|
|
@ -0,0 +1,778 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
|
||||
#define REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1280_READ_MASK 0x000107FFU
|
||||
#define LPDDR4__DENALI_PHY_1280_WRITE_MASK 0x000107FFU
|
||||
#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_1280
|
||||
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_1280
|
||||
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1_MASK 0x07000000U
|
||||
#define LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1_WIDTH 3U
|
||||
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__REG DENALI_PHY_1280
|
||||
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1281_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1281_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__REG DENALI_PHY_1281
|
||||
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1282_READ_MASK 0x0FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1282_WRITE_MASK 0x0FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_WIDTH 16U
|
||||
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_1282
|
||||
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1_MASK 0x00FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_1282
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x0F000000U
|
||||
#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_1282
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1283_READ_MASK 0xFF7F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1283_WRITE_MASK 0xFF7F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_1283
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_MASK 0x007F0000U
|
||||
#define LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_1283
|
||||
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_1283
|
||||
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1284_READ_MASK 0x01000707U
|
||||
#define LPDDR4__DENALI_PHY_1284_WRITE_MASK 0x01000707U
|
||||
#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U
|
||||
#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_1284
|
||||
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_MASK 0x00000700U
|
||||
#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__REG DENALI_PHY_1284
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__REG DENALI_PHY_1284
|
||||
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__REG DENALI_PHY_1284
|
||||
#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1285_READ_MASK 0x011F7F7FU
|
||||
#define LPDDR4__DENALI_PHY_1285_WRITE_MASK 0x011F7F7FU
|
||||
#define LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1_MASK 0x0000007FU
|
||||
#define LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__REG DENALI_PHY_1285
|
||||
#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1_MASK 0x00007F00U
|
||||
#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__REG DENALI_PHY_1285
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__REG DENALI_PHY_1285
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__REG DENALI_PHY_1285
|
||||
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1286_READ_MASK 0x01070301U
|
||||
#define LPDDR4__DENALI_PHY_1286_WRITE_MASK 0x01070301U
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_1286
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1_MASK 0x00000300U
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_TYPE_1__REG DENALI_PHY_1286
|
||||
#define LPDDR4__PHY_ADR_TYPE_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1_MASK 0x00070000U
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__REG DENALI_PHY_1286
|
||||
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_IE_MODE_1__REG DENALI_PHY_1286
|
||||
#define LPDDR4__PHY_ADR_IE_MODE_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1287_READ_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1287_WRITE_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1_WIDTH 27U
|
||||
#define LPDDR4__PHY_ADR_DDL_MODE_1__REG DENALI_PHY_1287
|
||||
#define LPDDR4__PHY_ADR_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1288_READ_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1288_WRITE_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_DDL_MASK_1__REG DENALI_PHY_1288
|
||||
#define LPDDR4__PHY_ADR_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1289_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1289_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__REG DENALI_PHY_1289
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1290_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1290_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_1290
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1291_READ_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1291_WRITE_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_START_1__REG DENALI_PHY_1291
|
||||
#define LPDDR4__PHY_ADR_CALVL_START_1__FLD LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1_MASK 0x07FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__REG DENALI_PHY_1291
|
||||
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__FLD LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1292_READ_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1292_WRITE_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_QTR_1__REG DENALI_PHY_1292
|
||||
#define LPDDR4__PHY_ADR_CALVL_QTR_1__FLD LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1293_READ_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1293_WRITE_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1_WIDTH 24U
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__REG DENALI_PHY_1293
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1294_READ_MASK 0x03FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1294_WRITE_MASK 0x03FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1_WIDTH 24U
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__REG DENALI_PHY_1294
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1_MASK 0x03000000U
|
||||
#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__REG DENALI_PHY_1294
|
||||
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__FLD LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1295_READ_MASK 0x01FF0F03U
|
||||
#define LPDDR4__DENALI_PHY_1295_WRITE_MASK 0x01FF0F03U
|
||||
#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1_MASK 0x00000003U
|
||||
#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__REG DENALI_PHY_1295
|
||||
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__FLD LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1_MASK 0x00000F00U
|
||||
#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__REG DENALI_PHY_1295
|
||||
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_MASK 0x01FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_WIDTH 9U
|
||||
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__REG DENALI_PHY_1295
|
||||
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1296_READ_MASK 0x07000001U
|
||||
#define LPDDR4__DENALI_PHY_1296_WRITE_MASK 0x07000001U
|
||||
#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__REG DENALI_PHY_1296
|
||||
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_MASK 0x00000100U
|
||||
#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__REG DENALI_PHY_1296
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__REG DENALI_PHY_1296
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__FLD LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1_MASK 0x07000000U
|
||||
#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__REG DENALI_PHY_1296
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1297_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1297_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_1__REG DENALI_PHY_1297
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_1__FLD LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1298_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1298_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_1__REG DENALI_PHY_1298
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_1__FLD LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1299_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1299_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS1_1__REG DENALI_PHY_1299
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS1_1__FLD LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1300_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1300_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS2_1__REG DENALI_PHY_1300
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS2_1__FLD LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1301_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1301_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_0_1__REG DENALI_PHY_1301
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_0_1__FLD LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1302_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1302_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_0_1__REG DENALI_PHY_1302
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_0_1__FLD LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1303_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1303_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_1_1__REG DENALI_PHY_1303
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_1_1__FLD LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1304_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1304_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_1_1__REG DENALI_PHY_1304
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_1_1__FLD LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1305_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1305_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_2_1__REG DENALI_PHY_1305
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_2_1__FLD LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1306_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1306_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_2_1__REG DENALI_PHY_1306
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_2_1__FLD LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1307_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1307_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_3_1__REG DENALI_PHY_1307
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_3_1__FLD LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1308_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1308_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_3_1__REG DENALI_PHY_1308
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_3_1__FLD LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1309_READ_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1309_WRITE_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1_WIDTH 30U
|
||||
#define LPDDR4__PHY_ADR_ADDR_SEL_1__REG DENALI_PHY_1309
|
||||
#define LPDDR4__PHY_ADR_ADDR_SEL_1__FLD LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1310_READ_MASK 0x3F3F03FFU
|
||||
#define LPDDR4__DENALI_PHY_1310_WRITE_MASK 0x3F3F03FFU
|
||||
#define LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1_MASK 0x000003FFU
|
||||
#define LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__REG DENALI_PHY_1310
|
||||
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1_MASK 0x003F0000U
|
||||
#define LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_BIT_MASK_1__REG DENALI_PHY_1310
|
||||
#define LPDDR4__PHY_ADR_BIT_MASK_1__FLD LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SEG_MASK_1__REG DENALI_PHY_1310
|
||||
#define LPDDR4__PHY_ADR_SEG_MASK_1__FLD LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1311_READ_MASK 0x3F0F3F3FU
|
||||
#define LPDDR4__DENALI_PHY_1311_WRITE_MASK 0x3F0F3F3FU
|
||||
#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__REG DENALI_PHY_1311
|
||||
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1_MASK 0x00003F00U
|
||||
#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__REG DENALI_PHY_1311
|
||||
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1_MASK 0x000F0000U
|
||||
#define LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__REG DENALI_PHY_1311
|
||||
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__REG DENALI_PHY_1311
|
||||
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1312_READ_MASK 0xFFFFFF03U
|
||||
#define LPDDR4__DENALI_PHY_1312_WRITE_MASK 0xFFFFFF03U
|
||||
#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1_MASK 0x00000003U
|
||||
#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_1__REG DENALI_PHY_1312
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_1__REG DENALI_PHY_1312
|
||||
#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1_MASK 0x00FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_1__REG DENALI_PHY_1312
|
||||
#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_1__REG DENALI_PHY_1312
|
||||
#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1313_READ_MASK 0x01FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1313_WRITE_MASK 0x01FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_1__REG DENALI_PHY_1313
|
||||
#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_1__REG DENALI_PHY_1313
|
||||
#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1_MASK 0x00FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_1__REG DENALI_PHY_1313
|
||||
#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1__REG DENALI_PHY_1313
|
||||
#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1314_READ_MASK 0x3F03FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1314_WRITE_MASK 0x3F03FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_1314
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_1__REG DENALI_PHY_1314
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1_MASK 0x00030000U
|
||||
#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_DC_WEIGHT_1__REG DENALI_PHY_1314
|
||||
#define LPDDR4__PHY_ADR_DC_WEIGHT_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_START_1__REG DENALI_PHY_1314
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_START_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1315_READ_MASK 0x0101FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1315_WRITE_MASK 0x0101FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1__REG DENALI_PHY_1315
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_1__REG DENALI_PHY_1315
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_1__REG DENALI_PHY_1315
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_1__REG DENALI_PHY_1315
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1316_READ_MASK 0x00003F01U
|
||||
#define LPDDR4__DENALI_PHY_1316_WRITE_MASK 0x00003F01U
|
||||
#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_START_1__REG DENALI_PHY_1316
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_START_1__FLD LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1_MASK 0x00003F00U
|
||||
#define LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__REG DENALI_PHY_1316
|
||||
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1317_READ_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1317_WRITE_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_TSEL_SELECT_1__REG DENALI_PHY_1317
|
||||
#define LPDDR4__PHY_ADR_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1_MASK 0x00000700U
|
||||
#define LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_1__REG DENALI_PHY_1317
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1_MASK 0x07FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__REG DENALI_PHY_1317
|
||||
#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__FLD LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1318_READ_MASK 0x07FF1F07U
|
||||
#define LPDDR4__DENALI_PHY_1318_WRITE_MASK 0x07FF1F07U
|
||||
#define LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_MASK 0x00000007U
|
||||
#define LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_WIDTH 3U
|
||||
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_1318
|
||||
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1_MASK 0x00001F00U
|
||||
#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1318
|
||||
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_MASK 0x07FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1318
|
||||
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1319_READ_MASK 0x1F07FF1FU
|
||||
#define LPDDR4__DENALI_PHY_1319_WRITE_MASK 0x1F07FF1FU
|
||||
#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1_MASK 0x0000001FU
|
||||
#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1319
|
||||
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_MASK 0x0007FF00U
|
||||
#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1319
|
||||
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1_MASK 0x1F000000U
|
||||
#define LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1319
|
||||
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1320_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1320_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1320
|
||||
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1320
|
||||
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1321_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1321_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1321
|
||||
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1321
|
||||
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1322_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1322_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1322
|
||||
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1322
|
||||
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1323_READ_MASK 0x000F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1323_WRITE_MASK 0x000F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1323
|
||||
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1_MASK 0x000F0000U
|
||||
#define LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__REG DENALI_PHY_1323
|
||||
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1324_READ_MASK 0xFF3F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1324_WRITE_MASK 0xFF3F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__REG DENALI_PHY_1324
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1_MASK 0x003F0000U
|
||||
#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__REG DENALI_PHY_1324
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__REG DENALI_PHY_1324
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1325_READ_MASK 0x0103FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1325_WRITE_MASK 0x0103FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_1325
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1_MASK 0x0003FF00U
|
||||
#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__REG DENALI_PHY_1325
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__REG DENALI_PHY_1325
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1326_READ_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1326_WRITE_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__REG DENALI_PHY_1326
|
||||
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1327_READ_MASK 0x03FF010FU
|
||||
#define LPDDR4__DENALI_PHY_1327_WRITE_MASK 0x03FF010FU
|
||||
#define LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__REG DENALI_PHY_1327
|
||||
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_MASK 0x00000100U
|
||||
#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_1327
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1_MASK 0x03FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_1__REG DENALI_PHY_1327
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1328_READ_MASK 0x0000FF01U
|
||||
#define LPDDR4__DENALI_PHY_1328_WRITE_MASK 0x0000FF01U
|
||||
#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_1__REG DENALI_PHY_1328
|
||||
#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_1__REG DENALI_PHY_1328
|
||||
#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_1__FLD LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1
|
||||
|
||||
#endif /* REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_ */
|
||||
778
drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_2_macros.h
Normal file
778
drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_2_macros.h
Normal file
|
|
@ -0,0 +1,778 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
|
||||
#define REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1536_READ_MASK 0x000107FFU
|
||||
#define LPDDR4__DENALI_PHY_1536_WRITE_MASK 0x000107FFU
|
||||
#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_1536
|
||||
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_1536
|
||||
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2_MASK 0x07000000U
|
||||
#define LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2_WIDTH 3U
|
||||
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__REG DENALI_PHY_1536
|
||||
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1537_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1537_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__REG DENALI_PHY_1537
|
||||
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1538_READ_MASK 0x0FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1538_WRITE_MASK 0x0FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_WIDTH 16U
|
||||
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_1538
|
||||
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2_MASK 0x00FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_1538
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x0F000000U
|
||||
#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_1538
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1539_READ_MASK 0xFF7F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1539_WRITE_MASK 0xFF7F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_1539
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_MASK 0x007F0000U
|
||||
#define LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1539
|
||||
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1539
|
||||
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1540_READ_MASK 0x01000707U
|
||||
#define LPDDR4__DENALI_PHY_1540_WRITE_MASK 0x01000707U
|
||||
#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U
|
||||
#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_1540
|
||||
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_MASK 0x00000700U
|
||||
#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__REG DENALI_PHY_1540
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__REG DENALI_PHY_1540
|
||||
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__REG DENALI_PHY_1540
|
||||
#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1541_READ_MASK 0x011F7F7FU
|
||||
#define LPDDR4__DENALI_PHY_1541_WRITE_MASK 0x011F7F7FU
|
||||
#define LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2_MASK 0x0000007FU
|
||||
#define LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__REG DENALI_PHY_1541
|
||||
#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2_MASK 0x00007F00U
|
||||
#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__REG DENALI_PHY_1541
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__REG DENALI_PHY_1541
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__REG DENALI_PHY_1541
|
||||
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1542_READ_MASK 0x01070301U
|
||||
#define LPDDR4__DENALI_PHY_1542_WRITE_MASK 0x01070301U
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_1542
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2_MASK 0x00000300U
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_TYPE_2__REG DENALI_PHY_1542
|
||||
#define LPDDR4__PHY_ADR_TYPE_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2_MASK 0x00070000U
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__REG DENALI_PHY_1542
|
||||
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_IE_MODE_2__REG DENALI_PHY_1542
|
||||
#define LPDDR4__PHY_ADR_IE_MODE_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1543_READ_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1543_WRITE_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2_WIDTH 27U
|
||||
#define LPDDR4__PHY_ADR_DDL_MODE_2__REG DENALI_PHY_1543
|
||||
#define LPDDR4__PHY_ADR_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1544_READ_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1544_WRITE_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_DDL_MASK_2__REG DENALI_PHY_1544
|
||||
#define LPDDR4__PHY_ADR_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1545_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1545_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__REG DENALI_PHY_1545
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1546_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1546_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_1546
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1547_READ_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1547_WRITE_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_START_2__REG DENALI_PHY_1547
|
||||
#define LPDDR4__PHY_ADR_CALVL_START_2__FLD LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2_MASK 0x07FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__REG DENALI_PHY_1547
|
||||
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__FLD LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1548_READ_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1548_WRITE_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_QTR_2__REG DENALI_PHY_1548
|
||||
#define LPDDR4__PHY_ADR_CALVL_QTR_2__FLD LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1549_READ_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1549_WRITE_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2_WIDTH 24U
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__REG DENALI_PHY_1549
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1550_READ_MASK 0x03FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1550_WRITE_MASK 0x03FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2_WIDTH 24U
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__REG DENALI_PHY_1550
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2_MASK 0x03000000U
|
||||
#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__REG DENALI_PHY_1550
|
||||
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__FLD LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1551_READ_MASK 0x01FF0F03U
|
||||
#define LPDDR4__DENALI_PHY_1551_WRITE_MASK 0x01FF0F03U
|
||||
#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2_MASK 0x00000003U
|
||||
#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__REG DENALI_PHY_1551
|
||||
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__FLD LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2_MASK 0x00000F00U
|
||||
#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__REG DENALI_PHY_1551
|
||||
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_MASK 0x01FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_WIDTH 9U
|
||||
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__REG DENALI_PHY_1551
|
||||
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1552_READ_MASK 0x07000001U
|
||||
#define LPDDR4__DENALI_PHY_1552_WRITE_MASK 0x07000001U
|
||||
#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__REG DENALI_PHY_1552
|
||||
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_MASK 0x00000100U
|
||||
#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__REG DENALI_PHY_1552
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__REG DENALI_PHY_1552
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__FLD LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2_MASK 0x07000000U
|
||||
#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__REG DENALI_PHY_1552
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1553_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1553_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_2__REG DENALI_PHY_1553
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_2__FLD LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1554_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1554_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_2__REG DENALI_PHY_1554
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_2__FLD LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1555_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1555_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS1_2__REG DENALI_PHY_1555
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS1_2__FLD LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1556_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1556_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS2_2__REG DENALI_PHY_1556
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS2_2__FLD LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1557_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1557_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_0_2__REG DENALI_PHY_1557
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_0_2__FLD LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1558_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1558_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_0_2__REG DENALI_PHY_1558
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_0_2__FLD LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1559_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1559_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_1_2__REG DENALI_PHY_1559
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_1_2__FLD LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1560_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1560_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_1_2__REG DENALI_PHY_1560
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_1_2__FLD LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1561_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1561_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_2_2__REG DENALI_PHY_1561
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_2_2__FLD LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1562_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1562_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_2_2__REG DENALI_PHY_1562
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_2_2__FLD LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1563_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1563_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_3_2__REG DENALI_PHY_1563
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_3_2__FLD LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1564_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1564_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_3_2__REG DENALI_PHY_1564
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_3_2__FLD LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1565_READ_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1565_WRITE_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2_WIDTH 30U
|
||||
#define LPDDR4__PHY_ADR_ADDR_SEL_2__REG DENALI_PHY_1565
|
||||
#define LPDDR4__PHY_ADR_ADDR_SEL_2__FLD LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1566_READ_MASK 0x3F3F03FFU
|
||||
#define LPDDR4__DENALI_PHY_1566_WRITE_MASK 0x3F3F03FFU
|
||||
#define LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2_MASK 0x000003FFU
|
||||
#define LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__REG DENALI_PHY_1566
|
||||
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2_MASK 0x003F0000U
|
||||
#define LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_BIT_MASK_2__REG DENALI_PHY_1566
|
||||
#define LPDDR4__PHY_ADR_BIT_MASK_2__FLD LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SEG_MASK_2__REG DENALI_PHY_1566
|
||||
#define LPDDR4__PHY_ADR_SEG_MASK_2__FLD LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1567_READ_MASK 0x3F0F3F3FU
|
||||
#define LPDDR4__DENALI_PHY_1567_WRITE_MASK 0x3F0F3F3FU
|
||||
#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__REG DENALI_PHY_1567
|
||||
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2_MASK 0x00003F00U
|
||||
#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__REG DENALI_PHY_1567
|
||||
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2_MASK 0x000F0000U
|
||||
#define LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__REG DENALI_PHY_1567
|
||||
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__REG DENALI_PHY_1567
|
||||
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1568_READ_MASK 0xFFFFFF03U
|
||||
#define LPDDR4__DENALI_PHY_1568_WRITE_MASK 0xFFFFFF03U
|
||||
#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2_MASK 0x00000003U
|
||||
#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_2__REG DENALI_PHY_1568
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_2__REG DENALI_PHY_1568
|
||||
#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2_MASK 0x00FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_2__REG DENALI_PHY_1568
|
||||
#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_2__REG DENALI_PHY_1568
|
||||
#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1569_READ_MASK 0x01FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1569_WRITE_MASK 0x01FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_2__REG DENALI_PHY_1569
|
||||
#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_2__REG DENALI_PHY_1569
|
||||
#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2_MASK 0x00FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_2__REG DENALI_PHY_1569
|
||||
#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2__REG DENALI_PHY_1569
|
||||
#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1570_READ_MASK 0x3F03FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1570_WRITE_MASK 0x3F03FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_1570
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_2__REG DENALI_PHY_1570
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2_MASK 0x00030000U
|
||||
#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_DC_WEIGHT_2__REG DENALI_PHY_1570
|
||||
#define LPDDR4__PHY_ADR_DC_WEIGHT_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_START_2__REG DENALI_PHY_1570
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_START_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1571_READ_MASK 0x0101FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1571_WRITE_MASK 0x0101FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2__REG DENALI_PHY_1571
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_2__REG DENALI_PHY_1571
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_2__REG DENALI_PHY_1571
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_2__REG DENALI_PHY_1571
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1572_READ_MASK 0x00003F01U
|
||||
#define LPDDR4__DENALI_PHY_1572_WRITE_MASK 0x00003F01U
|
||||
#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_START_2__REG DENALI_PHY_1572
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_START_2__FLD LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2_MASK 0x00003F00U
|
||||
#define LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__REG DENALI_PHY_1572
|
||||
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1573_READ_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1573_WRITE_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_TSEL_SELECT_2__REG DENALI_PHY_1573
|
||||
#define LPDDR4__PHY_ADR_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2_MASK 0x00000700U
|
||||
#define LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_2__REG DENALI_PHY_1573
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2_MASK 0x07FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__REG DENALI_PHY_1573
|
||||
#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__FLD LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1574_READ_MASK 0x07FF1F07U
|
||||
#define LPDDR4__DENALI_PHY_1574_WRITE_MASK 0x07FF1F07U
|
||||
#define LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_MASK 0x00000007U
|
||||
#define LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_WIDTH 3U
|
||||
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_1574
|
||||
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2_MASK 0x00001F00U
|
||||
#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1574
|
||||
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_MASK 0x07FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1574
|
||||
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1575_READ_MASK 0x1F07FF1FU
|
||||
#define LPDDR4__DENALI_PHY_1575_WRITE_MASK 0x1F07FF1FU
|
||||
#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2_MASK 0x0000001FU
|
||||
#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1575
|
||||
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_MASK 0x0007FF00U
|
||||
#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1575
|
||||
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2_MASK 0x1F000000U
|
||||
#define LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1575
|
||||
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1576_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1576_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1576
|
||||
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1576
|
||||
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1577_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1577_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1577
|
||||
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1577
|
||||
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1578_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1578_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1578
|
||||
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1578
|
||||
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1579_READ_MASK 0x000F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1579_WRITE_MASK 0x000F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1579
|
||||
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2_MASK 0x000F0000U
|
||||
#define LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__REG DENALI_PHY_1579
|
||||
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1580_READ_MASK 0xFF3F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1580_WRITE_MASK 0xFF3F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__REG DENALI_PHY_1580
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2_MASK 0x003F0000U
|
||||
#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__REG DENALI_PHY_1580
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__REG DENALI_PHY_1580
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1581_READ_MASK 0x0103FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1581_WRITE_MASK 0x0103FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_1581
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2_MASK 0x0003FF00U
|
||||
#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__REG DENALI_PHY_1581
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__REG DENALI_PHY_1581
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1582_READ_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1582_WRITE_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__REG DENALI_PHY_1582
|
||||
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1583_READ_MASK 0x03FF010FU
|
||||
#define LPDDR4__DENALI_PHY_1583_WRITE_MASK 0x03FF010FU
|
||||
#define LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__REG DENALI_PHY_1583
|
||||
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_MASK 0x00000100U
|
||||
#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_1583
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2_MASK 0x03FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_2__REG DENALI_PHY_1583
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1584_READ_MASK 0x0000FF01U
|
||||
#define LPDDR4__DENALI_PHY_1584_WRITE_MASK 0x0000FF01U
|
||||
#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_2__REG DENALI_PHY_1584
|
||||
#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_2__REG DENALI_PHY_1584
|
||||
#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_2__FLD LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2
|
||||
|
||||
#endif /* REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_ */
|
||||
25
drivers/ram/k3-ddrss/am62a/lpddr4_am62a_ctl_regs_rw_masks.h
Normal file
25
drivers/ram/k3-ddrss/am62a/lpddr4_am62a_ctl_regs_rw_masks.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_RW_MASKS_H_
|
||||
#define LPDDR4_RW_MASKS_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern u32 g_lpddr4_ddr_controller_rw_mask[435];
|
||||
extern u32 g_lpddr4_pi_rw_mask[424];
|
||||
extern u32 g_lpddr4_data_slice_0_rw_mask[137];
|
||||
extern u32 g_lpddr4_data_slice_1_rw_mask[137];
|
||||
extern u32 g_lpddr4_data_slice_2_rw_mask[137];
|
||||
extern u32 g_lpddr4_data_slice_3_rw_mask[137];
|
||||
extern u32 g_lpddr4_address_slice_0_rw_mask[49];
|
||||
extern u32 g_lpddr4_address_slice_1_rw_mask[49];
|
||||
extern u32 g_lpddr4_address_slice_2_rw_mask[49];
|
||||
extern u32 g_lpddr4_phy_core_rw_mask[132];
|
||||
|
||||
#endif /* LPDDR4_RW_MASKS_H_ */
|
||||
108
drivers/ram/k3-ddrss/am62a/lpddr4_am62a_if.h
Normal file
108
drivers/ram/k3-ddrss/am62a/lpddr4_am62a_if.h
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_AM62A_IF_H
|
||||
#define LPDDR4_AM62A_IF_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define LPDDR4_INTR_MAX_CS (2U)
|
||||
|
||||
#define LPDDR4_INTR_CTL_REG_COUNT (435U)
|
||||
|
||||
#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (424U)
|
||||
|
||||
#define LPDDR4_INTR_PHY_REG_COUNT (1924U)
|
||||
|
||||
typedef enum {
|
||||
LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT = 0U,
|
||||
LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH = 1U,
|
||||
LPDDR4_INTR_TIMEOUT_ZQ_CALSTART = 2U,
|
||||
LPDDR4_INTR_TIMEOUT_MRR_TEMP = 3U,
|
||||
LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ = 4U,
|
||||
LPDDR4_INTR_TIMEOUT_DFI_UPDATE = 5U,
|
||||
LPDDR4_INTR_TIMEOUT_LP_WAKEUP = 6U,
|
||||
LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX = 7U,
|
||||
LPDDR4_INTR_ECC_ERROR = 8U,
|
||||
LPDDR4_INTR_LP_DONE = 9U,
|
||||
LPDDR4_INTR_LP_TIMEOUT = 10U,
|
||||
LPDDR4_INTR_PORT_TIMEOUT = 11U,
|
||||
LPDDR4_INTR_RFIFO_TIMEOUT = 12U,
|
||||
LPDDR4_INTR_TRAINING_ZQ_STATUS = 13U,
|
||||
LPDDR4_INTR_TRAINING_DQS_OSC_DONE = 14U,
|
||||
LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE = 15U,
|
||||
LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW = 16U,
|
||||
LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT = 17U,
|
||||
LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS = 18U,
|
||||
LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS = 19U,
|
||||
LPDDR4_INTR_USERIF_PORT_CMD_ERROR = 20U,
|
||||
LPDDR4_INTR_USERIF_WRAP = 21U,
|
||||
LPDDR4_INTR_USERIF_INVAL_SETTING = 22U,
|
||||
LPDDR4_INTR_MISC_MRR_TRAFFIC = 23U,
|
||||
LPDDR4_INTR_MISC_SW_REQ_MODE = 24U,
|
||||
LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH = 25U,
|
||||
LPDDR4_INTR_MISC_TEMP_ALERT = 26U,
|
||||
LPDDR4_INTR_MISC_REFRESH_STATUS = 27U,
|
||||
LPDDR4_INTR_BIST_DONE = 28U,
|
||||
LPDDR4_INTR_CRC = 29U,
|
||||
LPDDR4_INTR_DFI_UPDATE_ERROR = 30U,
|
||||
LPDDR4_INTR_DFI_PHY_ERROR = 31U,
|
||||
LPDDR4_INTR_DFI_BUS_ERROR = 32U,
|
||||
LPDDR4_INTR_DFI_STATE_CHANGE = 33U,
|
||||
LPDDR4_INTR_DFI_DLL_SYNC_DONE = 34U,
|
||||
LPDDR4_INTR_DFI_TIMEOUT = 35U,
|
||||
LPDDR4_INTR_DIMM = 36U,
|
||||
LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE = 37U,
|
||||
LPDDR4_INTR_FREQ_DFS_HW_TERMINATE = 38U,
|
||||
LPDDR4_INTR_FREQ_DFS_HW_DONE = 39U,
|
||||
LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE = 40U,
|
||||
LPDDR4_INTR_FREQ_DFS_SW_TERMINATE = 41U,
|
||||
LPDDR4_INTR_FREQ_DFS_SW_DONE = 42U,
|
||||
LPDDR4_INTR_INIT_MEM_RESET_DONE = 43U,
|
||||
LPDDR4_INTR_MC_INIT_DONE = 44U,
|
||||
LPDDR4_INTR_INIT_POWER_ON_STATE = 45U,
|
||||
LPDDR4_INTR_MRR_ERROR = 46U,
|
||||
LPDDR4_INTR_MR_READ_DONE = 47U,
|
||||
LPDDR4_INTR_MR_WRITE_DONE = 48U,
|
||||
LPDDR4_INTR_PARITY_ERROR = 49U,
|
||||
LPDDR4_INTR_LOR_BITS = 50U
|
||||
} lpddr4_intr_ctlinterrupt;
|
||||
|
||||
typedef enum {
|
||||
LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT = 0U,
|
||||
LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT = 1U,
|
||||
LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT = 2U,
|
||||
LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT = 3U,
|
||||
LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT = 4U,
|
||||
LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT = 5U,
|
||||
LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT = 6U,
|
||||
LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT = 7U,
|
||||
LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT = 8U,
|
||||
LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT = 9U,
|
||||
LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT = 10U,
|
||||
LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT = 11U,
|
||||
LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT = 12U,
|
||||
LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT = 13U,
|
||||
LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT = 14U,
|
||||
LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 15U,
|
||||
LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 16U,
|
||||
LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT = 17U,
|
||||
LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT = 18U,
|
||||
LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT = 19U,
|
||||
LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT = 20U,
|
||||
LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT = 21U,
|
||||
LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT = 22U,
|
||||
LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT = 23U,
|
||||
LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT = 24U,
|
||||
LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT = 25U,
|
||||
LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT = 26U,
|
||||
LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT = 27U,
|
||||
LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT = 28U
|
||||
} lpddr4_intr_phyindepinterrupt;
|
||||
|
||||
#endif /* LPDDR4_AM62A_IF_H */
|
||||
14
drivers/ram/k3-ddrss/am62a/lpddr4_am62a_obj_if.h
Normal file
14
drivers/ram/k3-ddrss/am62a/lpddr4_am62a_obj_if.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_AM62A_OBJ_IF_H
|
||||
#define LPDDR4_AM62A_OBJ_IF_H
|
||||
|
||||
#include "lpddr4_am62a_if.h"
|
||||
|
||||
#endif /* LPDDR4_AM62A_OBJ_IF_H */
|
||||
15
drivers/ram/k3-ddrss/am62a/lpddr4_am62a_structs_if.h
Normal file
15
drivers/ram/k3-ddrss/am62a/lpddr4_am62a_structs_if.h
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_AM62A_STRUCTS_IF_H
|
||||
#define LPDDR4_AM62A_STRUCTS_IF_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include "lpddr4_am62a_if.h"
|
||||
|
||||
#endif /* LPDDR4_AM62A_STRUCTS_IF_H */
|
||||
1721
drivers/ram/k3-ddrss/am62a/lpddr4_ctl_regs.h
Normal file
1721
drivers/ram/k3-ddrss/am62a/lpddr4_ctl_regs.h
Normal file
File diff suppressed because it is too large
Load diff
2292
drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_0_macros.h
Normal file
2292
drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_0_macros.h
Normal file
File diff suppressed because it is too large
Load diff
2292
drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_1_macros.h
Normal file
2292
drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_1_macros.h
Normal file
File diff suppressed because it is too large
Load diff
2292
drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_2_macros.h
Normal file
2292
drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_2_macros.h
Normal file
File diff suppressed because it is too large
Load diff
2292
drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_3_macros.h
Normal file
2292
drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_3_macros.h
Normal file
File diff suppressed because it is too large
Load diff
6560
drivers/ram/k3-ddrss/am62a/lpddr4_ddr_controller_macros.h
Normal file
6560
drivers/ram/k3-ddrss/am62a/lpddr4_ddr_controller_macros.h
Normal file
File diff suppressed because it is too large
Load diff
1986
drivers/ram/k3-ddrss/am62a/lpddr4_phy_core_macros.h
Normal file
1986
drivers/ram/k3-ddrss/am62a/lpddr4_phy_core_macros.h
Normal file
File diff suppressed because it is too large
Load diff
6892
drivers/ram/k3-ddrss/am62a/lpddr4_pi_macros.h
Normal file
6892
drivers/ram/k3-ddrss/am62a/lpddr4_pi_macros.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_RW_MASKS_H_
|
||||
|
|
@ -2,12 +2,12 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_16BIT_IF_H
|
||||
#define LPDDR4_16BIT_IF_H
|
||||
#ifndef LPDDR4_AM64_IF_H
|
||||
#define LPDDR4_AM64_IF_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
|
|
@ -105,4 +105,4 @@ typedef enum {
|
|||
LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT = 28U
|
||||
} lpddr4_intr_phyindepinterrupt;
|
||||
|
||||
#endif /* LPDDR4_16BIT_IF_H */
|
||||
#endif /* LPDDR4_AM64_IF_H */
|
||||
14
drivers/ram/k3-ddrss/am64/lpddr4_am64_obj_if.h
Normal file
14
drivers/ram/k3-ddrss/am64/lpddr4_am64_obj_if.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_AM64_OBJ_IF_H
|
||||
#define LPDDR4_AM64_OBJ_IF_H
|
||||
|
||||
#include "lpddr4_am64_if.h"
|
||||
|
||||
#endif /* LPDDR4_AM64_OBJ_IF_H */
|
||||
15
drivers/ram/k3-ddrss/am64/lpddr4_am64_structs_if.h
Normal file
15
drivers/ram/k3-ddrss/am64/lpddr4_am64_structs_if.h
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_AM64_STRUCTS_IF_H
|
||||
#define LPDDR4_AM64_STRUCTS_IF_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include "lpddr4_am64_if.h"
|
||||
|
||||
#endif /* LPDDR4_AM64_STRUCTS_IF_H */
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_CTL_REGS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_PHY_CORE_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_PI_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef CPS_DRV_H_
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_CTL_REGS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_DATA_SLICE_2_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_DATA_SLICE_3_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_RW_MASKS_H_
|
||||
|
|
@ -2,12 +2,12 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_32BIT_IF_H
|
||||
#define LPDDR4_32BIT_IF_H
|
||||
#ifndef LPDDR4_J721E_IF_H
|
||||
#define LPDDR4_J721E_IF_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
|
|
@ -88,4 +88,4 @@ typedef enum {
|
|||
LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U
|
||||
} lpddr4_intr_phyindepinterrupt;
|
||||
|
||||
#endif /* LPDDR4_32BIT_IF_H */
|
||||
#endif /* LPDDR4_J721E_IF_H */
|
||||
14
drivers/ram/k3-ddrss/j721e/lpddr4_j721e_obj_if.h
Normal file
14
drivers/ram/k3-ddrss/j721e/lpddr4_j721e_obj_if.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_J721E_OBJ_IF_H
|
||||
#define LPDDR4_J721E_OBJ_IF_H
|
||||
|
||||
#include "lpddr4_j721e_if.h"
|
||||
|
||||
#endif /* LPDDR4_J721E_OBJ_IF_H */
|
||||
15
drivers/ram/k3-ddrss/j721e/lpddr4_j721e_structs_if.h
Normal file
15
drivers/ram/k3-ddrss/j721e/lpddr4_j721e_structs_if.h
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_J721E_STRUCTS_IF_H
|
||||
#define LPDDR4_J721E_STRUCTS_IF_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include "lpddr4_j721e_if.h"
|
||||
|
||||
#endif /* LPDDR4_J721E_STRUCTS_IF_H */
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_PHY_CORE_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_PI_MACROS_H_
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
|
|
@ -13,14 +13,6 @@
|
|||
#include "lpddr4.h"
|
||||
#include "lpddr4_structs_if.h"
|
||||
|
||||
#ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY
|
||||
#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
|
||||
#endif
|
||||
|
||||
#ifndef LPDDR4_CPS_NS_DELAY_TIME
|
||||
#define LPDDR4_CPS_NS_DELAY_TIME 10000000U
|
||||
#endif
|
||||
|
||||
static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay);
|
||||
static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd);
|
||||
static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd);
|
||||
|
|
@ -51,10 +43,7 @@ static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_l
|
|||
static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
|
||||
static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
|
||||
static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
|
||||
#ifdef REG_WRITE_VERIF
|
||||
static u32 lpddr4_getphyrwmask(u32 regoffset);
|
||||
static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
|
||||
#endif
|
||||
|
||||
u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay)
|
||||
{
|
||||
|
|
@ -202,8 +191,6 @@ u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoff
|
|||
return result;
|
||||
}
|
||||
|
||||
#ifdef REG_WRITE_VERIF
|
||||
|
||||
static u32 lpddr4_getphyrwmask(u32 regoffset)
|
||||
{
|
||||
u32 rwmask = 0U;
|
||||
|
|
@ -231,33 +218,43 @@ static u32 lpddr4_getphyrwmask(u32 regoffset)
|
|||
return rwmask;
|
||||
}
|
||||
|
||||
static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue)
|
||||
u32 lpddr4_deferredregverify(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regvalues[], u16 regnum[], u16 regcount)
|
||||
{
|
||||
u32 result = (u32)0;
|
||||
u32 aindex;
|
||||
u32 regreadval = 0U;
|
||||
u32 rwmask = 0U;
|
||||
|
||||
result = lpddr4_readreg(pd, cpp, regoffset, ®readval);
|
||||
result = lpddr4_deferredregverifysf(pd, cpp);
|
||||
|
||||
if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
|
||||
result = EINVAL;
|
||||
if (result == (u32)0) {
|
||||
switch (cpp) {
|
||||
case LPDDR4_PHY_INDEP_REGS:
|
||||
rwmask = g_lpddr4_pi_rw_mask[regoffset];
|
||||
break;
|
||||
case LPDDR4_PHY_REGS:
|
||||
rwmask = lpddr4_getphyrwmask(regoffset);
|
||||
break;
|
||||
default:
|
||||
rwmask = g_lpddr4_ddr_controller_rw_mask[regoffset];
|
||||
break;
|
||||
}
|
||||
for (aindex = 0; aindex < regcount; aindex++) {
|
||||
result = lpddr4_readreg(pd, cpp, (u32)regnum[aindex], ®readval);
|
||||
|
||||
if ((rwmask & regreadval) != (regvalue & rwmask))
|
||||
result = EIO;
|
||||
if (result == (u32)0) {
|
||||
switch (cpp) {
|
||||
case LPDDR4_PHY_INDEP_REGS:
|
||||
rwmask = g_lpddr4_pi_rw_mask[(u32)regnum[aindex]];
|
||||
break;
|
||||
case LPDDR4_PHY_REGS:
|
||||
rwmask = lpddr4_getphyrwmask((u32)regnum[aindex]);
|
||||
break;
|
||||
default:
|
||||
rwmask = g_lpddr4_ddr_controller_rw_mask[(u32)regnum[aindex]];
|
||||
break;
|
||||
}
|
||||
|
||||
if ((rwmask & regreadval) != ((u32)(regvalues[aindex]) & rwmask)) {
|
||||
result = EIO;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue)
|
||||
{
|
||||
|
|
@ -284,11 +281,6 @@ u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regof
|
|||
CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset), regvalue);
|
||||
}
|
||||
}
|
||||
#ifdef REG_WRITE_VERIF
|
||||
if (result == (u32)0)
|
||||
result = lpddr4_verifyregwrite(pd, cpp, regoffset, regvalue);
|
||||
|
||||
#endif
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
@ -346,9 +338,6 @@ u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef ASILC
|
||||
#endif
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_H
|
||||
|
|
@ -11,19 +11,13 @@
|
|||
|
||||
#include "lpddr4_ctl_regs.h"
|
||||
#include "lpddr4_sanity.h"
|
||||
#ifdef CONFIG_K3_AM64_DDRSS
|
||||
#include "lpddr4_16bit.h"
|
||||
#include "lpddr4_16bit_sanity.h"
|
||||
#else
|
||||
#include "lpddr4_32bit.h"
|
||||
#include "lpddr4_32bit_sanity.h"
|
||||
#endif
|
||||
|
||||
#ifdef REG_WRITE_VERIF
|
||||
#include "lpddr4_ctl_regs_rw_masks.h"
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#if defined (CONFIG_K3_AM64_DDRSS) || defined (CONFIG_K3_AM62A_DDRSS)
|
||||
#include "lpddr4_am6x.h"
|
||||
#include "lpddr4_am6x_sanity.h"
|
||||
#else
|
||||
#include "lpddr4_j721e.h"
|
||||
#include "lpddr4_j721e_sanity.h"
|
||||
#endif
|
||||
|
||||
#define PRODUCT_ID (0x1046U)
|
||||
|
|
@ -56,6 +50,14 @@ extern "C" {
|
|||
#define CDN_TRUE 1U
|
||||
#define CDN_FALSE 0U
|
||||
|
||||
#ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY
|
||||
#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
|
||||
#endif
|
||||
|
||||
#ifndef LPDDR4_CPS_NS_DELAY_TIME
|
||||
#define LPDDR4_CPS_NS_DELAY_TIME 10000000U
|
||||
#endif
|
||||
|
||||
void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
|
||||
volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset);
|
||||
u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay);
|
||||
|
|
@ -66,8 +68,5 @@ u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd);
|
|||
void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
|
||||
u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus);
|
||||
u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* LPDDR4_H */
|
||||
|
|
|
|||
|
|
@ -1,33 +0,0 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_16BIT_H
|
||||
#define LPDDR4_16BIT_H
|
||||
|
||||
#define DSLICE_NUM (2U)
|
||||
#define ASLICE_NUM (3U)
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DSLICE0_REG_COUNT (126U)
|
||||
#define DSLICE1_REG_COUNT (126U)
|
||||
#define ASLICE0_REG_COUNT (42U)
|
||||
#define ASLICE1_REG_COUNT (42U)
|
||||
#define ASLICE2_REG_COUNT (42U)
|
||||
#define PHY_CORE_REG_COUNT (126U)
|
||||
|
||||
#define GRP_SHIFT 1
|
||||
#define INT_SHIFT 2
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* LPDDR4_16BIT_H */
|
||||
1726
drivers/ram/k3-ddrss/lpddr4_am62a_ctl_regs_rw_masks.c
Normal file
1726
drivers/ram/k3-ddrss/lpddr4_am62a_ctl_regs_rw_masks.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -2,12 +2,12 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include "lpddr4_ctl_regs_rw_masks.h"
|
||||
#include <lpddr4_am64_ctl_regs_rw_masks.h>
|
||||
|
||||
u32 g_lpddr4_ddr_controller_rw_mask[] = {
|
||||
0x00000F01U,
|
||||
|
|
@ -2,19 +2,18 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#include "cps_drv_lpddr4.h"
|
||||
#include "lpddr4_ctl_regs.h"
|
||||
#include "lpddr4_if.h"
|
||||
#include "lpddr4.h"
|
||||
#include "lpddr4_structs_if.h"
|
||||
|
||||
static u32 ctlintmap[51][3] = {
|
||||
static u16 ctlintmap[51][3] = {
|
||||
{ 0, 0, 7 },
|
||||
{ 1, 0, 8 },
|
||||
{ 2, 0, 9 },
|
||||
|
|
@ -86,6 +85,7 @@ u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd)
|
|||
CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)), regval);
|
||||
regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)));
|
||||
CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
|
@ -345,15 +345,18 @@ u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mr
|
|||
result = (u32)EIO;
|
||||
} else {
|
||||
*mrrstatus = (u8)0;
|
||||
#ifdef CONFIG_K3_AM64_DDRSS
|
||||
lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA__REG));
|
||||
#else
|
||||
lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_0__REG));
|
||||
*mmrvalue = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_1__REG));
|
||||
#endif
|
||||
*mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata);
|
||||
result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
#ifdef REG_WRITE_VERIF
|
||||
|
||||
u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
|
||||
{
|
||||
u32 rwmask = 0U;
|
||||
|
|
@ -370,7 +373,6 @@ u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
|
|||
}
|
||||
return rwmask;
|
||||
}
|
||||
#endif
|
||||
|
||||
u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam)
|
||||
{
|
||||
45
drivers/ram/k3-ddrss/lpddr4_am6x.h
Normal file
45
drivers/ram/k3-ddrss/lpddr4_am6x.h
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_AM6X_H
|
||||
#define LPDDR4_AM6X_H
|
||||
|
||||
#ifdef CONFIG_K3_AM64_DDRSS
|
||||
#include "lpddr4_am64_ctl_regs_rw_masks.h"
|
||||
#elif CONFIG_K3_AM62A_DDRSS
|
||||
#include "lpddr4_am62a_ctl_regs_rw_masks.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_K3_AM64_DDRSS
|
||||
#define DSLICE_NUM (2U)
|
||||
#define ASLICE_NUM (2U)
|
||||
#define DSLICE0_REG_COUNT (126U)
|
||||
#define DSLICE1_REG_COUNT (126U)
|
||||
#define ASLICE0_REG_COUNT (42U)
|
||||
#define ASLICE1_REG_COUNT (42U)
|
||||
#define ASLICE2_REG_COUNT (42U)
|
||||
#define PHY_CORE_REG_COUNT (126U)
|
||||
|
||||
#elif CONFIG_K3_AM62A_DDRSS
|
||||
#define DSLICE_NUM (4U)
|
||||
#define ASLICE_NUM (3U)
|
||||
#define DSLICE0_REG_COUNT (136U)
|
||||
#define DSLICE1_REG_COUNT (136U)
|
||||
#define DSLICE2_REG_COUNT (136U)
|
||||
#define DSLICE3_REG_COUNT (136U)
|
||||
#define ASLICE0_REG_COUNT (48U)
|
||||
#define ASLICE1_REG_COUNT (48U)
|
||||
#define ASLICE2_REG_COUNT (48U)
|
||||
#define PHY_CORE_REG_COUNT (132U)
|
||||
|
||||
#endif
|
||||
|
||||
#define GRP_SHIFT 1
|
||||
#define INT_SHIFT 2
|
||||
|
||||
#endif /* LPDDR4_AM6X_H */
|
||||
|
|
@ -2,19 +2,19 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_16BIT_SANITY_H
|
||||
#define LPDDR4_16BIT_SANITY_H
|
||||
#ifndef LPDDR4_AM6X_SANITY_H
|
||||
#define LPDDR4_AM6X_SANITY_H
|
||||
|
||||
#include <errno.h>
|
||||
#include <linux/types.h>
|
||||
#include <lpddr4_if.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include <lpddr4_if.h>
|
||||
#include <lpddr4_if.h>
|
||||
#include <lpddr4_if.h>
|
||||
|
||||
static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
|
||||
static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
|
||||
|
|
@ -250,8 +250,4 @@ static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, cons
|
|||
return ret;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* LPDDR4_16BIT_SANITY_H */
|
||||
#endif /* LPDDR4_AM6X_SANITY_H */
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_IF_H
|
||||
|
|
@ -11,9 +11,11 @@
|
|||
|
||||
#include <linux/types.h>
|
||||
#ifdef CONFIG_K3_AM64_DDRSS
|
||||
#include <lpddr4_16bit_if.h>
|
||||
#include <lpddr4_am64_if.h>
|
||||
#elif CONFIG_K3_AM62A_DDRSS
|
||||
#include <lpddr4_am62a_if.h>
|
||||
#else
|
||||
#include <lpddr4_32bit_if.h>
|
||||
#include <lpddr4_j721e_if.h>
|
||||
#endif
|
||||
|
||||
typedef struct lpddr4_config_s lpddr4_config;
|
||||
|
|
@ -141,4 +143,6 @@ u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *
|
|||
|
||||
u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval);
|
||||
|
||||
u32 lpddr4_deferredregverify(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regvalues[], u16 regnum[], u16 regcount);
|
||||
|
||||
#endif /* LPDDR4_IF_H */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
|
|
@ -273,8 +273,6 @@ u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mr
|
|||
return result;
|
||||
}
|
||||
|
||||
#ifdef REG_WRITE_VERIF
|
||||
|
||||
u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
|
||||
{
|
||||
u32 rwmask = 0U;
|
||||
|
|
@ -299,4 +297,3 @@ u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
|
|||
}
|
||||
return rwmask;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -2,20 +2,18 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_32BIT_H
|
||||
#define LPDDR4_32BIT_H
|
||||
#ifndef LPDDR4_J721E_H
|
||||
#define LPDDR4_J721E_H
|
||||
|
||||
#include "lpddr4_j721e_ctl_regs_rw_masks.h"
|
||||
|
||||
#define DSLICE_NUM (4U)
|
||||
#define ASLICE_NUM (1U)
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DSLICE0_REG_COUNT (140U)
|
||||
#define DSLICE1_REG_COUNT (140U)
|
||||
#define DSLICE2_REG_COUNT (140U)
|
||||
|
|
@ -23,8 +21,4 @@ extern "C" {
|
|||
#define ASLICE0_REG_COUNT (52U)
|
||||
#define PHY_CORE_REG_COUNT (140U)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* LPDDR4_32BIT_H */
|
||||
#endif /* LPDDR4_J721E_H */
|
||||
|
|
@ -2,12 +2,12 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include "lpddr4_ctl_regs_rw_masks.h"
|
||||
#include <lpddr4_j721e_ctl_regs_rw_masks.h>
|
||||
|
||||
u32 g_lpddr4_ddr_controller_rw_mask[] = {
|
||||
0x00000F01U,
|
||||
|
|
@ -2,19 +2,16 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_32BIT_SANITY_H
|
||||
#define LPDDR4_32BIT_SANITY_H
|
||||
#ifndef LPDDR4_J721E_SANITY_H
|
||||
#define LPDDR4_J721E_SANITY_H
|
||||
|
||||
#include <errno.h>
|
||||
#include <linux/types.h>
|
||||
#include <lpddr4_if.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
|
||||
static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
|
||||
|
|
@ -216,8 +213,4 @@ static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, cons
|
|||
return ret;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* LPDDR4_32BIT_SANITY_H */
|
||||
#endif /* LPDDR4_J721E_SANITY_H */
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include "lpddr4_obj_if.h"
|
||||
|
|
@ -45,6 +45,7 @@ lpddr4_obj *lpddr4_getinstance(void)
|
|||
.getrefreshrate = lpddr4_getrefreshrate,
|
||||
.setrefreshrate = lpddr4_setrefreshrate,
|
||||
.refreshperchipselect = lpddr4_refreshperchipselect,
|
||||
.deferredregverify = lpddr4_deferredregverify,
|
||||
};
|
||||
|
||||
return &driver;
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef lpddr4_obj_if_h
|
||||
|
|
@ -79,6 +79,8 @@ typedef struct lpddr4_obj_s {
|
|||
u32 (*setrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
|
||||
|
||||
u32 (*refreshperchipselect)(const lpddr4_privatedata *pd, const u32 trefinterval);
|
||||
|
||||
u32 (*deferredregverify)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regvalues[], u16 regnum[], u16 regcount);
|
||||
} lpddr4_obj;
|
||||
|
||||
extern lpddr4_obj *lpddr4_getinstance(void);
|
||||
|
|
|
|||
|
|
@ -1,60 +0,0 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/**********************************************************************
|
||||
* Copyright (C) 2012-2018 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
**********************************************************************
|
||||
* Cadence Core Driver for LPDDR4.
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_PRIV_H
|
||||
#define LPDDR4_PRIV_H
|
||||
|
||||
#define PRODUCT_ID (0x1046U)
|
||||
#define VERSION_0 (0x54d5da40U)
|
||||
#define VERSION_1 (0xc1865a1U)
|
||||
|
||||
#define LPDDR4_BIT_MASK (0x1U)
|
||||
#define BYTE_MASK (0xffU)
|
||||
#define NIBBLE_MASK (0xfU)
|
||||
|
||||
#define WORD_SHIFT (32U)
|
||||
#define WORD_MASK (0xffffffffU)
|
||||
#define SLICE_WIDTH (0x100)
|
||||
/* Number of Data slices */
|
||||
#define DSLICE_NUM (4U)
|
||||
/*Number of Address Slices */
|
||||
#define ASLICE_NUM (1U)
|
||||
|
||||
/* Number of accessible registers in each slice */
|
||||
#define DSLICE0_REG_COUNT (140U)
|
||||
#define DSLICE1_REG_COUNT (140U)
|
||||
#define DSLICE2_REG_COUNT (140U)
|
||||
#define DSLICE3_REG_COUNT (140U)
|
||||
#define ASLICE0_REG_COUNT (52U)
|
||||
#define PHY_CORE_REG_COUNT (140U)
|
||||
|
||||
#define CTL_OFFSET 0
|
||||
#define PI_OFFSET (((uint32_t)1) << 11)
|
||||
#define PHY_OFFSET (((uint32_t)1) << 12)
|
||||
|
||||
/* BIT[17] on INT_MASK_1 register. */
|
||||
#define CTL_INT_MASK_ALL ((uint32_t)LPDDR4_LOR_BITS - WORD_SHIFT)
|
||||
|
||||
/* Init Error information bits */
|
||||
#define PLL_READY (0x3U)
|
||||
#define IO_CALIB_DONE ((uint32_t)0x1U << 23U)
|
||||
#define IO_CALIB_FIELD ((uint32_t)NIBBLE_MASK << 28U)
|
||||
#define IO_CALIB_STATE ((uint32_t)0xBU << 28U)
|
||||
#define RX_CAL_DONE ((uint32_t)LPDDR4_BIT_MASK << 4U)
|
||||
#define CA_TRAIN_RL (((uint32_t)LPDDR4_BIT_MASK << 5U) | \
|
||||
((uint32_t)LPDDR4_BIT_MASK << 4U))
|
||||
#define WR_LVL_STATE (((uint32_t)NIBBLE_MASK) << 13U)
|
||||
#define GATE_LVL_ERROR_FIELDS (((uint32_t)LPDDR4_BIT_MASK << 7U) | \
|
||||
((uint32_t)LPDDR4_BIT_MASK << 6U))
|
||||
#define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | \
|
||||
(((uint32_t)BYTE_MASK) << 16U))
|
||||
#define DQ_LVL_STATUS (((uint32_t)LPDDR4_BIT_MASK << 26U) | \
|
||||
(((uint32_t)BYTE_MASK) << 18U))
|
||||
|
||||
#endif /* LPDDR4_PRIV_H */
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_SANITY_H
|
||||
|
|
@ -12,9 +12,6 @@
|
|||
#include <errno.h>
|
||||
#include <linux/types.h>
|
||||
#include "lpddr4_if.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
static inline u32 lpddr4_configsf(const lpddr4_config *obj);
|
||||
static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj);
|
||||
|
|
@ -37,7 +34,7 @@ static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lp
|
|||
static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
|
||||
static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off);
|
||||
static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
|
||||
static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
|
||||
static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref_val, const u32 *tras_max_val);
|
||||
static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
|
||||
|
||||
#define lpddr4_probesf lpddr4_sanityfunction1
|
||||
|
|
@ -70,6 +67,7 @@ static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lp
|
|||
#define lpddr4_getrefreshratesf lpddr4_sanityfunction28
|
||||
#define lpddr4_setrefreshratesf lpddr4_sanityfunction29
|
||||
#define lpddr4_refreshperchipselectsf lpddr4_sanityfunction3
|
||||
#define lpddr4_deferredregverifysf lpddr4_sanityfunction5
|
||||
|
||||
static inline u32 lpddr4_configsf(const lpddr4_config *obj)
|
||||
{
|
||||
|
|
@ -390,15 +388,15 @@ static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lp
|
|||
return ret;
|
||||
}
|
||||
|
||||
static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
|
||||
static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref_val, const u32 *tras_max_val)
|
||||
{
|
||||
u32 ret = 0;
|
||||
|
||||
if (fspnum == NULL) {
|
||||
ret = EINVAL;
|
||||
} else if (tref == NULL) {
|
||||
} else if (tref_val == NULL) {
|
||||
ret = EINVAL;
|
||||
} else if (tras_max == NULL) {
|
||||
} else if (tras_max_val == NULL) {
|
||||
ret = EINVAL;
|
||||
} else if (lpddr4_privatedatasf(pd) == EINVAL) {
|
||||
ret = EINVAL;
|
||||
|
|
@ -438,8 +436,4 @@ static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lp
|
|||
return ret;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* LPDDR4_SANITY_H */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_STRUCTS_IF_H
|
||||
|
|
|
|||
Loading…
Reference in a new issue