Add build support for Agilex SoC.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add device tree files for Agilex SoC platform.
socfpga_agilex-u-boot.dtsi and socfpga_agilex_socdk-u-boot.dts contains
Uboot specific DT properties.
socfpga_agilex.dtsi and socfpga_agilex_socdk.dts are from Linux
(kernel/git/dinguyen/linux.git, commit 6f0bf971bacacc)
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add clock wrapper functions call to clock DM functions to get clock
frequency and used in cm_print_clock_quick_summary().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.
agilex-clock.h is from Linux commit ID cd2e1ad12247.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz.
Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Move Stratix10 and Agilex clock manager common code to new header file.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add system manager support for Agilex.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Move Stratix10 and Agilex system manager common code to
system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add reset manager support for Agilex.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Move Stratix10 and Agilex reset manager common code to
reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*.
Remove unused RSTMGR_XXX defines.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Move firewall related code to new firewall.c, to share
code in Stratix 10 and Agilex.
SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC
to allow DMA transfer to OCRAM.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add base address for Intel Agilex SoC.
Reuse base_addr_s10.h for Agilex, only one base address is
different from S10.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get clock manager base address from DT node instead of using
#define.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get system manager base address from DT node instead of
using #define.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get reset manager base address from DT node instead of using
#define.
spl_early_init() initializes the DT setup. So, move spl_early_init() to
beginning of function and before get base address from DT.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes to use it in SPL.
In preparation to get base address from DT.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Import the Khadas VIM3L device-tree from [1]
[1] e42617b825f8 ("Linux 5.5-rc1")
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
It's true that booting normally doesn't take long enough for the
register to roll (which actually happens in a little over an hour, not
just a few seconds). However, the counter starts at power-on, and if
the board is held in reset to be booted over USB, one actually risks
hitting wrap-around during boot, which can both result in too short
delays (if the "st += delay" calculation makes st small) and
theoretically also unbound delays (if st ends up being UINT_MAX and
one just misses sampling digctl_microseconds at that point).
It doesn't take more code to DTRT, and once bitten, twice shy.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Engicam i.CoreM6 1.5 Quad/Dual MIPI dtsi is reusing fec node
from Engicam i.CoreM6 dtsi but have sampe copy of phy-reset-gpio
and phy-mode properties.
So, drop this phy reset methods from imx6qdl-icore-1.5 dsti file.
Cc: Jacopo Mondi <jacopo@jmondi.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The EDIMM STARTER KIT i.Core 1.5 MIPI Evaluation is based on
the 1.5 version of the i.Core MX6 cpu module. The 1.5 version
differs from the original one for a few details, including the
ethernet PHY interface clock provider.
With this commit, the ethernet interface works properly:
SMSC LAN8710/LAN8720 2188000.ethernet-1:00: attached PHY driver
While before using the 1.5 version, ethernet failed to startup
do to un-clocked PHY interface:
fec 2188000.ethernet eth0: could not attach to PHY
Similar fix has merged for i.Core MX6Q but missed to update for DL.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Sync Engicam device tree file from v5.4 linux-next.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The data sheet says that the DIV field cannot change while the CLKGATE
bit is set or modified. So do it a little more carefully, by first
clearing the bit, waiting for that to appear, then setting the DIV
field.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
The comment says to clear the bypass bit, but in fact it sets it, thus
selecting ref_xtal. And the next line of code does not set the divider
to 12, but to (the reset value of) 1.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
I tried clearing a bit by writing to hw_clkctrl_gpmi_clr, then
busy-waiting for it to actually clear. My board hung. The data sheet
agrees, these registers do not have _set, _clr, _tog, so fix up the
definitions. git grep -E 'clkctrl_(gpmi|ssp[0-9])_' says that nobody
uses those non-existing ops registers.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Add info about supported i.MX7, improve details the usage of
bcbonly subcommand.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
In cases when the same SPL should run on boards with i.MX8MM, that
differ in DDR configuration, it is necessary to try different
parameters and check if the training done by the firmware suceeds or
not.
Therefore we return the DDR training/initialization success to the
upper layer in order to be able to retry with different settings if
necessary.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
In the case of i.MX6 and i.MX7 family SoCs it is safe (from an errata
point of view) to use thumb2 by default to save space.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Currently imx-specific bootaux command doesn't support ELF format
firmware for Cortex-M4 core.
This patches introduces a PoC implementation of handling elf firmware
(load_elf_image_phdr() was copy-pasted from elf.c just for PoC).
ELF64 binaries isn't supported yet.
This has the advantage that the user does not need to know to which
address the binary has been linked to. However, in order to handle
and load the elf sections to the right address, we need to translate the
Cortex-M4 core memory addresses to primary/host CPU memory
addresses (Cortex A7/A9 cores).
This allows to boot firmwares from any location with just using
bootaux, e.g.:
> tftp ${loadaddr} hello_world.elf && bootaux ${loadaddr}
Similar translation table can be found in the Linux remoteproc
driver [1].
[1] https://elixir.bootlin.com/linux/latest/source/drivers/remoteproc/imx_rproc.c
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Sync DTS with the mainline Linux and introduce fec node and
regulator configuration for rn5t567 PMU.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Sync DTS with the mainline Linux and introduce fec node.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Sync DTS with the mainline Linux and introduce fec node.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
The Embedded Artists COM board is based on NXP i.MX7ULP.
It has a BD70528 PMIC from Rohm with discrete DCDC powering option and
improved current observability (compared to the existing NXP i.MX7ULP EVK).
Add the initial support for the board.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Note: gpio7_8 was never used for usb power regulator so we remove it here
Acked-by: Patrick Bruenn <p.bruenn@beckhoff.com>
Signed-off-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Sync the Linux Kernel 5.4-rc6 device tree for Phytec Phycore
SoM and Segin board based on imx6UL and imx6ULL.
Changes includes Phytec naming convention for the devicetree files.
Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
This patch fixes the issue with broken bootaux command,
when M4 binary is loaded and data cache isn't flushed
before M4 core is enabled.
Reproducing:
> tftpboot ${loadaddr} ${board_name}/hello_world.bin
> cp.b ${loadaddr} 0x7F8000 $filesize
> bootaux 0x7F8000
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
1. Change information printed about loaded M4 binary, print the stack
pointer and reset vector addressed.
2. Add sanity check for the address provided as param.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
This patch adds support for iMX6SX MMDC into the DDR calibration
code. The only difference between MX6DQ and MX6SX is that the SX
has 2 SDQS registers, while the DQ has 8.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Eric Nelson <eric@nelint.com>
Instead of explicitly setting up each SDQS register, use a loop.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Eric Nelson <eric@nelint.com>
Pull out the code turning SDQS pullups on and off into a separate
function, since it is replicated in two places in the code and it
is the single place in the entire function which is SoC dependent.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Eric Nelson <eric@nelint.com>
The %08X format returns just zeroes with tiny printf, which is
horribly confusing, especially when debugging DRAM calibration
problems. Change the format to %08x (with lowercase x), which
behaves correctly with either implementation of printf in SPL.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Eric Nelson <eric@nelint.com>
The wdt-reboot node is needed for the sysreset_watchdog driver to
register a watchdog as a reset handler in case 'CONFIG_SYSRESET' is
enabled.
Signed-off-by: Claudius Heine <ch@denx.de>
These DT files are copied from kernel v5.3 with no changes.
This is part 2 of 2 commits. Included are DT files for SOM rev 1.5, and
Hummingboard2 Gate/Edge.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
These DT files are copied from kernel v5.3 with no changes.
This is part 1 of 2 commits. Included are DT files for the original
Cubox-i and Hummingboard Base/Pro.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Copy device trees from linux, keeping them as separate files for
each board to ease future sync.
Update board code to use generic bx50v3 dt initially, then select
the specific dt based on board detection.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
This patch introduces support for i.MX28 based XEA board.
This board supports DM/DTS in U-Boot proper as well as DM aware drivers
in SPL (u-boot.sb) by using OF_PLATDATA.
More detailed information regarding usage of it can be found in
./board/liebherr/xea/README file.
U-Boot SPL 2019.10-rc1-00233-g6aa549f05c (Aug 12 2019 - 09:23:36 +0200)
Trying to boot from MMC1
MMC0: Command 8 timeout (status 0xf0344020)
mmc_load_image_raw_sector: mmc block read error
U-Boot 2019.10-rc1-00233-g6aa549f05c (Aug 12 2019 - 09:23:36 +0200)
CPU: Freescale i.MX28 rev1.2 at 454 MHz
BOOT: SSP SPI #3, master, 3V3 NOR
Model: Liebherr (LWE) XEA i.MX28 Board
DRAM: 128 MiB
MMC: MXS MMC: 0
Loading Environment from SPI Flash... SF: Detected n25q128a13 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
OK
In: serial
Out: serial
Err: serial
Net:
Warning: ethernet@800f0000 (eth0) using random MAC address - ce:e1:9e:46:f3:a2
eth0: ethernet@800f0000
Hit any key to stop autoboot: 0
Signed-off-by: Lukasz Majewski <lukma@denx.de>
add DM_SERIAL support for the aristainetos board, and
remove not used code from board code.
remove CONSOLE_OVERWRITE_ROUTINE.
Signed-off-by: Heiko Schocher <hs@denx.de>
as we switch to support DM and DTS, rework the existing
DTS trees. Change also Linux specific Device trees, goal
is to push this changes to linux.
Collect U-Boot specific changes in separate "*u-boot*" dts
files.
Signed-off-by: Heiko Schocher <hs@denx.de>
Add device trees from Linux in preparation for driver model
conversions.
device tree files taken from Linux:
71ae5fc87c34: "Merge tag 'linux-kselftest-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest"
and added SPDX license identifier.
Signed-off-by: Heiko Schocher <hs@denx.de>
remove 2b version of aristainetos board, as it
is easier to make the DM / DTS port and introduce
the 2b board version again (also some more board
version).
Signed-off-by: Heiko Schocher <hs@denx.de>
Bring in the following merges:
commit 8fbbec12f7
Merge: 87f69f467a63618e71e8
Author: Tom Rini <trini@konsulko.com>
Date: Fri Jan 3 09:48:47 2020 -0500
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next
- updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support
commit 87f69f467a
Merge: c0912f9bbf4466b99703
Author: Tom Rini <trini@konsulko.com>
Date: Tue Dec 24 08:18:19 2019 -0500
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next
- Enable DM driver on ppc/km boards
- Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x,
T104x, P4080, P2041, P2020, P1020, P3041
- Some updates in mpc85xx-ddr driver, km boards
commit c0912f9bbf
Merge: 533c9f5714a1d6dc3f84
Author: Tom Rini <trini@konsulko.com>
Date: Wed Dec 18 07:20:19 2019 -0500
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral
commit 533c9f5714
Merge: 553cb06887033e18b47b
Author: Tom Rini <trini@konsulko.com>
Date: Tue Dec 17 07:53:08 2019 -0500
Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next
i2c: for next
- misc: i2c_eeprom:
Add partition support and add ability to query size
of eeprom device and partitions
- i2c common:
add support for offset overflow in to address and add
sandbox tests for it.
commit 553cb06887
Merge: f39abbbc53b4f98b3b16
Author: Tom Rini <trini@konsulko.com>
Date: Thu Dec 12 08:18:59 2019 -0500
Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next
buildman improvements including toolchain environment feature
sandbox unicode support in serial
On K3 devices there are 2 conditions where R5F can deadlock:
1.When software is performing series of store operations to
cacheable write back/write allocate memory region and later
on software execute barrier operation (DSB or DMB). R5F may
hang at the barrier instruction.
2.When software is performing a mix of load and store operations
within a tight loop and store operations are all writing to
cacheable write back/write allocates memory regions, R5F may
hang at one of the load instruction.
To avoid the above two conditions disable linefill optimization
inside Cortex R5F which will make R5F to only issue up to 2 cache
line fills at any point of time.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Update the ddr settings to use the DDR reg config tool rev 0.2.0.
This reduces the aging count(in DDRSS_CTL_274_DATA reg) to 15 in-order
to avoid DSS underflow errors.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
- Fix latest mainline kernel for rk3308
- Update rk3288-evb config to suport OP-TEE
- Fix for firefly-px30 DEBUG_UART channel and make it standalone
- Script make_fit_atf add python3 support
- Fix rk3328 timer with correct COUNTER_FREQUENCY
- Fix rk3328 ATF support with enable spl-fifo-mode
move the PCIE related config from arch Kconfig to PCI Kconfig.
As the PCI_LAYERSCAPE driver is being used in platform other than
fsl-layerscape platforms like ls102xa.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This fixes commit <91435cd40d30> "ARM: i.MX6: exclude the ARM errata
from i.MX6 UP system"
for nitrogen6x. The above commit removed the errata for the board
since MX6Q/MXDL/MX6S is selected via CONFIG_SYS_EXTRA_OPTIONS
This restores the errata configs.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
IMX based platforms can have the DCD table located on different
addresses due to differences in their memory maps (ie iMX7ULP).
This information is required by the user to sign the images for secure
boot so continue making it accessible via mkimage.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
SPL_ROCKCHIP_COMMON_BOARD, an almost identical option, has a title but
this one doesn't for some reason. Add a description to make the menu
easier to read.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Firefly Core-PX30-JD4 use UART2M1 while PX30 evb using UART2M0, the U-Boot
proper will use the dts setting to do the IOMUX init, and a separate dts
is needed for px30-firefly.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
On a distribution with no python2 installed and no
python->python3 symlink the script will fail to execute.
Specify python3 explicitly as it's already a requirement
to build u-boot.
Signed-off-by: Jack Mitchell <ml@embed.me.uk>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Instead of hardcode the base address, we can get them from the build
output, eg. get the SYS_TEXT_BASE from .config and get optee base from
DRAM_BASE.
We can use this script for SoCs with DRAM base not from 0x60000000(rk3229
and many other 32bit Rockchip SoCs), eg. rk3288 DRAM base is 0.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Enable AHB support for Flexspi controller interface meaning
memory can be accessed via md command using absolute addresses
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Hardware comes out of reset with implicit values, but these are outside
the accepted range for Layerscape gen 3 chassis spec used on LS1028A.
Allocate different IDs and fix up Linux DT to use them.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
LX2160A PL011 UART driver fetch IP block values using
platform data from board file instead of device tree.
Modified UART nodes in device tree to disable state.
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
USB3.0 Receiver needs to enable fixed equalization
for each of PHY instances in an SOC. This is similar
to erratum A-009007, but this one is for LX2160A,
and the register value is different.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Mark board_fit_config_name_match() as weak so a board can overwrite the
empty function.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
struct sunxi_prcm_reg is naturally packed. There is no need to define it as
packed. Defining it as packed leads to compilation errors with GCC 9.2.1:
CC arch/arm/lib/reloc_arm_efi.o
arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’:
:qarch/arm/cpu/armv7/sunxi/psci.c:163:21: error: taking address of packed
member of ‘struct sunxi_prcm_reg’ may result in an unaligned pointer value
[-Werror=address-of-packed-member]
163 | sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,
| ^~~~~~~~~~~~~~~~~~~~~~~~~
Remove __packed attribute from struct sunxi_prcm_reg.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Orangepi Zero Plus 2 is an open-source single-board computer, available
in two Allwinner SOC variants, H3 and H5. We add support for H3 variant
here, as the H5 is already supported.
H3 Orangepi Zero Plus 2 has:
- Quad-core Cortex-A7
- 512MB DDR3
- microSD slot and 8GB eMMC
- Debug TTL UART
- HDMI
- Wifi + BT
- OTG + power supply
Sync dts from linux v5.2 commit:
"ARM: dts: sunxi: h3/h5: Remove stale pinctrl-names entry"
(sha1: 75f9a058838be9880afd75c4cb14e1bf4fe34a0b)
Commit:
"ARM: dts: sun8i: h3: Refactor the pinctrl node names"
(sha1: a4dc791974e568a15f7f37131729b1a6912f4811)
has been avoided as it breaks U-Boot build.
Signed-off-by: Diego Rondini <diego.rondini@kynetics.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Compiling with GCC 9.2.1 leads to build errors:
arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’:
arch/arm/cpu/armv7/sunxi/psci.c:144:21: error: taking address of packed
member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer
value [-Werror=address-of-packed-member]
144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
| ^~~~~~~~~~~~~~~~~~~~~~~
arch/arm/cpu/armv7/sunxi/psci.c:144:46: error: taking address of packed
member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer
value [-Werror=address-of-packed-member]
144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
| ^~~~~~~~~~~~~~~~~~~~
Use memcpy() and void* pointers to resolve the problem caused by packing
the struct sunxi_cpucfg_reg.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral
This patch is only a temporarily workaround for crash introduced by
commit ac9cd4805c ("bootstage: Correct relocation algorithm").
The crash occurs because the bootstage struct is not correctly aligned
when BOOTSTAGE feature is activated.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Activate by default the command CLS (clear screen);
this command used in pxe or sysboot command (DISTRO support)
when the "menu background" keyword is present.
This patch avoid the warning "Unknown command 'cls'"
with extlinux.conf:
# Generic Distro Configuration file generated by OpenEmbedded
menu title Select the boot mode
MENU BACKGROUND /splash.bmp
TIMEOUT 20
DEFAULT stm32mp157c-ev1-emmc
LABEL stm32mp157c-ev1-emmc
KERNEL /uImage
FDT /stm32mp157c-ev1.dtb
APPEND root=/dev/mmcblk1p4 rootwait rw console=ttySTM0,115200
...
Retrieving file: /mmc0_stm32mp157c-ev1_extlinux/extlinux.conf
614 bytes read in 36 ms (16.6 KiB/s)
Retrieving file: /splash.bmp
46180 bytes read in 40 ms (1.1 MiB/s)
Unknown command 'cls' - try 'help'
Select the boot mode
1: stm32mp157c-ev1-sdcard
...
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
The SST26VF064BEUI spi-nor flash is programmed at the factory with a
globally unique address stored in the SFDP vendor parameter table and
it is permanently writeprotected. Retrieve the EUI-48 address and set it
as ethaddr env.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Add support for setting the chip address offset mask to EEPROM sumulator
and add tests to test it.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Improve i2c EEPROM simulator testing by providing access functions to
check the previous chip addr and offset.
Given that we can now directly test the offsets, also simplified the
offset mapping and allow for wrapping acceses.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add support for coral which is a range of Apollo Lake-based Chromebook
released in 2017. This also includes reef released in 2016, since it is
based on the same SoC.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The memory and silicon init parts of the FSP need support code to work.
Add this for Apollo Lake.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These are mostly specific to a particular SoC. Add the definitions for
Apollo Lake.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports
various child devices. It supposed both device tree and of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add code to init the system both in TPL and SPL. Each phase has its own
procedure.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add loaders for SPL and TPL so that the next stage can be loaded from
memory-mapped SPI or, failing that, the Fast SPI driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a
syscon driver since it only needs to be probed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver for the Apollo Lake Platform Controller Hub. It does not have
any functionality and is just a placeholder for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This driver the LPC and provides a few functions to set up LPC features.
These should probably use ioctls() or perhaps, better, have specific
uclass methods.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This driver models some sort of interrupt thingy but there are so many
abreviations that I cannot find out what it stands for. Possibly something
to do with interrupts.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This driver models the hostbridge as a northbridge. It simply sets up the
graphics BAR. It supports of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This driver handles communication with the systemagent which needs to be
told when U-Boot has completed its init.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver for the Apollo Lake pinctrl. This mostly makes use of the
common Intel pinctrl support.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver for the Apollo Lake UART. It uses the standard ns16550 device
but also sets up the input clock with LPSS and supports configuration via
of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver for the Apollo Lake SoC. It supports the basic operations and
can use device tree or of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add some fixed IO and mmap addresses for use in the device tree and with
some early-init code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function is specific to qemu so it seems best to keep it separate
from the generic code.
Move it out to a new file and update the condition to use if() instead of
#ifdef
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Recent Intel SoCs share a pinctrl mechanism with many common elements. Add
an implementation of this core functionality, allowing SoC-specific
drivers to avoid adding common code.
As well as a pinctrl driver this provides a GPIO driver based on the same
code.
Once other SoCs use this driver we may consider moving more properties to
the device tree (e.g. the community info and pad definitions).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This subsystem is present on various Intel SoCs.
Add very basic support for taking an lpss device out of reset.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
If these phases are used we typically want to enable pinctrl in then, so
that pad setup and GPIO access are possible.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is used on several boards so add it to the common file. Also add a
useful power-limit value while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present binman does not support updating a device tree that is part of
U-Boot (i.e u-boot.bin). Separate the entries into two so that we can get
updated entry information. This makes binman_entry_find() work correctly.
Do the same for SPL tool.
In both cases, group the two parts into a section so that SPL symbols get
the correct total size.
It may be possible for binman to handle this automatically at some point,
by ignoring u-boot.bin and always creating it from u-boot-nodtb.bin and
u-boot.dtb
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present if SPL sets up the microcode then it is still included in
U-Boot as well. This is wasteful as microcode is large. Adjust the logic
in the image to prevent this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add these entries to the ROM so that we can list the contents of an image
with 'binman ls'. The image-header is not essential but does speed up
access.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different
location from where SPL must be placed in ROM. In other words, although
SPL runs before SDRAM is set up, it is not execute-in-place (XIP).
Add a Kconfig option for the ROM position.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The existing work-around for positioning U-Boot in the ROM when it
actually runs from RAM still exists and there is not obvious way to change
this.
Add a proper Kconfig option to handle this case. This also adds a new bool
property to indicate whether CONFIG_SYS_TEXT_BASE exists.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Include the IFWI section and the FSP-M binary. The FSP-T binary is not
currently used, as CAR is set up manually.
Also drop the FSP binary as this relates only to FSP1.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we don't support loading microcode with FSP2. The correct way
to do this is by adding it to the FIT. For now, disable including
microcode in the image.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
Add support for these along with suitable configuration options.
To make the code cleaner, adjust a few definitions in processor.h so that
they can be used from assembler.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Many Intel SoCs require a FIT in order to boot properly. Add an option to
include this and enable it by default.
This term can be confused with FIT (Flat Image Tree) in U-Boot so the
CONFIG option has to include 'X86'.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't generally have enough space to run this, so don't build it into
TPL. This helps reduce the size of TPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The fsp_notify() API is the same for FSP1 and FSP2. Move it into a new
common API file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
FSP-S is used by the notify call after it has been used for silicon init.
To avoid having to load it again, add a field to store the location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The FSP-S may do this but at least for coral it does not. Set this up so
that graphics is not deathly slow.
It isn't clear whether the FSP is expected to set up MTRR. It is not
mentioned in the APL FSP document.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for some important configuration options and FSP memory init.
The memory init uses swizzle tables from the device tree.
Support for the FSP_S binary is also included.
Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI
reads.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This generic FSP file should include the generic FSP support header, not
the FSP1 version. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Both versions of FSP can use the same graphics support, so move it into
the common directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the interrupt table is included in all phases of U-Boot. Allow
it to be omitted, e.g. in TPL, to reduce size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't want to pull in libfdt if of-platdata is being used, since it
reduces the available code-size saves. Also, SPI flash is seldom needed
in TPL.
Drop these options.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Set up MTRRs for the FSP SDRAM regions to improve performance.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present with fsp a single DRAM bank is added which extends to the
whole size of memory. However there is typically only 2GB of memory
available below the 4GB boundary, and this is what is used by U-Boot while
running in 32-bit mode.
Scan the tables to set the banks correct. The first bank is set to memory
below 4GB, and the rest of memory is put into subsequent banks.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function needs to be different for FSP2, so move the existing
function into the fsp1 directory. Since it is only called from one file,
drop it from the header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function is only used within the implementation so make it static.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With Apollo Lake we need to support a normal cache, which almost never
changes and a much smaller 'variable' cache which changes every time.
Update the code to add a cache type, use an array for the caches and use a
for loop to iterate over the caches.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function is a bit confusing at present due to the error handling.
Update it to remove the goto, returning errors as they happen.
While we are here, use hex for the data size since this is the norm in
U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we reuse the mrc_output char * to also point to the cache
record after it has been set up. This is confusing and doesn't save much
data space.
Add a new mrc_cache member instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is now possible to obtain the memory map for a SPI controllers instead
of having it hard-coded in the device tree. Update the code to support
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
