Simon Glass f45e747d6d x86: Add support for newer CAR schemes ... Newer Intel SoCs have different ways of setting up cache-as-ram (CAR). Add support for these along with suitable configuration options. To make the code cleaner, adjust a few definitions in processor.h so that they can be used from assembler. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>		2019-12-15 11:44:18 +08:00
..
arc	common: Move enable/disable_interrupts out of common.h	2019-12-02 18:25:01 -05:00
arm	dm: gpio: Allow control of GPIO uclass in SPL	2019-12-15 08:52:29 +08:00
m68k	common: Move trap_init() out of common.h	2019-12-02 18:25:25 -05:00
microblaze	common: Move enable/disable_interrupts out of common.h	2019-12-02 18:25:01 -05:00
mips	Merge branch '2019-12-02-master-imports'	2019-12-02 22:05:35 -05:00
nds32	common: Move enable/disable_interrupts out of common.h	2019-12-02 18:25:01 -05:00
nios2	common: Move enable/disable_interrupts out of common.h	2019-12-02 18:25:01 -05:00
powerpc	common: Move some board functions out of common.h	2019-12-02 18:25:21 -05:00
riscv	riscv: add option to wait for ack from secondary harts in smp functions	2019-12-10 08:23:10 +08:00
sandbox	sandbox: Add a test for IRQ	2019-12-15 11:44:12 +08:00
sh	common: Move enable/disable_interrupts out of common.h	2019-12-02 18:25:01 -05:00
x86	x86: Add support for newer CAR schemes	2019-12-15 11:44:18 +08:00
xtensa	common: Move interrupt functions into a new header	2019-12-02 18:25:00 -05:00
.gitignore
Kconfig	x86: Don't imply libfdt or SPI flash in TPL	2019-12-15 11:44:15 +08:00