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x86: Add support for newer CAR schemes
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR). Add support for these along with suitable configuration options. To make the code cleaner, adjust a few definitions in processor.h so that they can be used from assembler. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
parent
2e2a0035d4
commit
f45e747d6d
5 changed files with 564 additions and 7 deletions
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@ -879,4 +879,20 @@ config HIGH_TABLE_SIZE
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Increse it if the default size does not fit the board's needs.
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This is most likely due to a large ACPI DSDT table is used.
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config INTEL_CAR_CQOS
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bool "Support Intel Cache Quality of Service"
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help
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Cache Quality of Service allows more fine-grained control of cache
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usage. As result, it is possible to set up a portion of L2 cache for
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CAR and use the remainder for actual caching.
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#
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# Each bit in QOS mask controls this many bytes. This is calculated as:
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# (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
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#
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config CACHE_QOS_SIZE_PER_BIT
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hex
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depends on INTEL_CAR_CQOS
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default 0x20000 # 128 KB
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endmenu
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@ -8,6 +8,14 @@ obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o
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obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o
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obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o
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endif
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ifdef CONFIG_INTEL_CAR_CQOS
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obj-$(CONFIG_TPL_BUILD) += car2.o
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ifndef CONFIG_SPL_BUILD
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obj-y += car2_uninit.o
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endif
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endif
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obj-y += cpu.o
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obj-y += fast_spi.o
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obj-y += lpc.o
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448
arch/x86/cpu/intel_common/car2.S
Normal file
448
arch/x86/cpu/intel_common/car2.S
Normal file
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@ -0,0 +1,448 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This file was modified from the coreboot version.
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*
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* Copyright (C) 2015-2016 Intel Corp.
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*/
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#include <config.h>
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#include <asm/msr-index.h>
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#include <asm/mtrr.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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#include <asm/processor-flags.h>
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#define KiB 1024
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#define IS_POWER_OF_2(x) (!((x) & ((x) - 1)))
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.global car_init
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car_init:
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post_code(POST_CAR_START)
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/*
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* Use the MTRR default type MSR as a proxy for detecting INIT#.
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* Reset the system if any known bits are set in that MSR. That is
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* an indication of the CPU not being properly reset.
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*/
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check_for_clean_reset:
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mov $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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and $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax
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cmp $0, %eax
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jz no_reset
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/* perform warm reset */
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movw $IO_PORT_RESET, %dx
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movb $(SYS_RST | RST_CPU), %al
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outb %al, %dx
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no_reset:
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post_code(POST_CAR_SIPI)
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/* Clear/disable fixed MTRRs */
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mov $fixed_mtrr_list_size, %ebx
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xor %eax, %eax
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xor %edx, %edx
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clear_fixed_mtrr:
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add $-2, %ebx
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movzwl fixed_mtrr_list(%ebx), %ecx
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wrmsr
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jnz clear_fixed_mtrr
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post_code(POST_CAR_MTRR)
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/* Figure put how many MTRRs we have, and clear them out */
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mov $MTRR_CAP_MSR, %ecx
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rdmsr
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movzb %al, %ebx /* Number of variable MTRRs */
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mov $MTRR_PHYS_BASE_MSR(0), %ecx
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xor %eax, %eax
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xor %edx, %edx
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clear_var_mtrr:
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wrmsr
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inc %ecx
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wrmsr
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inc %ecx
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dec %ebx
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jnz clear_var_mtrr
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post_code(POST_CAR_UNCACHEABLE)
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/* Configure default memory type to uncacheable (UC) */
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mov $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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/* Clear enable bits and set default type to UC */
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and $~(MTRR_DEF_TYPE_MASK | MTRR_DEF_TYPE_EN | \
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MTRR_DEF_TYPE_FIX_EN), %eax
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wrmsr
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/*
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* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB
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* based on the physical address size supported for this processor
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* This is based on read from CPUID EAX = 080000008h, EAX bits [7:0]
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*
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* Examples:
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* MTRR_PHYS_MASK_HIGH = 00000000Fh For 36 bit addressing
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* MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing
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*/
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movl $0x80000008, %eax /* Address sizes leaf */
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cpuid
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sub $32, %al
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movzx %al, %eax
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xorl %esi, %esi
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bts %eax, %esi
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dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */
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post_code(POST_CAR_BASE_ADDRESS)
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#if IS_POWER_OF_2(CONFIG_DCACHE_RAM_SIZE)
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/* Configure CAR region as write-back (WB) */
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mov $MTRR_PHYS_BASE_MSR(0), %ecx
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mov $CONFIG_DCACHE_RAM_BASE, %eax
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or $MTRR_TYPE_WRBACK, %eax
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xor %edx,%edx
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wrmsr
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/* Configure the MTRR mask for the size region */
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mov $MTRR_PHYS_MASK(0), %ecx
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mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */
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dec %eax
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not %eax
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or $MTRR_PHYS_MASK_VALID, %eax
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movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */
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wrmsr
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#elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */
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/* Configure CAR region as write-back (WB) */
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mov $MTRR_PHYS_BASE_MSR(0), %ecx
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mov $CONFIG_DCACHE_RAM_BASE, %eax
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or $MTRR_TYPE_WRBACK, %eax
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xor %edx,%edx
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wrmsr
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mov $MTRR_PHYS_MASK_MSR(0), %ecx
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mov $(512 * KiB), %eax /* size mask */
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dec %eax
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not %eax
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or $MTRR_PHYS_MASK_VALID, %eax
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movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */
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wrmsr
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mov $MTRR_PHYS_BASE_MSR(1), %ecx
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mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax
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or $MTRR_TYPE_WRBACK, %eax
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xor %edx,%edx
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wrmsr
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mov $MTRR_PHYS_MASK_MSR(1), %ecx
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mov $(256 * KiB), %eax /* size mask */
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dec %eax
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not %eax
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or $MTRR_PHYS_MASK_VALID, %eax
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movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */
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wrmsr
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#else
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#error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing"
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#endif
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post_code(POST_CAR_FILL)
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/* Enable variable MTRRs */
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mov $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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or $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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/* Enable caching */
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mov %cr0, %eax
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and $~(X86_CR0_CD | X86_CR0_NW), %eax
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invd
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mov %eax, %cr0
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#if IS_ENABLED(CONFIG_INTEL_CAR_NEM)
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jmp car_nem
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#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
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jmp car_cqos
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#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED)
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jmp car_nem_enhanced
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#else
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#error "No CAR mechanism selected:
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#endif
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jmp car_init_ret
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fixed_mtrr_list:
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.word MTRR_FIX_64K_00000_MSR
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.word MTRR_FIX_16K_80000_MSR
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.word MTRR_FIX_16K_A0000_MSR
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.word MTRR_FIX_4K_C0000_MSR
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.word MTRR_FIX_4K_C8000_MSR
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.word MTRR_FIX_4K_D0000_MSR
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.word MTRR_FIX_4K_D8000_MSR
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.word MTRR_FIX_4K_E0000_MSR
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.word MTRR_FIX_4K_E8000_MSR
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.word MTRR_FIX_4K_F0000_MSR
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.word MTRR_FIX_4K_F8000_MSR
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fixed_mtrr_list_size = . - fixed_mtrr_list
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#if IS_ENABLED(CONFIG_INTEL_CAR_NEM)
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.global car_nem
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car_nem:
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/* Disable cache eviction (setup stage) */
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mov $MSR_EVICT_CTL, %ecx
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rdmsr
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or $0x1, %eax
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wrmsr
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post_code(0x26)
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/* Clear the cache memory region. This will also fill up the cache */
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movl $CONFIG_DCACHE_RAM_BASE, %edi
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movl $CONFIG_DCACHE_RAM_SIZE, %ecx
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shr $0x02, %ecx
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xor %eax, %eax
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cld
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rep stosl
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post_code(0x27)
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/* Disable cache eviction (run stage) */
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mov $MSR_EVICT_CTL, %ecx
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rdmsr
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or $0x2, %eax
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wrmsr
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post_code(0x28)
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jmp car_init_ret
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#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
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.global car_cqos
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car_cqos:
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/*
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* Create CBM_LEN_MASK based on CBM_LEN
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* Get CPUID.(EAX=10H, ECX=2H):EAX.CBM_LEN[bits 4:0]
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*/
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mov $0x10, %eax
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mov $0x2, %ecx
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cpuid
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and $0x1f, %eax
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add $1, %al
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mov $1, %ebx
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mov %al, %cl
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shl %cl, %ebx
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sub $1, %ebx
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/* Store the CBM_LEN_MASK in mm3 for later use */
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movd %ebx, %mm3
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/*
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* Disable both L1 and L2 prefetcher. For yet-to-understood reason,
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* prefetchers slow down filling cache with rep stos in CQOS mode.
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*/
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mov $MSR_PREFETCH_CTL, %ecx
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rdmsr
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or $(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax
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wrmsr
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#if (CONFIG_DCACHE_RAM_SIZE == CONFIG_L2_CACHE_SIZE)
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/*
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* If CAR size is set to full L2 size, mask is calculated as all-zeros.
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* This is not supported by the CPU/uCode.
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*/
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#error "CQOS CAR may not use whole L2 cache area"
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#endif
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/* Calculate how many bits to be used for CAR */
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xor %edx, %edx
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mov $CONFIG_DCACHE_RAM_SIZE, %eax /* dividend */
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mov $CONFIG_CACHE_QOS_SIZE_PER_BIT, %ecx /* divisor */
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div %ecx /* result is in eax */
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mov %eax, %ecx /* save to ecx */
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mov $1, %ebx
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shl %cl, %ebx
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sub $1, %ebx /* resulting mask is is in ebx */
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/* Set this mask for initial cache fill */
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mov $MSR_L2_QOS_MASK(0), %ecx
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rdmsr
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mov %ebx, %eax
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wrmsr
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/* Set CLOS selector to 0 */
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mov $MSR_IA32_PQR_ASSOC, %ecx
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rdmsr
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and $~MSR_IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */
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wrmsr
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/* We will need to block CAR region from evicts */
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mov $MSR_L2_QOS_MASK(1), %ecx
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rdmsr
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/* Invert bits that are to be used for cache */
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mov %ebx, %eax
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xor $~0, %eax /* invert 32 bits */
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/*
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* Use CBM_LEN_MASK stored in mm3 to set bits based on Capacity Bit
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* Mask Length.
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*/
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movd %mm3, %ebx
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and %ebx, %eax
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wrmsr
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post_code(0x26)
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/* Clear the cache memory region. This will also fill up the cache */
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movl $CONFIG_DCACHE_RAM_BASE, %edi
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movl $CONFIG_DCACHE_RAM_SIZE, %ecx
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shr $0x02, %ecx
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xor %eax, %eax
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cld
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rep stosl
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post_code(0x27)
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/* Cache is populated. Use mask 1 that will block evicts */
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mov $MSR_IA32_PQR_ASSOC, %ecx
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rdmsr
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and $~MSR_IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */
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or $1, %edx /* select mask 1 */
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wrmsr
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/* Enable prefetchers */
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mov $MSR_PREFETCH_CTL, %ecx
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rdmsr
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and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax
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wrmsr
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post_code(0x28)
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jmp car_init_ret
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#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED)
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.global car_nem_enhanced
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car_nem_enhanced:
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/* Disable cache eviction (setup stage) */
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mov $MSR_EVICT_CTL, %ecx
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rdmsr
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or $0x1, %eax
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wrmsr
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post_code(0x26)
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/* Create n-way set associativity of cache */
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xorl %edi, %edi
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find_llc_subleaf:
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movl %edi, %ecx
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movl $0x04, %eax
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cpuid
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inc %edi
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and $0xe0, %al /* EAX[7:5] = Cache Level */
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cmp $0x60, %al /* Check to see if it is LLC */
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jnz find_llc_subleaf
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/*
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* Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE
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* for 4/8/16 way of LLC
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*/
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shr $22, %ebx
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inc %ebx
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/* Calculate n-way associativity of LLC */
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mov %bl, %cl
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/*
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* Maximizing RO cacheability while locking in the CAR to a
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* single way since that particular way won't be victim candidate
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* for evictions.
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* This has been done after programing LLC_WAY_MASK_1 MSR
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* with desired LLC way as mentioned below.
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*
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* Hence create Code and Data Size as per request
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* Code Size (RO) : Up to 16M
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* Data Size (RW) : Up to 256K
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*/
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movl $0x01, %eax
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/*
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* LLC Ways -> LLC_WAY_MASK_1:
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* 4: 0x000E
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* 8: 0x00FE
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* 12: 0x0FFE
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* 16: 0xFFFE
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*
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* These MSRs contain one bit per each way of LLC
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* - If this bit is '0' - the way is protected from eviction
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* - If this bit is '1' - the way is not protected from eviction
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*/
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shl %cl, %eax
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subl $0x02, %eax
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movl $MSR_IA32_L3_MASK_1, %ecx
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xorl %edx, %edx
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wrmsr
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/*
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* Set MSR 0xC92 IA32_L3_MASK_2 = 0x1
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*
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* For SKL SOC, data size remains 256K consistently.
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* Hence, creating 1-way associative cache for Data
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*/
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mov $MSR_IA32_L3_MASK_2, %ecx
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mov $0x01, %eax
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xorl %edx, %edx
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wrmsr
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/*
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* Set MSR_IA32_PQR_ASSOC = 0x02
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*
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* Possible values:
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* 0: Default value, no way mask should be applied
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* 1: Apply way mask 1 to LLC
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* 2: Apply way mask 2 to LLC
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* 3: Shouldn't be use in NEM Mode
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*/
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movl $MSR_IA32_PQR_ASSOC, %ecx
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movl $0x02, %eax
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xorl %edx, %edx
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wrmsr
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movl $CONFIG_DCACHE_RAM_BASE, %edi
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movl $CONFIG_DCACHE_RAM_SIZE, %ecx
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shr $0x02, %ecx
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xor %eax, %eax
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cld
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rep stosl
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/*
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* Set MSR_IA32_PQR_ASSOC = 0x01
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* At this stage we apply LLC_WAY_MASK_1 to the cache.
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* i.e. way 0 is protected from eviction.
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*/
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movl $MSR_IA32_PQR_ASSOC, %ecx
|
||||
movl $0x01, %eax
|
||||
xorl %edx, %edx
|
||||
wrmsr
|
||||
|
||||
post_code(0x27)
|
||||
/*
|
||||
* Enable No-Eviction Mode Run State by setting
|
||||
* NO_EVICT_MODE MSR 2E0h bit [1] = '1'.
|
||||
*/
|
||||
|
||||
movl $MSR_EVICT_CTL, %ecx
|
||||
rdmsr
|
||||
orl $0x02, %eax
|
||||
wrmsr
|
||||
|
||||
post_code(0x28)
|
||||
|
||||
jmp car_init_ret
|
||||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(X86_16BIT_INIT)
|
||||
_dt_ucode_base_size:
|
||||
/* These next two fields are filled in by binman */
|
||||
.globl ucode_base
|
||||
ucode_base: /* Declared in microcode.h */
|
||||
.long 0 /* microcode base */
|
||||
.globl ucode_size
|
||||
ucode_size: /* Declared in microcode.h */
|
||||
.long 0 /* microcode size */
|
||||
.long CONFIG_SYS_MONITOR_BASE /* code region base */
|
||||
.long CONFIG_SYS_MONITOR_LEN /* code region size */
|
||||
#endif
|
||||
87
arch/x86/cpu/intel_common/car2_uninit.S
Normal file
87
arch/x86/cpu/intel_common/car2_uninit.S
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright 2017 Intel Corp.
|
||||
* Copyright 2019 Google LLC
|
||||
* Taken from coreboot file exit_car.S
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/msr-index.h>
|
||||
#include <asm/mtrr.h>
|
||||
|
||||
.text
|
||||
.global car_uninit
|
||||
car_uninit:
|
||||
|
||||
/*
|
||||
* Retrieve return address from stack as it will get trashed below if
|
||||
* execution is utilizing the cache-as-ram stack.
|
||||
*/
|
||||
pop %ebx
|
||||
|
||||
/* Disable MTRRs */
|
||||
mov $(MTRR_DEF_TYPE_MSR), %ecx
|
||||
rdmsr
|
||||
and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax
|
||||
wrmsr
|
||||
|
||||
#ifdef CONFIG_INTEL_CAR_NEM
|
||||
.global car_nem_teardown
|
||||
car_nem_teardown:
|
||||
|
||||
/* invalidate cache contents */
|
||||
invd
|
||||
|
||||
/* Knock down bit 1 then bit 0 of NEM control not combining steps */
|
||||
mov $(MSR_EVICT_CTL), %ecx
|
||||
rdmsr
|
||||
and $(~(1 << 1)), %eax
|
||||
wrmsr
|
||||
and $(~(1 << 0)), %eax
|
||||
wrmsr
|
||||
|
||||
#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
|
||||
.global car_cqos_teardown
|
||||
car_cqos_teardown:
|
||||
|
||||
/* Go back to all-evicting mode, set both masks to all-1s */
|
||||
mov $MSR_L2_QOS_MASK(0), %ecx
|
||||
rdmsr
|
||||
mov $~0, %al
|
||||
wrmsr
|
||||
|
||||
mov $MSR_L2_QOS_MASK(1), %ecx
|
||||
rdmsr
|
||||
mov $~0, %al
|
||||
wrmsr
|
||||
|
||||
/* Reset CLOS selector to 0 */
|
||||
mov $MSR_IA32_PQR_ASSOC, %ecx
|
||||
rdmsr
|
||||
and $~MSR_IA32_PQR_ASSOC_MASK, %edx
|
||||
wrmsr
|
||||
|
||||
#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED)
|
||||
.global car_nem_enhanced_teardown
|
||||
car_nem_enhanced_teardown:
|
||||
|
||||
/* invalidate cache contents */
|
||||
invd
|
||||
|
||||
/* Knock down bit 1 then bit 0 of NEM control not combining steps */
|
||||
mov $(MSR_EVICT_CTL), %ecx
|
||||
rdmsr
|
||||
and $(~(1 << 1)), %eax
|
||||
wrmsr
|
||||
and $(~(1 << 0)), %eax
|
||||
wrmsr
|
||||
|
||||
/* Reset CLOS selector to 0 */
|
||||
mov $IA32_PQR_ASSOC, %ecx
|
||||
rdmsr
|
||||
and $~IA32_PQR_ASSOC_MASK, %edx
|
||||
wrmsr
|
||||
#endif
|
||||
|
||||
/* Return to caller */
|
||||
jmp *%ebx
|
||||
|
|
@ -25,8 +25,6 @@
|
|||
/* Length of the public header on Intel microcode blobs */
|
||||
#define UCODE_HEADER_LEN 0x30
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/*
|
||||
* This register is documented in (for example) the Intel Atom Processor E3800
|
||||
* Product Family Datasheet in "PCU - Power Management Controller (PMC)".
|
||||
|
|
@ -37,11 +35,11 @@
|
|||
*/
|
||||
#define IO_PORT_RESET 0xcf9
|
||||
|
||||
enum {
|
||||
SYS_RST = 1 << 1, /* 0 for soft reset, 1 for hard reset */
|
||||
RST_CPU = 1 << 2, /* initiate reset */
|
||||
FULL_RST = 1 << 3, /* full power cycle */
|
||||
};
|
||||
#define SYS_RST (1 << 1) /* 0 for soft reset, 1 for hard reset */
|
||||
#define RST_CPU (1 << 2) /* initiate reset */
|
||||
#define FULL_RST (1 << 3) /* full power cycle */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
static inline __attribute__((always_inline)) void cpu_hlt(void)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue