mirror of
https://github.com/AsahiLinux/u-boot
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x86: apl: Add FSP support
The memory and silicon init parts of the FSP need support code to work. Add this for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
parent
a9a4b685de
commit
2153e8fbfc
3 changed files with 877 additions and 0 deletions
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@ -10,6 +10,12 @@ obj-y += cpu_common.o
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ifndef CONFIG_TPL_BUILD
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obj-y += cpu.o
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obj-y += punit.o
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ifdef CONFIG_SPL_BUILD
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obj-y += fsp_m.o
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endif
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endif
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ifndef CONFIG_SPL_BUILD
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obj-y += fsp_s.o
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endif
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obj-y += hostbridge.o
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210
arch/x86/cpu/apollolake/fsp_m.c
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210
arch/x86/cpu/apollolake/fsp_m.c
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@ -0,0 +1,210 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Google LLC
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/arch/iomap.h>
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#include <asm/arch/fsp/fsp_configs.h>
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#include <asm/arch/fsp/fsp_m_upd.h>
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#include <asm/fsp2/fsp_internal.h>
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#include <dm/uclass-internal.h>
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/*
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* ODT settings:
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* If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A and HIGH for ODT_B,
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* choose ODT_A_B_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A
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* and LOW for ODT_B, choose ODT_A_B_HIGH_LOW.
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*
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* Note that the enum values correspond to the interpreted UPD fields
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* within Ch[3:0]_OdtConfig parameters.
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*/
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enum {
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ODT_A_B_HIGH_LOW = 0 << 1,
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ODT_A_B_HIGH_HIGH = 1 << 1,
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N_WR_24 = 1 << 5,
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};
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/*
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* LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation.
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* There are four physical LPDDR4 channels, each 32-bits wide. There are two
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* logical channels using two physical channels together to form a 64-bit
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* interface to memory for each logical channel.
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*/
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enum {
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LP4_PHYS_CH0A,
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LP4_PHYS_CH0B,
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LP4_PHYS_CH1A,
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LP4_PHYS_CH1B,
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LP4_NUM_PHYS_CHANNELS,
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};
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/*
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* The DQs within a physical channel can be bit-swizzled within each byte.
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* Within a channel the bytes can be swapped, but the DQs need to be routed
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* with the corresponding DQS (strobe).
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*/
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enum {
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LP4_DQS0,
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LP4_DQS1,
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LP4_DQS2,
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LP4_DQS3,
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LP4_NUM_BYTE_LANES,
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DQ_BITS_PER_DQS = 8,
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};
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/* Provide bit swizzling per DQS and byte swapping within a channel */
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struct lpddr4_chan_swizzle_cfg {
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u8 dqs[LP4_NUM_BYTE_LANES][DQ_BITS_PER_DQS];
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};
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struct lpddr4_swizzle_cfg {
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struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS];
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};
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static void setup_sdram(struct fsp_m_config *cfg,
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const struct lpddr4_swizzle_cfg *swizzle_cfg)
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{
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const struct lpddr4_chan_swizzle_cfg *sch;
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/* Number of bytes to copy per DQS */
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const size_t sz = DQ_BITS_PER_DQS;
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int chan;
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cfg->memory_down = 1;
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cfg->scrambler_support = 1;
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cfg->channel_hash_mask = 0x36;
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cfg->slice_hash_mask = 9;
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cfg->interleaved_mode = 2;
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cfg->channels_slices_enable = 0;
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cfg->min_ref_rate2x_enable = 0;
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cfg->dual_rank_support_enable = 1;
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/* LPDDR4 is memory down so no SPD addresses */
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cfg->dimm0_spd_address = 0;
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cfg->dimm1_spd_address = 0;
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for (chan = 0; chan < 4; chan++) {
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struct fsp_ram_channel *ch = &cfg->chan[chan];
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ch->rank_enable = 1;
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ch->device_width = 1;
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ch->dram_density = 2;
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ch->option = 3;
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ch->odt_config = ODT_A_B_HIGH_HIGH;
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}
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/*
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* CH0_DQB byte lanes in the bit swizzle configuration field are
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* not 1:1. The mapping within the swizzling field is:
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* indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
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* indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
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* indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
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* indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
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*/
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sch = &swizzle_cfg->phys[LP4_PHYS_CH0B];
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memcpy(&cfg->ch_bit_swizzling[0][0], &sch->dqs[LP4_DQS1], sz);
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memcpy(&cfg->ch_bit_swizzling[0][8], &sch->dqs[LP4_DQS0], sz);
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memcpy(&cfg->ch_bit_swizzling[0][16], &sch->dqs[LP4_DQS3], sz);
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memcpy(&cfg->ch_bit_swizzling[0][24], &sch->dqs[LP4_DQS2], sz);
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/*
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* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
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*/
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sch = &swizzle_cfg->phys[LP4_PHYS_CH0A];
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memcpy(&cfg->ch_bit_swizzling[1][0], &sch->dqs[LP4_DQS0], sz);
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memcpy(&cfg->ch_bit_swizzling[1][8], &sch->dqs[LP4_DQS1], sz);
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memcpy(&cfg->ch_bit_swizzling[1][16], &sch->dqs[LP4_DQS2], sz);
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memcpy(&cfg->ch_bit_swizzling[1][24], &sch->dqs[LP4_DQS3], sz);
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sch = &swizzle_cfg->phys[LP4_PHYS_CH1B];
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memcpy(&cfg->ch_bit_swizzling[2][0], &sch->dqs[LP4_DQS1], sz);
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memcpy(&cfg->ch_bit_swizzling[2][8], &sch->dqs[LP4_DQS0], sz);
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memcpy(&cfg->ch_bit_swizzling[2][16], &sch->dqs[LP4_DQS3], sz);
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memcpy(&cfg->ch_bit_swizzling[2][24], &sch->dqs[LP4_DQS2], sz);
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/*
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* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
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*/
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sch = &swizzle_cfg->phys[LP4_PHYS_CH1A];
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memcpy(&cfg->ch_bit_swizzling[3][0], &sch->dqs[LP4_DQS0], sz);
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memcpy(&cfg->ch_bit_swizzling[3][8], &sch->dqs[LP4_DQS1], sz);
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memcpy(&cfg->ch_bit_swizzling[3][16], &sch->dqs[LP4_DQS2], sz);
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memcpy(&cfg->ch_bit_swizzling[3][24], &sch->dqs[LP4_DQS3], sz);
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}
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int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
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{
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struct fsp_m_config *cfg = &upd->config;
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struct fspm_arch_upd *arch = &upd->arch;
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arch->nvs_buffer_ptr = NULL;
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prepare_mrc_cache(upd);
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arch->stack_base = (void *)0xfef96000;
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arch->boot_loader_tolum_size = 0;
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arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION;
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cfg->serial_debug_port_type = 2;
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cfg->serial_debug_port_device = 2;
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cfg->serial_debug_port_stride_size = 2;
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cfg->serial_debug_port_address = 0;
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cfg->package = 1;
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/* Don't enforce a memory size limit */
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cfg->memory_size_limit = 0;
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cfg->low_memory_max_value = 2048; /* 2 GB */
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/* No restrictions on memory above 4GiB */
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cfg->high_memory_max_value = 0;
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/* Always default to attempt to use saved training data */
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cfg->disable_fast_boot = 0;
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const u8 *swizzle_data;
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swizzle_data = dev_read_u8_array_ptr(dev, "lpddr4-swizzle",
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LP4_NUM_BYTE_LANES *
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DQ_BITS_PER_DQS *
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LP4_NUM_PHYS_CHANNELS);
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if (!swizzle_data)
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return log_msg_ret("Cannot read swizzel data", -EINVAL);
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setup_sdram(cfg, (struct lpddr4_swizzle_cfg *)swizzle_data);
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cfg->pre_mem_gpio_table_ptr = 0;
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cfg->profile = 0xb;
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cfg->msg_level_mask = 0;
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/* other */
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cfg->skip_cse_rbp = 1;
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cfg->periodic_retraining_disable = 0;
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cfg->enable_s3_heci2 = 0;
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return 0;
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}
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/*
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* The FSP-M binary appears to break the SPI controller. It can be fixed by
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* writing the BAR again, so do that here
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*/
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int fspm_done(struct udevice *dev)
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{
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struct udevice *spi;
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int ret;
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/* Don't probe the device, since that reads the BAR */
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ret = uclass_find_first_device(UCLASS_SPI, &spi);
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if (ret)
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return log_msg_ret("SPI", ret);
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if (!spi)
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return log_msg_ret("no SPI", -ENODEV);
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dm_pci_write_config32(spi, PCI_BASE_ADDRESS_0,
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IOMAP_SPI_BASE | PCI_BASE_ADDRESS_SPACE_MEMORY);
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return 0;
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}
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661
arch/x86/cpu/apollolake/fsp_s.c
Normal file
661
arch/x86/cpu/apollolake/fsp_s.c
Normal file
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@ -0,0 +1,661 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Google LLC
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <common.h>
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#include <acpi_s3.h>
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#include <binman.h>
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#include <dm.h>
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#include <irq.h>
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#include <asm/intel_pinctrl.h>
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#include <asm/io.h>
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#include <asm/intel_regs.h>
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#include <asm/msr.h>
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#include <asm/msr-index.h>
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#include <asm/pci.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/systemagent.h>
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#include <asm/arch/fsp/fsp_configs.h>
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#include <asm/arch/fsp/fsp_s_upd.h>
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#define PCH_P2SB_E0 0xe0
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#define HIDE_BIT BIT(0)
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#define INTEL_GSPI_MAX 3
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#define INTEL_I2C_DEV_MAX 8
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#define MAX_USB2_PORTS 8
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enum {
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CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
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CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
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};
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enum i2c_speed {
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I2C_SPEED_STANDARD = 100000,
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I2C_SPEED_FAST = 400000,
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I2C_SPEED_FAST_PLUS = 1000000,
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I2C_SPEED_HIGH = 3400000,
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I2C_SPEED_FAST_ULTRA = 5000000,
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};
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/*
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* Timing values are in units of clock period, with the clock speed
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* provided by the SOC
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*
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* TODO(sjg@chromium.org): Connect this up to the I2C driver
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*/
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struct dw_i2c_speed_config {
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enum i2c_speed speed;
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/* SCL high and low period count */
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u16 scl_lcnt;
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u16 scl_hcnt;
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/*
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* SDA hold time should be 300ns in standard and fast modes
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* and long enough for deterministic logic level change in
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* fast-plus and high speed modes.
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*
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* [15:0] SDA TX Hold Time
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* [23:16] SDA RX Hold Time
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*/
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u32 sda_hold;
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};
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/* Serial IRQ control. SERIRQ_QUIET is the default (0) */
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enum serirq_mode {
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SERIRQ_QUIET,
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SERIRQ_CONTINUOUS,
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SERIRQ_OFF,
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};
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/*
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* This I2C controller has support for 3 independent speed configs but can
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* support both FAST_PLUS and HIGH speeds through the same set of speed
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* config registers. These are treated separately so the speed config values
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* can be provided via ACPI to the OS.
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*/
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#define DW_I2C_SPEED_CONFIG_COUNT 4
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struct dw_i2c_bus_config {
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/* Bus should be enabled in TPL with temporary base */
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int early_init;
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/* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
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enum i2c_speed speed;
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/*
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* If rise_time_ns is non-zero the calculations for lcnt and hcnt
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* registers take into account the times of the bus. However, if
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* there is a match in speed_config those register values take
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* precedence
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*/
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int rise_time_ns;
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int fall_time_ns;
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int data_hold_time_ns;
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/* Specific bus speed configuration */
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struct dw_i2c_speed_config speed_config[DW_I2C_SPEED_CONFIG_COUNT];
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};
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struct gspi_cfg {
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/* Bus speed in MHz */
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u32 speed_mhz;
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/* Bus should be enabled prior to ramstage with temporary base */
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u8 early_init;
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};
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/*
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* This structure will hold data required by common blocks.
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* These are soc specific configurations which will be filled by soc.
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* We'll fill this structure once during init and use the data in common block.
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*/
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struct soc_intel_common_config {
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int chipset_lockdown;
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struct gspi_cfg gspi[INTEL_GSPI_MAX];
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struct dw_i2c_bus_config i2c[INTEL_I2C_DEV_MAX];
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};
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enum pnp_settings {
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PNP_PERF,
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PNP_POWER,
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PNP_PERF_POWER,
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};
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struct usb2_eye_per_port {
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u8 per_port_tx_pe_half;
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u8 per_port_pe_txi_set;
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u8 per_port_txi_set;
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u8 hs_skew_sel;
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u8 usb_tx_emphasis_en;
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u8 per_port_rxi_set;
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u8 hs_npre_drv_sel;
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u8 override_en;
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};
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struct apl_config {
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/* Common structure containing soc config data required by common code*/
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struct soc_intel_common_config common_soc_config;
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/*
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* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
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* four CLKREQ inputs, but six root ports. Root ports without an
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* associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
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*/
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u8 pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
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/* Enable/disable hot-plug for root ports (0 = disable, 1 = enable) */
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u8 pcie_rp_hotplug_enable[MAX_PCIE_PORTS];
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/* De-emphasis enable configuration for each PCIe root port */
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u8 pcie_rp_deemphasis_enable[MAX_PCIE_PORTS];
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/*
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* [14:8] DDR mode Number of dealy elements.Each = 125pSec.
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* [6:0] SDR mode Number of dealy elements.Each = 125pSec.
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*/
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u32 emmc_tx_cmd_cntl;
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/*
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* [14:8] HS400 mode Number of dealy elements.Each = 125pSec.
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* [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec.
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*/
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u32 emmc_tx_data_cntl1;
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/*
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* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
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* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
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* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
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* [6:0] SDR12/Compatibility mode Number of dealy elements.
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* Each = 125pSec.
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*/
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u32 emmc_tx_data_cntl2;
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/*
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* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
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* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
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* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
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* [6:0] SDR12/Compatibility mode Number of dealy elements.
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* Each = 125pSec.
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*/
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u32 emmc_rx_cmd_data_cntl1;
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/*
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* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec.
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* [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec.
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*/
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u32 emmc_rx_strobe_cntl;
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/*
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* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec.
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* [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec.
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*/
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u32 emmc_rx_cmd_data_cntl2;
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/* Select the eMMC max speed allowed */
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u32 emmc_host_max_speed;
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/* Specifies on which IRQ the SCI will internally appear */
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u32 sci_irq;
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/* Configure serial IRQ (SERIRQ) line */
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enum serirq_mode serirq_mode;
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/* Configure LPSS S0ix Enable */
|
||||
bool lpss_s0ix_enable;
|
||||
|
||||
/* Enable DPTF support */
|
||||
bool dptf_enable;
|
||||
|
||||
/* TCC activation offset value in degrees Celsius */
|
||||
int tcc_offset;
|
||||
|
||||
/*
|
||||
* Configure Audio clk gate and power gate
|
||||
* IOSF-SB port ID 92 offset 0x530 [5] and [3]
|
||||
*/
|
||||
bool hdaudio_clk_gate_enable;
|
||||
bool hdaudio_pwr_gate_enable;
|
||||
bool hdaudio_bios_config_lockdown;
|
||||
|
||||
/* SLP S3 minimum assertion width */
|
||||
int slp_s3_assertion_width_usecs;
|
||||
|
||||
/* GPIO pin for PERST_0 */
|
||||
u32 prt0_gpio;
|
||||
|
||||
/* USB2 eye diagram settings per port */
|
||||
struct usb2_eye_per_port usb2eye[MAX_USB2_PORTS];
|
||||
|
||||
/* GPIO SD card detect pin */
|
||||
unsigned int sdcard_cd_gpio;
|
||||
|
||||
/*
|
||||
* PRMRR size setting with three options
|
||||
* 0x02000000 - 32MiB
|
||||
* 0x04000000 - 64MiB
|
||||
* 0x08000000 - 128MiB
|
||||
*/
|
||||
u32 PrmrrSize;
|
||||
|
||||
/*
|
||||
* Enable SGX feature.
|
||||
* Enabling SGX feature is 2 step process,
|
||||
* (1) set sgx_enable = 1
|
||||
* (2) set PrmrrSize to supported size
|
||||
*/
|
||||
bool sgx_enable;
|
||||
|
||||
/*
|
||||
* Select PNP Settings.
|
||||
* (0) Performance,
|
||||
* (1) Power
|
||||
* (2) Power & Performance
|
||||
*/
|
||||
enum pnp_settings pnp_settings;
|
||||
|
||||
/*
|
||||
* PMIC PCH_PWROK delay configuration - IPC Configuration
|
||||
* Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address
|
||||
* (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0)
|
||||
*/
|
||||
u32 pmic_pmc_ipc_ctrl;
|
||||
|
||||
/*
|
||||
* Options to disable XHCI Link Compliance Mode. Default is FALSE to not
|
||||
* disable Compliance Mode. Set TRUE to disable Compliance Mode.
|
||||
* 0:FALSE(Default), 1:True.
|
||||
*/
|
||||
bool disable_compliance_mode;
|
||||
|
||||
/*
|
||||
* Options to change USB3 ModPhy setting for the Integrated Filter (IF)
|
||||
* value. Default is 0 to not changing default IF value (0x12). Set
|
||||
* value with the range from 0x01 to 0xff to change IF value.
|
||||
*/
|
||||
u32 mod_phy_if_value;
|
||||
|
||||
/*
|
||||
* Options to bump USB3 LDO voltage. Default is FALSE to not increasing
|
||||
* LDO voltage. Set TRUE to increase LDO voltage with 40mV.
|
||||
* 0:FALSE (default), 1:True.
|
||||
*/
|
||||
bool mod_phy_voltage_bump;
|
||||
|
||||
/*
|
||||
* Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting
|
||||
* the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage
|
||||
* configuration: I2C_Slave_Address (31:23) + Register_Offset (23:16)
|
||||
* + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]:
|
||||
* 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default).
|
||||
*/
|
||||
u32 pmic_vdd2_voltage;
|
||||
|
||||
/* Option to enable VTD feature */
|
||||
bool enable_vtd;
|
||||
};
|
||||
|
||||
static int get_config(struct udevice *dev, struct apl_config *apl)
|
||||
{
|
||||
const u8 *ptr;
|
||||
ofnode node;
|
||||
u32 emmc[4];
|
||||
int ret;
|
||||
|
||||
memset(apl, '\0', sizeof(*apl));
|
||||
|
||||
node = dev_read_subnode(dev, "fsp-s");
|
||||
if (!ofnode_valid(node))
|
||||
return log_msg_ret("fsp-s settings", -ENOENT);
|
||||
|
||||
ptr = ofnode_read_u8_array_ptr(node, "pcie-rp-clkreq-pin",
|
||||
MAX_PCIE_PORTS);
|
||||
if (!ptr)
|
||||
return log_msg_ret("pcie-rp-clkreq-pin", -EINVAL);
|
||||
memcpy(apl->pcie_rp_clkreq_pin, ptr, MAX_PCIE_PORTS);
|
||||
|
||||
ret = ofnode_read_u32(node, "prt0-gpio", &apl->prt0_gpio);
|
||||
if (ret)
|
||||
return log_msg_ret("prt0-gpio", ret);
|
||||
ret = ofnode_read_u32(node, "sdcard-cd-gpio", &apl->sdcard_cd_gpio);
|
||||
if (ret)
|
||||
return log_msg_ret("sdcard-cd-gpio", ret);
|
||||
|
||||
ret = ofnode_read_u32_array(node, "emmc", emmc, ARRAY_SIZE(emmc));
|
||||
if (ret)
|
||||
return log_msg_ret("emmc", ret);
|
||||
apl->emmc_tx_data_cntl1 = emmc[0];
|
||||
apl->emmc_tx_data_cntl2 = emmc[1];
|
||||
apl->emmc_rx_cmd_data_cntl1 = emmc[2];
|
||||
apl->emmc_rx_cmd_data_cntl2 = emmc[3];
|
||||
|
||||
apl->dptf_enable = ofnode_read_bool(node, "dptf-enable");
|
||||
|
||||
apl->hdaudio_clk_gate_enable = ofnode_read_bool(node,
|
||||
"hdaudio-clk-gate-enable");
|
||||
apl->hdaudio_pwr_gate_enable = ofnode_read_bool(node,
|
||||
"hdaudio-pwr-gate-enable");
|
||||
apl->hdaudio_bios_config_lockdown = ofnode_read_bool(node,
|
||||
"hdaudio-bios-config-lockdown");
|
||||
apl->lpss_s0ix_enable = ofnode_read_bool(node, "lpss-s0ix-enable");
|
||||
|
||||
/* Santa */
|
||||
apl->usb2eye[1].per_port_pe_txi_set = 7;
|
||||
apl->usb2eye[1].per_port_txi_set = 2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void apl_fsp_silicon_init_params_cb(struct apl_config *apl,
|
||||
struct fsp_s_config *cfg)
|
||||
{
|
||||
u8 port;
|
||||
|
||||
for (port = 0; port < MAX_USB2_PORTS; port++) {
|
||||
if (apl->usb2eye[port].per_port_tx_pe_half)
|
||||
cfg->port_usb20_per_port_tx_pe_half[port] =
|
||||
apl->usb2eye[port].per_port_tx_pe_half;
|
||||
|
||||
if (apl->usb2eye[port].per_port_pe_txi_set)
|
||||
cfg->port_usb20_per_port_pe_txi_set[port] =
|
||||
apl->usb2eye[port].per_port_pe_txi_set;
|
||||
|
||||
if (apl->usb2eye[port].per_port_txi_set)
|
||||
cfg->port_usb20_per_port_txi_set[port] =
|
||||
apl->usb2eye[port].per_port_txi_set;
|
||||
|
||||
if (apl->usb2eye[port].hs_skew_sel)
|
||||
cfg->port_usb20_hs_skew_sel[port] =
|
||||
apl->usb2eye[port].hs_skew_sel;
|
||||
|
||||
if (apl->usb2eye[port].usb_tx_emphasis_en)
|
||||
cfg->port_usb20_i_usb_tx_emphasis_en[port] =
|
||||
apl->usb2eye[port].usb_tx_emphasis_en;
|
||||
|
||||
if (apl->usb2eye[port].per_port_rxi_set)
|
||||
cfg->port_usb20_per_port_rxi_set[port] =
|
||||
apl->usb2eye[port].per_port_rxi_set;
|
||||
|
||||
if (apl->usb2eye[port].hs_npre_drv_sel)
|
||||
cfg->port_usb20_hs_npre_drv_sel[port] =
|
||||
apl->usb2eye[port].hs_npre_drv_sel;
|
||||
}
|
||||
}
|
||||
|
||||
int fsps_update_config(struct udevice *dev, ulong rom_offset,
|
||||
struct fsps_upd *upd)
|
||||
{
|
||||
struct fsp_s_config *cfg = &upd->config;
|
||||
struct apl_config *apl;
|
||||
struct binman_entry vbt;
|
||||
void *buf;
|
||||
int ret;
|
||||
|
||||
ret = binman_entry_find("intel-vbt", &vbt);
|
||||
if (ret)
|
||||
return log_msg_ret("Cannot find VBT", ret);
|
||||
vbt.image_pos += rom_offset;
|
||||
buf = malloc(vbt.size);
|
||||
if (!buf)
|
||||
return log_msg_ret("Alloc VBT", -ENOMEM);
|
||||
|
||||
/*
|
||||
* Load VBT before devicetree-specific config. This only supports
|
||||
* memory-mapped SPI at present.
|
||||
*/
|
||||
bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
|
||||
memcpy(buf, (void *)vbt.image_pos, vbt.size);
|
||||
bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
|
||||
if (*(u32 *)buf != VBT_SIGNATURE)
|
||||
return log_msg_ret("VBT signature", -EINVAL);
|
||||
cfg->graphics_config_ptr = (ulong)buf;
|
||||
|
||||
apl = malloc(sizeof(*apl));
|
||||
if (!apl)
|
||||
return log_msg_ret("config", -ENOMEM);
|
||||
get_config(dev, apl);
|
||||
|
||||
cfg->ish_enable = 0;
|
||||
cfg->enable_sata = 0;
|
||||
cfg->pcie_root_port_en[2] = 0;
|
||||
cfg->pcie_rp_hot_plug[2] = 0;
|
||||
cfg->pcie_root_port_en[3] = 0;
|
||||
cfg->pcie_rp_hot_plug[3] = 0;
|
||||
cfg->pcie_root_port_en[4] = 0;
|
||||
cfg->pcie_rp_hot_plug[4] = 0;
|
||||
cfg->pcie_root_port_en[5] = 0;
|
||||
cfg->pcie_rp_hot_plug[5] = 0;
|
||||
cfg->pcie_root_port_en[1] = 0;
|
||||
cfg->pcie_rp_hot_plug[1] = 0;
|
||||
cfg->usb_otg = 0;
|
||||
cfg->i2c6_enable = 0;
|
||||
cfg->i2c7_enable = 0;
|
||||
cfg->hsuart3_enable = 0;
|
||||
cfg->spi1_enable = 0;
|
||||
cfg->spi2_enable = 0;
|
||||
cfg->sdio_enabled = 0;
|
||||
|
||||
memcpy(cfg->pcie_rp_clk_req_number, apl->pcie_rp_clkreq_pin,
|
||||
sizeof(cfg->pcie_rp_clk_req_number));
|
||||
|
||||
memcpy(cfg->pcie_rp_hot_plug, apl->pcie_rp_hotplug_enable,
|
||||
sizeof(cfg->pcie_rp_hot_plug));
|
||||
|
||||
switch (apl->serirq_mode) {
|
||||
case SERIRQ_QUIET:
|
||||
cfg->sirq_enable = 1;
|
||||
cfg->sirq_mode = 0;
|
||||
break;
|
||||
case SERIRQ_CONTINUOUS:
|
||||
cfg->sirq_enable = 1;
|
||||
cfg->sirq_mode = 1;
|
||||
break;
|
||||
case SERIRQ_OFF:
|
||||
default:
|
||||
cfg->sirq_enable = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
if (apl->emmc_tx_cmd_cntl)
|
||||
cfg->emmc_tx_cmd_cntl = apl->emmc_tx_cmd_cntl;
|
||||
if (apl->emmc_tx_data_cntl1)
|
||||
cfg->emmc_tx_data_cntl1 = apl->emmc_tx_data_cntl1;
|
||||
if (apl->emmc_tx_data_cntl2)
|
||||
cfg->emmc_tx_data_cntl2 = apl->emmc_tx_data_cntl2;
|
||||
if (apl->emmc_rx_cmd_data_cntl1)
|
||||
cfg->emmc_rx_cmd_data_cntl1 = apl->emmc_rx_cmd_data_cntl1;
|
||||
if (apl->emmc_rx_strobe_cntl)
|
||||
cfg->emmc_rx_strobe_cntl = apl->emmc_rx_strobe_cntl;
|
||||
if (apl->emmc_rx_cmd_data_cntl2)
|
||||
cfg->emmc_rx_cmd_data_cntl2 = apl->emmc_rx_cmd_data_cntl2;
|
||||
if (apl->emmc_host_max_speed)
|
||||
cfg->e_mmc_host_max_speed = apl->emmc_host_max_speed;
|
||||
|
||||
cfg->lpss_s0ix_enable = apl->lpss_s0ix_enable;
|
||||
|
||||
cfg->skip_mp_init = true;
|
||||
|
||||
/* Disable setting of EISS bit in FSP */
|
||||
cfg->spi_eiss = 0;
|
||||
|
||||
/* Disable FSP from locking access to the RTC NVRAM */
|
||||
cfg->rtc_lock = 0;
|
||||
|
||||
/* Enable Audio clk gate and power gate */
|
||||
cfg->hd_audio_clk_gate = apl->hdaudio_clk_gate_enable;
|
||||
cfg->hd_audio_pwr_gate = apl->hdaudio_pwr_gate_enable;
|
||||
/* Bios config lockdown Audio clk and power gate */
|
||||
cfg->bios_cfg_lock_down = apl->hdaudio_bios_config_lockdown;
|
||||
apl_fsp_silicon_init_params_cb(apl, cfg);
|
||||
|
||||
cfg->usb_otg = true;
|
||||
cfg->vtd_enable = apl->enable_vtd;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void p2sb_set_hide_bit(pci_dev_t dev, int hide)
|
||||
{
|
||||
pci_x86_clrset_config(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
|
||||
hide ? HIDE_BIT : 0, PCI_SIZE_8);
|
||||
}
|
||||
|
||||
/* Configure package power limits */
|
||||
static int set_power_limits(struct udevice *dev)
|
||||
{
|
||||
msr_t rapl_msr_reg, limit;
|
||||
u32 power_unit;
|
||||
u32 tdp, min_power, max_power;
|
||||
u32 pl2_val;
|
||||
u32 override_tdp[2];
|
||||
int ret;
|
||||
|
||||
/* Get units */
|
||||
rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU_UNIT);
|
||||
power_unit = 1 << (rapl_msr_reg.lo & 0xf);
|
||||
|
||||
/* Get power defaults for this SKU */
|
||||
rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU);
|
||||
tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK;
|
||||
pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
|
||||
min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK;
|
||||
max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
|
||||
|
||||
if (min_power > 0 && tdp < min_power)
|
||||
tdp = min_power;
|
||||
|
||||
if (max_power > 0 && tdp > max_power)
|
||||
tdp = max_power;
|
||||
|
||||
ret = dev_read_u32_array(dev, "tdp-pl-override-mw", override_tdp,
|
||||
ARRAY_SIZE(override_tdp));
|
||||
if (ret)
|
||||
return log_msg_ret("tdp-pl-override-mw", ret);
|
||||
|
||||
/* Set PL1 override value */
|
||||
if (override_tdp[0])
|
||||
tdp = override_tdp[0] * power_unit / 1000;
|
||||
|
||||
/* Set PL2 override value */
|
||||
if (override_tdp[1])
|
||||
pl2_val = override_tdp[1] * power_unit / 1000;
|
||||
|
||||
/* Set long term power limit to TDP */
|
||||
limit.lo = tdp & PKG_POWER_LIMIT_MASK;
|
||||
/* Set PL1 Pkg Power clamp bit */
|
||||
limit.lo |= PKG_POWER_LIMIT_CLAMP;
|
||||
|
||||
limit.lo |= PKG_POWER_LIMIT_EN;
|
||||
limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT &
|
||||
PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT;
|
||||
|
||||
/* Set short term power limit PL2 */
|
||||
limit.hi = pl2_val & PKG_POWER_LIMIT_MASK;
|
||||
limit.hi |= PKG_POWER_LIMIT_EN;
|
||||
|
||||
/* Program package power limits in RAPL MSR */
|
||||
msr_write(MSR_PKG_POWER_LIMIT, limit);
|
||||
log_info("RAPL PL1 %d.%dW\n", tdp / power_unit,
|
||||
100 * (tdp % power_unit) / power_unit);
|
||||
log_info("RAPL PL2 %d.%dW\n", pl2_val / power_unit,
|
||||
100 * (pl2_val % power_unit) / power_unit);
|
||||
|
||||
/*
|
||||
* Sett RAPL MMIO register for Power limits. RAPL driver is using MSR
|
||||
* instead of MMIO, so disable LIMIT_EN bit for MMIO
|
||||
*/
|
||||
writel(limit.lo & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL));
|
||||
writel(limit.hi & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL + 4));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int p2sb_unhide(void)
|
||||
{
|
||||
pci_dev_t dev = PCI_BDF(0, 0xd, 0);
|
||||
ulong val;
|
||||
|
||||
p2sb_set_hide_bit(dev, 0);
|
||||
|
||||
pci_x86_read_config(dev, PCI_VENDOR_ID, &val, PCI_SIZE_16);
|
||||
|
||||
if (val != PCI_VENDOR_ID_INTEL)
|
||||
return log_msg_ret("p2sb unhide", -EIO);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Overwrites the SCI IRQ if another IRQ number is given by device tree */
|
||||
static void set_sci_irq(void)
|
||||
{
|
||||
/* Skip this for now */
|
||||
}
|
||||
|
||||
int arch_fsps_preinit(void)
|
||||
{
|
||||
struct udevice *itss;
|
||||
int ret;
|
||||
|
||||
ret = uclass_first_device_err(UCLASS_IRQ, &itss);
|
||||
if (ret)
|
||||
return log_msg_ret("no itss", ret);
|
||||
/*
|
||||
* Snapshot the current GPIO IRQ polarities. FSP is setting a default
|
||||
* policy that doesn't honour boards' requirements
|
||||
*/
|
||||
irq_snapshot_polarities(itss);
|
||||
|
||||
/*
|
||||
* Clear the GPI interrupt status and enable registers. These
|
||||
* registers do not get reset to default state when booting from S5.
|
||||
*/
|
||||
ret = pinctrl_gpi_clear_int_cfg();
|
||||
if (ret)
|
||||
return log_msg_ret("gpi_clear", ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_fsp_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_HAVE_ACPI_RESUME
|
||||
bool s3wake = gd->arch.prev_sleep_state == ACPI_S3;
|
||||
#else
|
||||
bool s3wake = false;
|
||||
#endif
|
||||
struct udevice *dev, *itss;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* This must be called before any devices are probed. Put any probing
|
||||
* into arch_fsps_preinit() above.
|
||||
*
|
||||
* We don't use CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH here since it will
|
||||
* force PCI to be probed.
|
||||
*/
|
||||
ret = fsp_silicon_init(s3wake, false);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = uclass_first_device_err(UCLASS_IRQ, &itss);
|
||||
if (ret)
|
||||
return log_msg_ret("no itss", ret);
|
||||
/* Restore GPIO IRQ polarities back to previous settings */
|
||||
irq_restore_polarities(itss);
|
||||
|
||||
/* soc_init() */
|
||||
ret = p2sb_unhide();
|
||||
if (ret)
|
||||
return log_msg_ret("unhide p2sb", ret);
|
||||
|
||||
/* Set RAPL MSR for Package power limits*/
|
||||
ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
|
||||
if (ret)
|
||||
return log_msg_ret("Cannot get northbridge", ret);
|
||||
set_power_limits(dev);
|
||||
|
||||
/*
|
||||
* FSP-S routes SCI to IRQ 9. With the help of this function you can
|
||||
* select another IRQ for SCI.
|
||||
*/
|
||||
set_sci_irq();
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in a new issue