By providing entries in the binman node of the device tree, binman will
be able to find and package board config artifacts generated by
TIBoardConfig with sysfw.bin and generate the final image sysfw.itb.
It will also pick out the R5 SPL and sign it with the help of TI signing
entry and generate the final tiboot3.bin.
Entries for A72 build have been added to k3-j721e-binman.dtsi to
generate tispl.bin and u-boot.img.
Support has been added for both HS-SE(SR 1.1), HS-FS(SR 2.0) and GP images
In HS-SE, the encrypted system firmware binary must be signed along with
the signed certificate binary.
HS-SE:
* tiboot3-j721e_sr1_1-hs-evm.bin
* sysfw-j721e_sr1_1-hs-evm.itb
* tispl.bin
* u-boot.img
HS-FS:
* tiboot3-j721e_sr2-hs-fs-evm.bin
* sysfw-j721e_sr2-hs-fs-evm.itb
* tispl.bin
* u-boot.img
GP:
* tiboot3.bin -->tiboot3-j721e-gp-evm.bin
* sysfw.itb --> sysfw-j721e-gp-evm.itb
* tispl.bin_unsigned
* u-boot.img_unsigned
It is to be noted that the bootflow followed by J721E requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
sysfw.itb:
* TIFS
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* DM
* ATF
* OP-TEE
* A72 SPL
* A72 SPL dtbs
u-boot.img:
* A72 U-Boot
* A72 U-Boot dtbs
Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Board config binary artifacts must be generated to be used by binman to
package sysfw.itb and tiboot3.bin for all K3 devices.
For devices that follow combined flow, these board configuration
binaries must again be packaged into a combined board configuration
blobs to be used by binman to package tiboot3.bin.
Add common k3-binman.dtsi to generate all the board configuration
binaries needed.
Also add custMpk.pem and ti-degenerate-key.pem needed for signing GP and
HS bootloader images common to all K3 devices.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
axi_emac:
- Change return value if RX packet is not ready
cadence_qspi:
- Enable flash reset for Versal NET
dt:
- Various DT syncups with Linux kernel
- SOM - reserved pmufw memory location
fpga:
- Add load event
mtd:
- Add missing dependency for FLASH_CFI_MTD
spi/nand:
- Minor cleanup in Xilinx drivers
versal-net:
- Prioritize boot device in boot_targets
- Wire mini ospi/qspi/emmc configurations
watchdog:
- Use new versal-wwdt property
xilinx:
- fix sparse warnings in various places ps7_init*
- add missing headers
- consolidate code around zynqmp_mmio_read/write
- switch to amd.com email
zynqmp_clk:
- Add handling for gem rx/tsu clocks
zynq_gem:
- Configure mdio clock at run time
zynq:
- Enable fdt overlay support
zynq_sdhci:
- Call dll reset only for ZynqMP SOCs
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCZLqHzgAKCRDKSWXLKUoM
IcdEAKCSgy0lMxb1c0adCjpkQR9x63oKbQCdGiioU+W+0moznHdI7+W2UptNt3w=
=Uzn8
-----END PGP SIGNATURE-----
Merge tag 'xilinx-for-v2023.10-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2023.10-rc1 v2
axi_emac:
- Change return value if RX packet is not ready
cadence_qspi:
- Enable flash reset for Versal NET
dt:
- Various DT syncups with Linux kernel
- SOM - reserved pmufw memory location
fpga:
- Add load event
mtd:
- Add missing dependency for FLASH_CFI_MTD
spi/nand:
- Minor cleanup in Xilinx drivers
versal-net:
- Prioritize boot device in boot_targets
- Wire mini ospi/qspi/emmc configurations
watchdog:
- Use new versal-wwdt property
xilinx:
- fix sparse warnings in various places ps7_init*
- add missing headers
- consolidate code around zynqmp_mmio_read/write
- switch to amd.com email
zynqmp_clk:
- Add handling for gem rx/tsu clocks
zynq_gem:
- Configure mdio clock at run time
zynq:
- Enable fdt overlay support
zynq_sdhci:
- Call dll reset only for ZynqMP SOCs
To sync with the upstream code, removed 'snps,enable_guctl1_resume_quirk'
quirk for usb. This quirk is no more available in linux after the xilinx
release 2022.2.
This functionality is taken care of by the 'snps,resume-hs-terminations'
quirk.
Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4b7a132116bf0248cdb558e04de3b06b412c4a0f.1688992653.git.michal.simek@amd.com
Explicitly specify interrupt affinity to avoid HW perfevents
need to guess. This avoids the following error upon linux boot:
armv8-pmu pmu: hw perfevents: no interrupt-affinity property,
guessing.
Reported-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c2f55a10cf54c6004f5dfe2ea18bcb4cf04f5723.1688992653.git.michal.simek@amd.com
Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for
CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache
node and let each CPU point to it.
Reported-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8dfabab12c97922aaad7fa91be0cbc7e4021528.1688992653.git.michal.simek@amd.com
The commit a4180c3696 ("arm64: zynqmp: Add mode-pin GPIO controller DT
node") added usb phy reset over bootmode pins by default on usb0 only.
zcu100 is using usb0 as peripheral and usb1 as host. Unfortunately reset
line is shared for both usb ulpi phys but usb_rst_b is connected to usb5744
hub which is used only in host mode. Especially this chip requires reset to
operate properly that's why better assign gpio reset to usb1 instead of
usb0.
Without this change usb start crashed when runs.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1ca80ec5bf7a595c03822f3e4e3683298205067a.1688992653.git.michal.simek@amd.com
Extend compatible versions for K24 SOM.
Changes are not affecting SW behavior that's why all versions are
compatible to each other.
Describing all revisions is done by purpose because user space SW is
reading compatible string for logic around DT overlays and bitstreams.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/92eba01ac316e58bd2d3508b0e63bbfafbedbb73.1688992653.git.michal.simek@amd.com
Increase reset assert time for TI SGMII PHY on KR260 CC starting
6.1 kernel. This PHY does not come out of reset with the existing
100us pulse width as per testing on multiple carrier cards. The reset
is driven via a PCA9570 I2C expander. The expander driver was updated
to an upstream version in 6.1 where gpio_chip _set was optimized.
Delays in earlier kernels may have masked this issue. This is a safe
workaround value for assert pulse width before the discussions are
resolved with TI.
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8fb9f17d43a43ef504c9f29006cd686cce8ac98b.1688992653.git.michal.simek@amd.com
Add support for Versal NET mini Octal SPI flash configuration. This runs
from onchip memory, so it has to be compact. Hence only Octal SPI
related settings are enabled.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614121351.21521-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add support for Versal NET mini Quad SPI flash configuration. This runs
from onchip memory, so it has to be compact. Hence only Quad SPI
related settings are enabled.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614121351.21521-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
PMUFW requires top 1MB of the lower DDR memory reserved for its operation,
this is missing in k26/k24 sm static dts files because of which U-Boot
throws warning messages "efi_free_pool: illegal free" as EFI puts
some code to that space which shouldn't happen.
Signed-off-by: Sharath Kumar Dasari <sharath.kumar.dasari@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/57452d16df2d48593de206bebf877d2c2cfe7bf1.1685966389.git.michal.simek@amd.com
These boards use SPL in a mkimage entry and apparently access the symbol
containing the image position of U-Boot, but put U-Boot in another
image. This means that binman is unable to fill in the symbol correctly
in the SPL binary.
This doesn't matter at present since mkimage doesn't support symbol
writing. But with the upcoming conversion to a section, it will. So add
a property to disable symbol writing.
Signed-off-by: Simon Glass <sjg@chromium.org>
The sar-reg0 alias was left over from an earlier iteration of the
patches adding support for this board. Remove the unused alias.
Fixes: 6cc8b5db40 ("arm: mvebu: Add RD-AC5X board")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The x240 and SE240 are a series of L2+ switches from Allied Telesis.
There are a number of them in the range but as far as U-Boot is
concerned all the CPU block components are the same so there's only one
board defined.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Drive CTRL_SLEEP_MOCI# high at boot (SPL) using a GPIO hog, this signal
may be used to control some power-rails on the carrier board, therefore
it should be set to high when the module is booting.
To do this as early as possible is generally a good idea and the issue
was noticed on the Yavia carrier board where it is needed to power the
I2C EEPROM on the carrier board.
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Drive CTRL_SLEEP_MOCI# high at boot (SPL) using a GPIO hog, this signal
may be used to control some power-rails on the carrier board, therefore
it should be set to high when the module is booting.
To do this as early as possible is generally a good idea and the issue
was noticed on the Yavia carrier board where it is needed to power the
I2C EEPROM on the carrier board.
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
The USB Power domains should not have been removed as it causes
the board to hang if the USB is started.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Several changes have been made to the device tree
in the kernel, so update that as well as the
corresponding imx8mp-u-boot.dtsi files to prevent
breaking the booting.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
For SOM with the EC configuration, the ethernet PHY is located on the
SOM itself, and connected to the CPU ethernet controller. It has a
reset line controlled via GPIO1_IO9. In this configuration, the PHY
located on the carrier board is not connected to anything and is
therefore not used.
For SOM without EC configuration, the ethernet PHY on the carrier
board is connected to the CPU ethernet controller. It has a reset line
controlled via the GPIO expander PCA9534_IO5.
The hardware configuration (EC) is determined at runtime by
reading from the SOM EEPROM.
To support both hardware configurations (EC and non-EC), adjust/fix
the PHY reset gpios according to the hardware configuration
read at runtime from the SOM EEPROM. This adjustement is done in
U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
The AC5/AC5X SoC has a NAND flash controller. Add this to the
SoC device tree.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
- Update the Thecus N2350 DTS to conform with latest device-tree binding
and styles.
- Correct typo in mdio node.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
The Gateworks imx8mp-venice-gw7905-2x consists of a SOM + baseboard.
The GW702x SOM contains the following:
- i.MX8M Plus SoC
- LPDDR4 memory
- eMMC Boot device
- Gateworks System Controller (GSC) with integrated EEPROM, button
controller, and ADC's
- PMIC
- SOM connector providing:
- eQoS GbE MII
- 1x SPI
- 2x I2C
- 4x UART
- 2x USB 3.0
- 1x PCI
- 1x SDIO (4-bit 3.3V)
- 1x SDIO (4-bit 3.3V/1.8V)
- GPIO
The GW7905 Baseboard contains the following:
- GPS
- microSD
- off-board I/O connector with I2C, SPI, GPIO
- EERPOM
- PCIe clock generator
- 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0
- 1x half-length miniPCIe socket with USB2.0 and USB3.0
- USB 3.0 HUB
- USB Type-C with USB PD Sink capability and peripheral support
- USB Type-C with USB 3.0 host support
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
While testing the ethernet interface on a Variscite symphony carrier
board using an imx8mn SOM with an onboard ADIN1300 PHY (EC hardware
configuration), the ethernet PHY is not detected.
The ADIN1300 datasheet indicate that the "Management interface
active (t4)" state is reached at most 5ms after the reset signal is
deasserted.
The device tree in Variscite custom git repository uses the following
property:
phy-reset-post-delay = <20>;
Add a new MDIO property 'reset-deassert-us' of 20ms to have the same
delay inside the ethphy node. Adding this property fixes the problem
with the PHY detection.
Note that this SOM can also have an Atheros AR8033 PHY. In this case,
a 1ms deassert delay is sufficient. Add a comment to that effect.
Fixes: c4c1ed68c1 ("imx8mn_var_som: Add support for Variscite
VAR-SOM-MX8M-NANO board")
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Enable support to read and display configuration/manufacturing infos
from 4Kbit EEPROM located on SOM board.
Note: CONFIG_DISPLAY_BOARDINFO is automatically selected for ARM arch.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
As imx28 family of SoCs is NOT supporting the Common Clock Framework (CCF)
the 'clks' property shall NOT be enabled by default.
Without this change u-boot proper before relocation tries to bind driver
(which doesn't exists) for this device. As a result, pre-relocation DTB
parsing is finished with error and the board hangs in a very early stage
of u-boot proper boot process.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The imx287 SoC doesn't support common clock framework (CCF), so the
'clocks' property is removed to avoid early (i.e. in SPL) errors when
SPL_OF_PLATDATA is used.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The DM_SERIAL implicitly requires CONFIG_PL01X_SERIAL, which
allows support for both serial IP block versions (i.e. PL011 and
PL010).
The decision about used IP block is based on the compatible string,
when DM is used.
In the XEA, the OF_PLATDATA is used to allow usage of serial driver in
the SPL (as the size of SPL is crucial). In this case one cannot extract
the type of IP block from .data field (corresponding to compatible) and
it must be explicitly read at probe from dtoc generated, u-boot specific
property.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
After enabling DM_SERIAL for XEA board, the same serial shall be used
in the SPL (with SPL_OF_PLATDATA support).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
After the commit (SHA1: 7d08ddd09b) some
u-boot specific XEA FEC related properties have been replaced by ones
from the Linux kernel.
To be more specific - XEA board (and imx287 in general) has built L2
switch connected to FEC, which needs some special treatment.
In u-boot it is handled with 'mac0' node, whereas Linux uses dedicated
switch DTS node.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
After the re-sync with Linux Kernel's DTS
(SHA1: 7d08ddd09b), the XEA's
descripion has nodes and properties, which are NOT utilized
in the u-boot.
To avoid confusion - those are deleted.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
In order to use the FlexSPI interface in U-Boot, configure
the alias to make spi0 point to flexspi.
With that enabled, sf probe detects the QSPI part as:
SF: Detected n25q256ax1 with page size 256 Bytes, erase size 4 KiB, total 32 MiB
Signed-off-by: Adam Ford <aford173@gmail.com>
Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all".
In order to keep the serial nodes in sync with their representation in
the Linux dts, add these u-boot specific properties to *-u-boot.dtsi
files.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Pick up the serial node descriptions from Linux v6.3 for the ls1046ardb
and ls1046afrwy boards and their dependencies. Including the
fsl,qoriq-clockgen.h and arm-gic.h headers forces us to change the include
directives to explicitly go through the C preprocessor for all boards in
the ls1046a SoC family.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all".
In order to keep the serial nodes in sync with their representation in
the Linux dts, add these u-boot specific properties to *-u-boot.dtsi
files.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Pick up the serial node descriptions from Linux v6.3 for the ls1043ardb
board and its dependencies. Including the fsl,qoriq-clockgen.h and
arm-gic.h headers forces us to change the include directives to explicitly
go through the C preprocessor for all boards in the ls1043a SoC family.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The HTC One X is a touchscreen-based, slate-sized smartphone
designed and manufactured by HTC that runs the Android operating
system. The One X features a 4.7" display, an Nvidia Tegra 3
quad-core chip, 1 GB of RAM and non-extendable 32 GB of internal
storage. UART-A is default debug port.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com>
Tested-by: Ion Agorria <ion@agorria.com>
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
LG X3 is a development board based on Nvidia Tegra 3 SoC
on base of which Optimus 4X HD and Optimus Vu were created.
Both smartphones feature a 4.7" and 5" panels respectively,
an Nvidia Tegra 3 quad-core chip, 1 GB of RAM and 16/32 GB
of internal storage. Optimux 4X HD additionally has a micro
SD slot.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # LG P880 T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Nexus 7 is a mini tablet computer co-developed by Google and Asus
that runs the Android operating system. The Nexus 7 features a 7"
display, an Nvidia Tegra 3 quad-core chip, 1 GB of RAM and 8/16 GB
of internal storage.
This patch brings support for all 3 known ASUS/Google devices:
- Nexus 7 (2012) E1565
- Nexus 7 (2012) PM269
- Nexus 7 (2012) 3G - tilapia
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS Grouper E1565
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The ASUS Transformer T30 family are 2-in-1 detachable tablets
and AiO developed by ASUS that run the Android operating system
(TF600T runs Windows RT and P1801-T runs Android and Windows).
The T30 Transformers feature a 10.1-inch display (apart P1801-T),
an Nvidia Tegra 3 quad-core chip, 1/2 GB of RAM, and 16/32 GB of
storage. Transformers board derives from Nvidia Cardhu development
board.
This patch brings support for 7 known Transformer devices:
- ASUS Transformer Prime TF201
- ASUS Transformer Pad TF300T/TF300TG/TF300TL
- ASUS VivoTab RT TF600T (Windows RT based)
- ASUS Transformer Infinity TF700T
- ASUS Portable AiO P1801-T
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # all devices
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Import the device tree from mainline linux (v6.4-rc1) and add the
old PHY reset bindings in the PHY node, else U-Boot and linux won't
be able to use the PHY.
Signed-off-by: Ferass El Hafidi <vitali64pmemail@protonmail.com>
Link: https://lore.kernel.org/r/20230507124109.31778-2-vitali64pmemail@protonmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Add meson-a1-ad401.dts file from Linux 6.3-rc7
Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230505125639.3605-3-ivprusov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Import Linux 6.3-rc7 Device tree and necessary bindings for Amlogic A1
board from 6a8f57ae2eb0 ("Linux 6.3-rc7").
Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230505125639.3605-2-ivprusov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
The current mechanism is unnecessarily complex. Simplify the whole mechanism
such that the entire fitImage is signed, IVT is placed at the end, followed
by CSF, and this entire bundle is also authenticated. This makes the signing
scripting far simpler.
Signed-off-by: Marek Vasut <marex@denx.de>
After "spi: spi_flash_probe_bus_cs() rely on DT for spi speed and mode"
series flash speed and mode wasn't passed to driver anymore, which
resulted in:
Loading Environment from SPIFlash... tegra20_sflash spi@7000c380: Invalid chip select 0:0 (err=-19)
*** Warning - spi_flash_probe_bus_cs() failed, using default environment
Fix it by syncing SPI node of affected device dts with Linux kernel dts.
The changed SPI bus frequency doesn't influence stability of read/write
operations.
Ref: https://patchwork.ozlabs.org/project/uboot/cover/20220518064648.1843664-1-patrice.chotard@foss.st.com
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
The node has become useless, as described in the
commit 754815b854 ("video: stm32: remove the compatible "synopsys, dw-mipi-dsi" support")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add partitions subnode in flash0 and nand nodes for all stm32mp157xx-ev1
boards. Update only the file stm32mp157c-ev1-*u-boot.dtsi, included by
other files stm32mp15*-ev1-*-u-boot.dtsi.
For SCMI variant of device tree used with stm32mp15_defconfig
add partitions needed by TF-A firmware update:
- metadata to save the TF-A information: 2 copy
- fip-a / fip-b: two FIP slots, used for system A/B (seamless) update
- the previous "fsbl" partition with 2 copy of TFA is replaced
by 2 partitions (only one copy in each MTD partition) to simplify
the update: no need to managed this copy on update, need to update the
two partition (skip bad block for NAND)
The offset for ENV partition are also updated in stm32mp15_defconfig
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Update "secure" version of STM32 boards based on SCMI when RCC_TZCR.TZEN=1
stm32mp15xx-*-scmi-u-boot.dtsi with latest patches on files
stm32mp15xx-*-u-boot.dtsi.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Describe the FMan Ethernet interfaces present on the board.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add compatible values to Ethernet PHY subnodes representing SMSC
LAN8710A PHYs on RZ/A1 and R-Mobile A1 boards. This allows software to
identify the PHY model at any time, regardless of the state of the PHY
reset line.
Ported from Linux kernel commit 1c65ef1c71e473c00f2a7a1b9c140f0b4862f282 .
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/247dc2074dae149af07b6d014985ad30eb362eda.1631174218.git.geert+renesas@glider.be
---
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Michal Simek <michal.simek@amd.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Add board code for the R8A77980 V3HSK board.
Add CPLD sysreset driver to the R-Car V3H SK board.
Extracted from a larger patch by Valentine Barshak.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync configs and board code with V3H Condor, squash CPLD driver in]
Import R8A77980 V3HSK DTs from Linux 6.1.31,
commit d2869ace6eeb ("Linux 6.1.31").
Extracted from a larger patch by Valentine Barshak.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Sync with 6.1.31
Add board code for the R8A77970 V3MSK board.
Add CPLD sysreset driver to the R-Car V3M SK board.
Extracted from a larger patch by Valentine Barshak.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync configs and board code with V3M Eagle, squash CPLD driver in]
Import R8A77970 V3MSK DTs from Linux 6.1.31,
commit d2869ace6eeb ("Linux 6.1.31").
Extracted from a larger patch by Valentine Barshak.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Sync with 6.1.31
Sync the devicetree files from the official Linux kernel tree, v6.4-rc2.
This is covering both 64-bit and 32-bit Allwinner SoCs with Arm Ltd.
cores, we skip the new RISC-V bits for now, as sunxi RISC-V support
is still work in progress.
Among smaller cosmetic changes, this adds a SATA regulator node which we
need in U-Boot to get rid of hard-coded GPIOs.
Also this updates the Allwinner F1C100s DTs, enabling USB support, and
also adds the DTs for two new boards.
As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This platform is currently unmaintained and untested, so remove it.
Further, as it is the only TI816X SoC example, remove related files as
well.
Signed-off-by: Tom Rini <trini@konsulko.com>
Commit 1a7904fdfa ("mmc: fsl_esdhc_imx: Use esdhc_soc_data
flags to set host caps") exposed the following SD card error:
U-Boot 2023.04-00652-g487e42f7bc5e (Apr 05 2023 - 22:14:21 -0300)
CPU: Freescale i.MX7D rev1.0 1000 MHz (running at 792 MHz)
CPU: Commercial temperature grade (0C to 95C) at 35C
Reset cause: POR
Model: Freescale i.MX7 SabreSD Board
Board: i.MX7D SABRESD in non-secure mode
DRAM: 1 GiB
Core: 100 devices, 19 uclasses, devicetree: separate
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x10
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... Card did not respond to voltage
select! : -110
*** Warning - No block device, using default environment
The reason of the problem, as explained by Ye Li:
"When UHS is enabled in defconfig, the usdhc1 node in imx7d-sdb.dts does
not configure pad for VSELECT, also the data pad should be set to
100Mhz/200Mhz pin states."
Apply these changes into u-boot.dtsi for now. When these changes
reach the Linux mainline imx7d-sdb, they can be dropped from u-boot.dtsi.
This fixes UHS mode on the imx7d-sdb board.
Suggested-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 5 Model B.
Similar to RK3568 the BootRom in RK3588 can read all data and look for
idbloader at 0x8000, same as on SD and eMMC.
Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x60000.
=> sf probe
SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB
=> load mmc 1:1 10000000 u-boot-rockchip-spi.bin
1492992 bytes read in 129 ms (11 MiB/s)
=> sf update $fileaddr 0 $filesize
device 0 offset 0x0, size 0x16c800
1300480 bytes written, 192512 bytes skipped in 11.103s, speed 137694 B/s
The BROM_BOOTSOURCE_ID value read back when booting from SPI flash does
not match the expected value of 3 (SPINOR) used by other SoCs. Instead a
value of 6 is read back, add a new enum value to handle this new
bootsource id.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Enable pinctrl for sdhci in SPL to support loading of FIT image from SD
and eMMC storage when booting from SPI NOR flash.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 3 Model A.
Unlike prior generation SoCs the BootRom in RK3568 can read all data and
look for idbloader at 0x8000, same as on SD and eMMC.
Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x60000.
=> sf probe
SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB
=> load mmc 1:1 10000000 u-boot-rockchip-spi.bin
1384448 bytes read in 119 ms (11.1 MiB/s)
=> sf update $fileaddr 0 $filesize
device 0 offset 0x0, size 0x152000
1179648 bytes written, 204800 bytes skipped in 9.901s, speed 143185 B/s
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Update defconfig for rk3566-radxa-cm3-io with new defaults. Also add
missing supported mmc modes to sdhci node.
Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.
Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.
Add config option to include useful gpio cmd.
Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.
Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.
Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add bootph-all prop to xin24m clock node, it is referenced by cru node.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable the PCIe 2x1l 2 device and associated combphy.
On this bus, the Rock5B has an Ethernet transceiver connected.
Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
[eugen.hristev@collabora.com: minor tweaks]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: add PCIe pins]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add the node for PCIe 2x1l 2 device together with the corresponding
combphy.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
[eugen.hristev@collabora.com: moved to -u-boot.dtsi, minor
adaptations]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: adapt to kernel node]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable the use of SDMA mode to boost eMMC performance on ROCK Pi 4.
Also add missing flags to indicate the supported MMC modes.
Using mmc read command to read 32 MiB data shows following improvement:
=> time mmc read 10000000 2000 10000
Before: time: 3.178 seconds
After: time: 0.402 seconds
This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
any possible future issue with loading TF-A into DRAM/SRAM.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable the use of SDMA mode to boost eMMC performance on RockPro64.
Also add missing flags to indicate the supported MMC modes.
Using mmc read command to read 32 MiB data shows following improvement:
=> time mmc read 10000000 2000 10000
Before: time: 3.178 seconds
After: time: 0.402 seconds
This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
any possible future issue with loading TF-A into DRAM/SRAM.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Loading part of TF-A into SRAM from eMMC using DMA fails on RK3399
similar to other Rockchip SoCs. Checksum validation fails with:
## Checking hash(es) for Image atf-2 ... sha256 error!
Bad hash value for 'hash' hash node in 'atf-2' image node
spl_load_simple_fit: can't load image loadables index 1 (ret = -1)
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Add a device tree property, u-boot,spl-fifo-mode, to control when the
rockchip_sdhci driver should disable the use of DMA and fallback on PIO
mode. Same device tree property is used by the rockchip_dw_mmc driver.
In commit 2cc6cde647 ("mmc: rockchip_sdhci: Limit number of blocks
read in a single command") the DMA mode was disabled using a CONFIG
option on RK3588. Revert that and instead disable DMA using the device
tree property for all RK3588 boards, also apply similar workaround for
all RK3399 boards.
Fixes: 2cc6cde647 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
To be able to initialize the pinctrl correctly at SPL level and read
u-boot proper from SD-Card, the pinctrl must be initialized.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add USB 2.0 host nodes and PHYs.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Co-developed-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This is taken directly from Linux kernel 6.3
(commit 457391b0380335d5e9a5babdec90ac53928b23b4)
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Linux commit 246450344dad arm64: dts: rockchip: rk3399: Radxa ROCK 4C+
Add support for Radxa ROCK 4C+ SBC.
Key differences of 4C+ compared to previous ROCK Pi 4.
- Rockchip RK3399-T SoC
- DP from 4C replaced with micro HDMI 2K@60fps
- 4-lane MIPI DSI with 1920*1080
- RK817 Audio codec
Also, an official naming convention from Radxa mention to remove
Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not
Radxa ROCK Pi 4C+.
Signed-off-by: Stephen Chen <stephen@radxa.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
sync dts{,i} files for Radxa ROCK Pi 4 series with Linux 6.3.
because rk3399-rock-pi-4a.dts is enough for ROCK Pi 4A/B/A+/B+ and ROCK
4SE, delete dts{,i} for ROCK Pi 4B.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The Anbernic RGxx3 is a "pseudo-device" that encompasses the following
devices:
- Anbernic RG353M
- Anbernic RG353P
- Anbernic RG353V
- Anbernic RG353VS
- Anbernic RG503
The rk3566-anbernic-rgxx3.dtsi is synced with upstream Linux, but
rk3566-anbernic-rgxx3.dts is a U-Boot specific devicetree that
is used for all RGxx3 devices.
Via the board.c file, the bootloader automatically sets the correct
fdtfile, board, and board_name environment variables so that the
correct devicetree can be passed to Linux. It is also possible to
simply hard-code a single devicetree in the boot.scr file and use
that to load Linux as well.
The common specifications for each device are:
- Rockchip RK3566 SoC
- 2 external SDMMC slots
- 1 USB-C host port, 1 USB-C peripheral port
- 1 mini-HDMI output
- MIPI-DSI based display panel
- ADC controlled joysticks with a GPIO mux
- GPIO buttons
- A PWM controlled vibrator
- An ADC controlled button
All of the common features are defined in the devicetree synced from
upstream Linux.
TODO: DSI panel auto-detection for the RG353 devices (requires porting
of DSI controller driver and DSI-DPHY driver to send DSI commands to
the panel).
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Somehow, I managed to typo our company name in the U-Boot
and Linux kernel submissions.
Fix this and update the copyright year at the same time.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
This synchronises the Linux device tree with U-Boot
(cp linux/..../fsl-ls1088a-ten64.dts uboot/..../fsl-ls1088a-ten64.dts),
as of Linux v6.2-rc5.
Missing from the U-Boot copy previously was the
Ethernet PCS definitions (required for linking with PHY in
Linux but not used by U-Boot) and various upstream
fixes and formatting changes.
The board microcontroller (which doesn't have a Linux driver)
has been moved to the -u-boot.dtsi, as well as the
spi0 quadspi alias (used by U-boot 'sf' but not valid for Linux).
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
Our [U-Boot] copy of fsl-ls1088a.dtsi had all the hardware under
the top level, until the DM_SERIAL implementation recently.
In this commit, remove any remaining devices (that were in U-Boot,
but not touched by previous patches in this series) to be under /soc,
updating to their upstream (Linux) bindings.
The bindings have been copied closest to their relative positions
in the Linux version, so the eventual result is that the U-Boot
and Linux fsl-ls1088a.dtsi will be identical.
The next commit will add the hardware bindings that were not
in U-Boot.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
This moves the fsl-mc device tree definition under the /soc
node, as well as adding interrupt and IOMMU definitions that
were not in U-Boot before.
There are slight differences between the two bindings
as we add a "simple-mfd" compatible to function
under U-Boot's driver model.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
Synchronise the MDIO controller definitions with Linux, so
the controllers will be usable when passing U-Boot's
control FDT to Linux.
This also adds the PCS (internal controller) definitions
which are not used by U-Boot.
Caveat: The kernel definition uses "fsl,fman-memac-mdio",
as with other members of the Layerscape family, but
U-Boot uses a different driver for the DPAA2
Family devices (LS1088/LS2088/LX2160). So
we use "fsl,ls-mdio" as the first compatible string
for these devices.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
Synchronise the USB device tree definition with Linux, allowing
the U-Boot control FDT to be used to boot a Linux system with
working USB.
An extra compatible string, "fsl,layerscape-dwc3" is needed
for special handling in U-Boot, so has been added to the
-u-boot.dtsi file. It might be better to add this to the
Linux source bindings.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
U-Boot's definition for the I2C controllers did not contain any
clock information. This resulted in the I2C not functioning when
the U-Boot control FDT was passed to Linux.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
Move the GPIO controller definitions under the "soc" and in
the same relative position as the Linux kernel fsl-ls1088a.dtsi.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
This is required for Linux to boot using the same FDT as
U-Boot (such as passing the control FDT to bootefi).
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
The Linux kernel fsl-ls1088a.dtsi disables (status="disabled")
all PCIe controllers by default, with the bootloader (i.e U-Boot)
enabling the appropriate controllers (specified by the board
reset control word/RCW) by FDT fixup.
However, U-Boot needs these controllers to be enabled
to be usable, which we can add in the u-boot only dtsi.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
This moves the PCIe controller definitions under /soc and adopts
the same bindings (fsl,ls1088a-pcie) as Linux. Previously,
the format was different between the two versions.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
To synchronise the device tree in U-Boot with Linux, the GIC
(Interrupt Controller) and SMMU/IOMMU nodes need to be synchronised
before changing any dependent components like PCIe and DPAA2/fsl-mc.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
The top-level "memory" node does not exist in the Linux
version of the fsl-ls1088a.dtsi file. Move it to the U-Boot
"tweak" file, so we can have an identical copy of
fsl-ls1088a.dtsi between the projects in the end.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
This moves the bootph-all tags that were added in commit a593c1fec5
("arch: arm: dts: fsl-ls1088a.dtsi: tag serial nodes with bootph-all")
into a u-boot only include.
Due to the way the U-Boot device tree "tweak" system is setup[1],
we need to have a per-board <boardname>-u-boot.dtsi, which will
include the "fsl-ls1088a-u-boot.dtsi" tweaks.
By doing so, future updates to fsl-ls1088a.dtsi from upstream
(Linux kernel) can just be copied directly into the U-Boot tree,
without worrying about any extra data local to U-Boot.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
[1] - https://u-boot.readthedocs.io/en/latest/develop/devicetree/control.html#adding-tweaks-for-u-boot
The CONFIG_SYS_SOC, CONFIG_SYS_CPU and CONFIG_SYS_VENDOR
values are the same for the entire Layerscape family,
meaning there is no ability to create a LS1088A only
file here. But we will be adding per-board tweaks
later in any case.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
Update the DDR settings to those generated using 0.6 version of
Jacinto 7 DDRSS Register Configuration tool.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Update the DDR settings to those generated using 0.9.1 version of
Jacinto 7 DDRSS Register Configuration tool.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Create *-u-boot.dtsi files for each target dtb of the IOT2050 series so
that we can drop the #include deviations from upstream dts[i] files
here.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
This platform is unsupported by TI and was never widely distributed. As
this is untested for a long while and missing some DM conversions,
remove it and related device tree files.
Signed-off-by: Tom Rini <trini@konsulko.com>
Add board specific devicetree for Bananapi R3 SBC.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
On modern Qualcomm platforms including SDM845 a GENI SE QUP IP
description is supposed to be found in board device tree nodes,
the version of the IP is used by the GENI UART driver to properly
set an oversampling divider value, which impacts UART baudrate.
The change touches dragonboard845c and starqltechn board device
tree source files, a device tree node label to "debug" UART is
renamed to 'uart9' according to the naming found in Linux.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
The name "se" is used in upstream Linux device trees and has been for
ages, long before this U-Boot-ism was introduced. Same goes for the
existing compatible. Get rid of that.
[vzapolskiy: removed a ready change in the driver]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
This adds a simple Northstar "BRCMNS" board to be used with
the BCM4708x and BCM5301x chips.
The main intention is to use this with the D-Link DIR-890L
and DIR-885L routers for loading the kernel into RAM from
NAND memory using the BCH-1 ECC and using the separately
submitted SEAMA load command, so we are currently not adding
support for things such as networking.
The DTS file is a multiplatform NorthStar board, designed to
be usable with several NorthStar designs by avoiding any
particulars not related to the operation of U-Boot.
If other board need other ECC for example, they need to
create a separate DTS file and augment the code, but I don't
know if any other users will turn up.
Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This brings in the main SoC device tree used by the
Broadcom Northstar chipset, i.e. BCM4709x and BCM5301x.
This is taken from the v6.3 Linux kernel.
Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The MNT Reform 2 is a modular DIY laptop. In its initial version it
is based on the BoundaryDevices i.MX8MQ SoM. Some parts have been
lifted from BoundaryDevices official U-Boot downstream project.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Stefano Babic <sbabic@denx.de>
On sunxi boards, SPL looks for U-Boot at a 32 KiB offset, unless SPL is
larger than 32 KiB, in which case U-Boot immediately follows SPL. See
the logic in spl_mmc_get_uboot_raw_sector() and spl_spi_load_image().
In two cases, the existing binman description mismatches the SPL code.
For 64-bit boards, binman would place U-Boot immediately following SPL,
even if SPL is smaller than 32 KiB. This can happen when SPL MMC support
is disabled (i.e. when booting from SPI flash).
In contrast, for 32-bit boards, binman would place U-Boot at 32 KiB,
even if SPL is larger than that. This happens because the 'offset'
property does not consider the size of previous entries.
Fix both issues by setting a minimum size for the SPL entry, which
exactly matches the logic in the SPL code. Unfortunately, this size must
be provided as a magic number, since none of the relevant config symbols
(SPL_PAD_TO, SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, and SYS_SPI_U_BOOT_OFFS)
are guaranteed to be defined in all cases.
Fixes: cfa3db602c ("sunxi: Convert 64-bit boards to use binman")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
