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https://github.com/AsahiLinux/u-boot
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ARM: renesas: Add R8A77980 V3HSK board and CPLD code
Add board code for the R8A77980 V3HSK board. Add CPLD sysreset driver to the R-Car V3H SK board. Extracted from a larger patch by Valentine Barshak. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Sync configs and board code with V3H Condor, squash CPLD driver in]
This commit is contained in:
Valentine Barshak
Marek Vasut
parent
bd13df8b5d
commit
ed2f65f010
8 changed files with 370 additions and 0 deletions
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@ -1052,6 +1052,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
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r8a77970-eagle-u-boot.dtb \
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r8a77970-v3msk-u-boot.dtb \
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r8a77980-condor-u-boot.dtb \
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r8a77980-v3hsk-u-boot.dtb \
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r8a77990-ebisu-u-boot.dtb \
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r8a77995-draak-u-boot.dtb
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42
arch/arm/dts/r8a77980-v3hsk-u-boot.dts
Normal file
42
arch/arm/dts/r8a77980-v3hsk-u-boot.dts
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@ -0,0 +1,42 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source extras for U-Boot for the Eagle board
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*
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* Copyright (C) 2019 Cogent Embedded, Inc.
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*/
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#include "r8a77980-v3hsk.dts"
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#include "r8a77980-u-boot.dtsi"
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/ {
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aliases {
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spi0 = &rpc;
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};
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};
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&rpc {
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num-cs = <1>;
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status = "okay";
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spi-max-frequency = <50000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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flash0: spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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reg = <0>;
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status = "okay";
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};
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};
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&i2c0 {
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cpld {
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compatible = "renesas,v3hsk-cpld";
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reg = <0x70>;
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u-boot,i2c-offset-len = <2>;
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};
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};
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@ -99,6 +99,11 @@ config TARGET_CONDOR
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help
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Support for Renesas R-Car Gen3 Condor platform
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config TARGET_V3HSK
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bool "V3HSK board"
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help
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Support for Renesas R-Car Gen3 V3HSK platform
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config TARGET_DRAAK
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bool "Draak board"
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imply R8A77995
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@ -171,6 +176,7 @@ source "board/renesas/eagle/Kconfig"
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source "board/renesas/ebisu/Kconfig"
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source "board/renesas/salvator-x/Kconfig"
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source "board/renesas/ulcb/Kconfig"
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source "board/renesas/v3hsk/Kconfig"
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source "board/renesas/v3msk/Kconfig"
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source "board/beacon/beacon-rzg2m/Kconfig"
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source "board/hoperun/hihope-rzg2/Kconfig"
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15
board/renesas/v3hsk/Kconfig
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15
board/renesas/v3hsk/Kconfig
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@ -0,0 +1,15 @@
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if TARGET_V3HSK
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config SYS_SOC
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default "rmobile"
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config SYS_BOARD
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default "v3hsk"
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config SYS_VENDOR
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default "renesas"
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config SYS_CONFIG_NAME
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default "v3hsk"
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endif
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15
board/renesas/v3hsk/Makefile
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15
board/renesas/v3hsk/Makefile
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@ -0,0 +1,15 @@
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#
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# board/renesas/v3hsk/Makefile
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#
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# Copyright (C) 2019 Renesas Electronics Corporation
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# Copyright (C) 2019 Cogent Embedded, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD
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obj-y := ../rcar-common/gen3-spl.o
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else
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obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o
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obj-$(CONFIG_SYSRESET) += cpld.o
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endif
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180
board/renesas/v3hsk/cpld.c
Normal file
180
board/renesas/v3hsk/cpld.c
Normal file
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@ -0,0 +1,180 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* V3HSK board CPLD access support
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*
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* Copyright (C) 2019 Renesas Electronics Corporation
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* Copyright (C) 2019 Cogent Embedded, Inc.
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*
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <i2c.h>
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#include <linux/err.h>
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#include <sysreset.h>
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#include <command.h>
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#define CPLD_ADDR_PRODUCT_0 0x0000 /* R */
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#define CPLD_ADDR_PRODUCT_1 0x0001 /* R */
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#define CPLD_ADDR_PRODUCT_2 0x0002 /* R */
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#define CPLD_ADDR_PRODUCT_3 0x0003 /* R */
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#define CPLD_ADDR_CPLD_VERSION_D 0x0004 /* R */
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#define CPLD_ADDR_CPLD_VERSION_M 0x0005 /* R */
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#define CPLD_ADDR_CPLD_VERSION_Y_0 0x0006 /* R */
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#define CPLD_ADDR_CPLD_VERSION_Y_1 0x0007 /* R */
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#define CPLD_ADDR_MODE_SET_0 0x0008 /* R */
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#define CPLD_ADDR_MODE_SET_1 0x0009 /* R */
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#define CPLD_ADDR_MODE_SET_2 0x000A /* R */
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#define CPLD_ADDR_MODE_SET_3 0x000B /* R */
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#define CPLD_ADDR_MODE_SET_4 0x000C /* R */
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#define CPLD_ADDR_MODE_LAST_0 0x0018 /* R */
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#define CPLD_ADDR_MODE_LAST_1 0x0019 /* R */
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#define CPLD_ADDR_MODE_LAST_2 0x001A /* R */
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#define CPLD_ADDR_MODE_LAST_3 0x001B /* R */
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#define CPLD_ADDR_MODE_LAST_4 0x001C /* R */
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#define CPLD_ADDR_DIPSW4 0x0020 /* R */
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#define CPLD_ADDR_DIPSW5 0x0021 /* R */
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#define CPLD_ADDR_RESET 0x0024 /* R/W */
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#define CPLD_ADDR_POWER_CFG 0x0025 /* R/W */
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#define CPLD_ADDR_PERI_CFG_0 0x0030 /* R/W */
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#define CPLD_ADDR_PERI_CFG_1 0x0031 /* R/W */
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#define CPLD_ADDR_PERI_CFG_2 0x0032 /* R/W */
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#define CPLD_ADDR_PERI_CFG_3 0x0033 /* R/W */
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#define CPLD_ADDR_LEDS 0x0034 /* R/W */
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#define CPLD_ADDR_LEDS_CFG 0x0035 /* R/W */
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#define CPLD_ADDR_UART_CFG 0x0036 /* R/W */
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#define CPLD_ADDR_UART_STATUS 0x0037 /* R */
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#define CPLD_ADDR_PCB_VERSION_0 0x1000 /* R */
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#define CPLD_ADDR_PCB_VERSION_1 0x1001 /* R */
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#define CPLD_ADDR_SOC_VERSION_0 0x1002 /* R */
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#define CPLD_ADDR_SOC_VERSION_1 0x1003 /* R */
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#define CPLD_ADDR_PCB_SN_0 0x1004 /* R */
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#define CPLD_ADDR_PCB_SN_1 0x1005 /* R */
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static u16 cpld_read(struct udevice *dev, u16 addr)
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{
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u8 data[2];
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/* Random flash reads require 2 reads: first read is unreliable */
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if (addr >= CPLD_ADDR_PCB_VERSION_0)
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dm_i2c_read(dev, addr, data, 2);
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/* Only the second byte read is valid */
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dm_i2c_read(dev, addr, data, 2);
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return data[1];
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}
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static void cpld_write(struct udevice *dev, u16 addr, u8 data)
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{
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dm_i2c_write(dev, addr, &data, 1);
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}
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static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
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{
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struct udevice *dev;
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u16 addr, val;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
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DM_DRIVER_GET(sysreset_renesas_v3hsk),
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&dev);
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if (ret)
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return ret;
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if (argc == 2 && strcmp(argv[1], "info") == 0) {
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printf("Product: 0x%08x\n",
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(cpld_read(dev, CPLD_ADDR_PRODUCT_3) << 24) |
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(cpld_read(dev, CPLD_ADDR_PRODUCT_2) << 16) |
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(cpld_read(dev, CPLD_ADDR_PRODUCT_1) << 8) |
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cpld_read(dev, CPLD_ADDR_PRODUCT_0));
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printf("CPLD version: 0x%08x\n",
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(cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_1) << 24) |
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(cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_0) << 16) |
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(cpld_read(dev, CPLD_ADDR_CPLD_VERSION_M) << 8) |
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cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D));
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printf("Mode setting (MD0..26): 0x%08x\n",
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(cpld_read(dev, CPLD_ADDR_MODE_LAST_3) << 24) |
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(cpld_read(dev, CPLD_ADDR_MODE_LAST_2) << 16) |
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(cpld_read(dev, CPLD_ADDR_MODE_LAST_1) << 8) |
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cpld_read(dev, CPLD_ADDR_MODE_LAST_0));
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printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n",
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cpld_read(dev, CPLD_ADDR_DIPSW4) ^ 0xff,
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(cpld_read(dev, CPLD_ADDR_DIPSW5) ^ 0xff) & 0xf);
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printf("Power config: 0x%08x\n",
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cpld_read(dev, CPLD_ADDR_POWER_CFG));
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printf("Periferals config: 0x%08x\n",
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(cpld_read(dev, CPLD_ADDR_PERI_CFG_3) << 24) |
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(cpld_read(dev, CPLD_ADDR_PERI_CFG_2) << 16) |
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(cpld_read(dev, CPLD_ADDR_PERI_CFG_1) << 8) |
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cpld_read(dev, CPLD_ADDR_PERI_CFG_0));
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printf("PCB version: %d.%d\n",
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cpld_read(dev, CPLD_ADDR_PCB_VERSION_1),
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cpld_read(dev, CPLD_ADDR_PCB_VERSION_0));
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printf("SOC version: %d.%d\n",
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cpld_read(dev, CPLD_ADDR_SOC_VERSION_1),
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cpld_read(dev, CPLD_ADDR_SOC_VERSION_0));
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printf("PCB S/N: %d\n",
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(cpld_read(dev, CPLD_ADDR_PCB_SN_1) << 8) |
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cpld_read(dev, CPLD_ADDR_PCB_SN_0));
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return 0;
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}
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if (argc < 3)
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return CMD_RET_USAGE;
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addr = simple_strtoul(argv[2], NULL, 16);
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if (!(addr >= CPLD_ADDR_PRODUCT_0 && addr <= CPLD_ADDR_UART_STATUS)) {
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printf("cpld invalid addr\n");
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return CMD_RET_USAGE;
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}
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if (argc == 3 && strcmp(argv[1], "read") == 0) {
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printf("0x%x\n", cpld_read(dev, addr));
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} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
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val = simple_strtoul(argv[3], NULL, 16);
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cpld_write(dev, addr, val);
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}
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return 0;
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}
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U_BOOT_CMD(cpld, 4, 1, do_cpld,
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"CPLD access",
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"info\n"
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"cpld read addr\n"
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"cpld write addr val\n"
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);
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static int renesas_v3hsk_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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cpld_write(dev, CPLD_ADDR_RESET, 1);
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return -EINPROGRESS;
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}
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static int renesas_v3hsk_sysreset_probe(struct udevice *dev)
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{
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if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
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return -EPROTONOSUPPORT;
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return 0;
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}
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static struct sysreset_ops renesas_v3hsk_sysreset = {
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.request = renesas_v3hsk_sysreset_request,
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};
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static const struct udevice_id renesas_v3hsk_sysreset_ids[] = {
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{ .compatible = "renesas,v3hsk-cpld" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(sysreset_renesas_v3hsk) = {
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.name = "renesas_v3hsk_sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &renesas_v3hsk_sysreset,
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.probe = renesas_v3hsk_sysreset_probe,
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.of_match = renesas_v3hsk_sysreset_ids,
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};
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83
configs/r8a77980_v3hsk_defconfig
Normal file
83
configs/r8a77980_v3hsk_defconfig
Normal file
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@ -0,0 +1,83 @@
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CONFIG_ARM=y
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CONFIG_COUNTER_FREQUENCY=16666666
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CONFIG_ARCH_CPU_INIT=y
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CONFIG_ARCH_RMOBILE=y
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CONFIG_SYS_MALLOC_LEN=0x4000000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_ENV_SIZE=0x40000
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CONFIG_ENV_OFFSET=0x700000
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CONFIG_ENV_SECT_SIZE=0x40000
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="r8a77980-v3hsk-u-boot"
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CONFIG_SPL_TEXT_BASE=0xe6318000
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CONFIG_RCAR_GEN3=y
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CONFIG_R8A77980=y
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CONFIG_TARGET_V3HSK=y
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CONFIG_SPL_STACK=0xe6304000
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CONFIG_SYS_LOAD_ADDR=0x58000000
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CONFIG_LTO=y
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CONFIG_REMAKE_ELF=y
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CONFIG_SYS_MONITOR_LEN=1048576
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CONFIG_FIT=y
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CONFIG_SUPPORT_RAW_INITRD=y
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CONFIG_USE_BOOTARGS=y
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CONFIG_DEFAULT_FDT_FILE="r8a77980-v3hsk.dtb"
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# CONFIG_BOARD_EARLY_INIT_F is not set
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CONFIG_SYS_MALLOC_BOOTPARAMS=y
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CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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CONFIG_SPL_BSS_START_ADDR=0xe631f000
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CONFIG_SPL_BSS_MAX_SIZE=0x1000
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_MAXARGS=64
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CONFIG_SYS_PBSIZE=2068
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_ASKENV=y
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CONFIG_CMD_DFU=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_OF_CONTROL=y
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CONFIG_OF_DTB_PROPS_REMOVE=y
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CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_VERSION_VARIABLE=y
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CONFIG_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_CLK=y
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CONFIG_CLK_RENESAS=y
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CONFIG_RCAR_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_RCAR_I2C=y
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CONFIG_MMC_IO_VOLTAGE=y
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CONFIG_MMC_UHS_SUPPORT=y
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CONFIG_MMC_HS200_SUPPORT=y
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CONFIG_RENESAS_SDHI=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_SPANSION=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_BITBANGMII=y
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CONFIG_BITBANGMII_MULTI=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_SH_ETHER=y
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CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_RENESAS_RPC_SPI=y
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CONFIG_SYSRESET=y
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28
include/configs/v3hsk.h
Normal file
28
include/configs/v3hsk.h
Normal file
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@ -0,0 +1,28 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* include/configs/v3hsk.h
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* This file is V3HSK board configuration.
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*
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* Copyright (C) 2019 Renesas Electronics Corporation
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* Copyright (C) 2019 Cogent Embedded, Inc.
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*/
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#ifndef __V3HSK_H
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#define __V3HSK_H
|
||||
|
||||
#include "rcar-gen3-common.h"
|
||||
|
||||
/* Environment compatibility */
|
||||
|
||||
/* SH Ether */
|
||||
#define CFG_SH_ETHER_USE_PORT 0
|
||||
#define CFG_SH_ETHER_PHY_ADDR 0x0
|
||||
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID
|
||||
#define CFG_SH_ETHER_CACHE_WRITEBACK
|
||||
#define CFG_SH_ETHER_CACHE_INVALIDATE
|
||||
#define CFG_SH_ETHER_ALIGNE_SIZE 64
|
||||
|
||||
/* Board Clock */
|
||||
/* XTAL_CLK : 33.33MHz */
|
||||
|
||||
#endif /* __V3HSK_H */
|
||||
Loading…
Add table
Reference in a new issue