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ARM: renesas: Add R8A77970 V3MSK board and CPLD code
Add board code for the R8A77970 V3MSK board. Add CPLD sysreset driver to the R-Car V3M SK board. Extracted from a larger patch by Valentine Barshak. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Sync configs and board code with V3M Eagle, squash CPLD driver in]
This commit is contained in:
Valentine Barshak
Marek Vasut
parent
f2a21a8c24
commit
5f4e26964c
9 changed files with 564 additions and 0 deletions
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@ -1050,6 +1050,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
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r8a77965-ulcb-u-boot.dtb \
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r8a77965-salvator-x-u-boot.dtb \
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r8a77970-eagle-u-boot.dtb \
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r8a77970-v3msk-u-boot.dtb \
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r8a77980-condor-u-boot.dtb \
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r8a77990-ebisu-u-boot.dtb \
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r8a77995-draak-u-boot.dtb
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65
arch/arm/dts/r8a77970-v3msk-u-boot.dts
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65
arch/arm/dts/r8a77970-v3msk-u-boot.dts
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@ -0,0 +1,65 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source extras for U-Boot for the V3MSK board
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*
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* Copyright (C) 2019 Cogent Embedded, Inc.
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*/
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#include "r8a77970-v3msk.dts"
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#include "r8a77970-u-boot.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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aliases {
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spi0 = &rpc;
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};
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cpld {
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compatible = "renesas,v3msk-cpld";
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status = "okay";
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gpio-mdc = <&gpio1 21 0>;
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gpio-mosi = <&gpio1 22 0>;
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gpio-miso = <&gpio1 23 0>;
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gpio-enablez = <&gpio1 19 0>;
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/* Disable V3MSK Videobox Mini CANFD PHY */
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gpios = <&gpio0 12 0>, <&gpio0 14 0>;
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};
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};
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&avb {
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pinctrl-0 = <&avb0_pins>;
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pinctrl-names = "default";
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};
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&phy0 {
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reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
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};
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&pfc {
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avb0_pins: avb {
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mux {
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groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
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function = "avb0";
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};
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};
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};
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&rpc {
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num-cs = <1>;
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status = "okay";
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spi-max-frequency = <50000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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flash0: spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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reg = <0>;
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status = "okay";
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};
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};
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@ -111,6 +111,11 @@ config TARGET_EAGLE
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help
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Support for Renesas R-Car Gen3 Eagle platform
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config TARGET_V3MSK
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bool "V3MSK board"
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help
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Support for Renesas R-Car Gen3 V3MSK platform
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config TARGET_EBISU
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bool "Ebisu board"
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imply R8A77990
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@ -166,6 +171,7 @@ source "board/renesas/eagle/Kconfig"
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source "board/renesas/ebisu/Kconfig"
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source "board/renesas/salvator-x/Kconfig"
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source "board/renesas/ulcb/Kconfig"
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source "board/renesas/v3msk/Kconfig"
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source "board/beacon/beacon-rzg2m/Kconfig"
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source "board/hoperun/hihope-rzg2/Kconfig"
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source "board/silinux/ek874/Kconfig"
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15
board/renesas/v3msk/Kconfig
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15
board/renesas/v3msk/Kconfig
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@ -0,0 +1,15 @@
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if TARGET_V3MSK
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config SYS_SOC
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default "rmobile"
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config SYS_BOARD
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default "v3msk"
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config SYS_VENDOR
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default "renesas"
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config SYS_CONFIG_NAME
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default "rcar-gen3-common"
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endif
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6
board/renesas/v3msk/MAINTAINERS
Normal file
6
board/renesas/v3msk/MAINTAINERS
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@ -0,0 +1,6 @@
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V3MSK BOARD
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M: Cogent Embedded, Inc. <source@cogentembedded.com>
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S: Maintained
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F: board/renesas/v3msk/
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F: include/configs/v3msk.h
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F: configs/r8a77970_v3msk_defconfig
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15
board/renesas/v3msk/Makefile
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15
board/renesas/v3msk/Makefile
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@ -0,0 +1,15 @@
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#
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# board/renesas/v3msk/Makefile
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#
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# Copyright (C) 2019 Renesas Electronics Corporation
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# Copyright (C) 2019 Cogent Embedded, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD
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obj-y := ../rcar-common/gen3-spl.o
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else
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obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o
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obj-$(CONFIG_SYSRESET) += cpld.o
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endif
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368
board/renesas/v3msk/cpld.c
Normal file
368
board/renesas/v3msk/cpld.c
Normal file
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@ -0,0 +1,368 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* V3MSK board CPLD access support
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*
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* Copyright (C) 2019 Renesas Electronics Corporation
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* Copyright (C) 2019 Cogent Embedded, Inc.
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*
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <errno.h>
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#include <linux/err.h>
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#include <sysreset.h>
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#include <linux/delay.h>
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#include <command.h>
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#define CPLD_ADDR_PRODUCT_L 0x000 /* R */
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#define CPLD_ADDR_PRODUCT_H 0x001 /* R */
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#define CPLD_ADDR_CPLD_VERSION_D 0x002 /* R */
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#define CPLD_ADDR_CPLD_VERSION_Y 0x003 /* R */
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#define CPLD_ADDR_MODE_SET_L 0x004 /* R/W */
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#define CPLD_ADDR_MODE_SET_H 0x005 /* R/W */
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#define CPLD_ADDR_MODE_APPLIED_L 0x006 /* R */
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#define CPLD_ADDR_MODE_APPLIED_H 0x007 /* R */
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#define CPLD_ADDR_DIPSW 0x008 /* R */
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#define CPLD_ADDR_RESET 0x00A /* R/W */
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#define CPLD_ADDR_POWER_CFG 0x00B /* R/W */
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#define CPLD_ADDR_PERI_CFG1 0x00C /* R/W */
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#define CPLD_ADDR_PERI_CFG2 0x00D /* R/W */
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#define CPLD_ADDR_LEDS 0x00E /* R/W */
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#define CPLD_ADDR_PCB_VERSION 0x300 /* R */
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#define CPLD_ADDR_SOC_VERSION 0x301 /* R */
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#define CPLD_ADDR_PCB_SN_L 0x302 /* R */
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#define CPLD_ADDR_PCB_SN_H 0x303 /* R */
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#define MDIO_DELAY 10 /* microseconds */
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#define CPLD_MAX_GPIOS 2
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struct renesas_v3msk_sysreset_priv {
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struct gpio_desc miso;
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struct gpio_desc mosi;
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struct gpio_desc mdc;
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struct gpio_desc enablez;
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/*
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* V3MSK Videobox Mini board has CANFD PHY connected
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* we must shutdown this chip to use bb pins
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*/
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struct gpio_desc gpios[CPLD_MAX_GPIOS];
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};
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static void mdio_bb_active_mdio(struct renesas_v3msk_sysreset_priv *priv)
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{
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dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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}
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static void mdio_bb_tristate_mdio(struct renesas_v3msk_sysreset_priv *priv)
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{
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dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_IN);
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}
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static void mdio_bb_set_mdio(struct renesas_v3msk_sysreset_priv *priv, int val)
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{
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dm_gpio_set_value(&priv->mosi, val);
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}
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static int mdio_bb_get_mdio(struct renesas_v3msk_sysreset_priv *priv)
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{
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return dm_gpio_get_value(&priv->miso);
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}
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static void mdio_bb_set_mdc(struct renesas_v3msk_sysreset_priv *priv, int val)
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{
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dm_gpio_set_value(&priv->mdc, val);
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}
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static void mdio_bb_delay(void)
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{
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udelay(MDIO_DELAY);
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}
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/* Send the preamble, address, and register (common to read and write) */
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static void mdio_bb_pre(struct renesas_v3msk_sysreset_priv *priv,
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u8 op, u8 addr, u8 reg)
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{
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int i;
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/* 32-bit preamble */
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mdio_bb_active_mdio(priv);
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mdio_bb_set_mdio(priv, 1);
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for (i = 0; i < 32; i++) {
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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}
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/* send the ST (2-bits of '01') */
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mdio_bb_set_mdio(priv, 0);
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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mdio_bb_set_mdio(priv, 1);
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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/* send the OP (2-bits of Opcode: '10'-read, '01'-write) */
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mdio_bb_set_mdio(priv, op >> 1);
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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mdio_bb_set_mdio(priv, op & 1);
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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/* send the PA5 (5-bits of PHY address) */
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for (i = 0; i < 5; i++) {
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mdio_bb_set_mdio(priv, addr & 0x10); /* MSB first */
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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addr <<= 1;
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}
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/* send the RA5 (5-bits of register address) */
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for (i = 0; i < 5; i++) {
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mdio_bb_set_mdio(priv, reg & 0x10); /* MSB first */
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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reg <<= 1;
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}
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}
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static int mdio_bb_read(struct renesas_v3msk_sysreset_priv *priv,
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u8 addr, u8 reg)
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{
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int i;
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u16 data = 0;
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mdio_bb_pre(priv, 2, addr, reg);
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/* tri-state MDIO */
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mdio_bb_tristate_mdio(priv);
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/* read TA (2-bits of turn-around, last bit must be '0') */
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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/* check the turnaround bit: the PHY should drive line to zero */
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if (mdio_bb_get_mdio(priv) != 0) {
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printf("PHY didn't drive TA low\n");
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for (i = 0; i < 32; i++) {
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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}
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/* There is no PHY, set value to 0xFFFF */
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return 0xFFFF;
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}
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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/* read 16-bits of data */
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for (i = 0; i < 16; i++) {
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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data <<= 1;
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data |= mdio_bb_get_mdio(priv);
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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}
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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debug("cpld_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, data);
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return data;
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}
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static void mdio_bb_write(struct renesas_v3msk_sysreset_priv *priv,
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u8 addr, u8 reg, u16 val)
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{
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int i;
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mdio_bb_pre(priv, 1, addr, reg);
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/* send the TA (2-bits of turn-around '10') */
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mdio_bb_set_mdio(priv, 1);
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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mdio_bb_set_mdio(priv, 0);
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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/* write 16-bits of data */
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for (i = 0; i < 16; i++) {
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mdio_bb_set_mdio(priv, val & 0x8000); /* MSB first */
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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val <<= 1;
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}
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/* tri-state MDIO */
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mdio_bb_tristate_mdio(priv);
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mdio_bb_set_mdc(priv, 0);
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mdio_bb_delay();
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mdio_bb_set_mdc(priv, 1);
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mdio_bb_delay();
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}
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static u16 cpld_read(struct udevice *dev, u16 addr)
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{
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struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
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/* random flash reads require 2 reads: first read is unreliable */
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if (addr >= CPLD_ADDR_PCB_VERSION)
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mdio_bb_read(priv, addr >> 5, addr & 0x1f);
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return mdio_bb_read(priv, addr >> 5, addr & 0x1f);
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}
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static void cpld_write(struct udevice *dev, u16 addr, u16 data)
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{
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struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
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mdio_bb_write(priv, addr >> 5, addr & 0x1f, data);
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}
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static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
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{
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struct udevice *dev;
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u16 addr, val;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
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DM_DRIVER_GET(sysreset_renesas_v3msk),
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&dev);
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if (ret)
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return ret;
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if (argc == 2 && strcmp(argv[1], "info") == 0) {
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printf("Product: 0x%08x\n",
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(cpld_read(dev, CPLD_ADDR_PRODUCT_H) << 16) |
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cpld_read(dev, CPLD_ADDR_PRODUCT_L));
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printf("CPLD version: 0x%08x\n",
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(cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y) << 16) |
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cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D));
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printf("Mode setting (MD0..26): 0x%08x\n",
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(cpld_read(dev, CPLD_ADDR_MODE_APPLIED_H) << 16) |
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cpld_read(dev, CPLD_ADDR_MODE_APPLIED_L));
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printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n",
|
||||
(cpld_read(dev, CPLD_ADDR_DIPSW) & 0xff) ^ 0xff,
|
||||
(cpld_read(dev, CPLD_ADDR_DIPSW) >> 8) ^ 0xf);
|
||||
printf("Power config: 0x%08x\n",
|
||||
cpld_read(dev, CPLD_ADDR_POWER_CFG));
|
||||
printf("Periferals config: 0x%08x\n",
|
||||
(cpld_read(dev, CPLD_ADDR_PERI_CFG2) << 16) |
|
||||
cpld_read(dev, CPLD_ADDR_PERI_CFG1));
|
||||
printf("PCB version: %d.%d\n",
|
||||
cpld_read(dev, CPLD_ADDR_PCB_VERSION) >> 8,
|
||||
cpld_read(dev, CPLD_ADDR_PCB_VERSION) & 0xff);
|
||||
printf("SOC version: %d.%d\n",
|
||||
cpld_read(dev, CPLD_ADDR_SOC_VERSION) >> 8,
|
||||
cpld_read(dev, CPLD_ADDR_SOC_VERSION) & 0xff);
|
||||
printf("PCB S/N: %d\n",
|
||||
(cpld_read(dev, CPLD_ADDR_PCB_SN_H) << 16) |
|
||||
cpld_read(dev, CPLD_ADDR_PCB_SN_L));
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (argc < 3)
|
||||
return CMD_RET_USAGE;
|
||||
|
||||
addr = simple_strtoul(argv[2], NULL, 16);
|
||||
if (!(addr >= CPLD_ADDR_PRODUCT_L && addr <= CPLD_ADDR_LEDS)) {
|
||||
printf("cpld invalid addr\n");
|
||||
return CMD_RET_USAGE;
|
||||
}
|
||||
|
||||
if (argc == 3 && strcmp(argv[1], "read") == 0) {
|
||||
printf("0x%x\n", cpld_read(dev, addr));
|
||||
} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
|
||||
val = simple_strtoul(argv[3], NULL, 16);
|
||||
cpld_write(dev, addr, val);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(cpld, 4, 1, do_cpld,
|
||||
"CPLD access",
|
||||
"info\n"
|
||||
"cpld read addr\n"
|
||||
"cpld write addr val\n"
|
||||
);
|
||||
|
||||
static int renesas_v3msk_sysreset_request(struct udevice *dev, enum sysreset_t type)
|
||||
{
|
||||
cpld_write(dev, CPLD_ADDR_RESET, 1);
|
||||
|
||||
return -EINPROGRESS;
|
||||
}
|
||||
|
||||
static int renesas_v3msk_sysreset_probe(struct udevice *dev)
|
||||
{
|
||||
struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso,
|
||||
GPIOD_IS_IN))
|
||||
return -EINVAL;
|
||||
|
||||
if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi,
|
||||
GPIOD_IS_OUT))
|
||||
return -EINVAL;
|
||||
|
||||
if (gpio_request_by_name(dev, "gpio-mdc", 0, &priv->mdc,
|
||||
GPIOD_IS_OUT))
|
||||
return -EINVAL;
|
||||
|
||||
if (gpio_request_by_name(dev, "gpio-enablez", 0, &priv->enablez,
|
||||
GPIOD_IS_OUT))
|
||||
return -EINVAL;
|
||||
|
||||
/* V3MSK Videobox Mini board has CANFD PHY connected
|
||||
* we must shutdown this chip to use bb pins
|
||||
*/
|
||||
gpio_request_list_by_name(dev, "gpios", priv->gpios, CPLD_MAX_GPIOS,
|
||||
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sysreset_ops renesas_v3msk_sysreset = {
|
||||
.request = renesas_v3msk_sysreset_request,
|
||||
};
|
||||
|
||||
static const struct udevice_id renesas_v3msk_sysreset_ids[] = {
|
||||
{ .compatible = "renesas,v3msk-cpld" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(sysreset_renesas_v3msk) = {
|
||||
.name = "renesas_v3msk_sysreset",
|
||||
.id = UCLASS_SYSRESET,
|
||||
.ops = &renesas_v3msk_sysreset,
|
||||
.probe = renesas_v3msk_sysreset_probe,
|
||||
.of_match = renesas_v3msk_sysreset_ids,
|
||||
.priv_auto = sizeof(struct renesas_v3msk_sysreset_priv),
|
||||
};
|
||||
87
configs/r8a77970_v3msk_defconfig
Normal file
87
configs/r8a77970_v3msk_defconfig
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_COUNTER_FREQUENCY=16666666
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_TEXT_BASE=0x50000000
|
||||
CONFIG_SYS_MALLOC_LEN=0x4000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_ENV_SIZE=0x40000
|
||||
CONFIG_ENV_OFFSET=0x700000
|
||||
CONFIG_ENV_SECT_SIZE=0x40000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a77970-v3msk-u-boot"
|
||||
CONFIG_SPL_TEXT_BASE=0xe6318000
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_R8A77970=y
|
||||
CONFIG_TARGET_V3MSK=y
|
||||
CONFIG_SPL_STACK=0xe6304000
|
||||
CONFIG_SYS_LOAD_ADDR=0x58000000
|
||||
CONFIG_LTO=y
|
||||
CONFIG_REMAKE_ELF=y
|
||||
CONFIG_SYS_MONITOR_LEN=1048576
|
||||
CONFIG_FIT=y
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_DEFAULT_FDT_FILE="r8a77970-v3msk.dtb"
|
||||
CONFIG_SYS_MALLOC_BOOTPARAMS=y
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0xe631f000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x1000
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_MAXARGS=64
|
||||
CONFIG_SYS_PBSIZE=2068
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_DTB_PROPS_REMOVE=y
|
||||
CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_CLK_RENESAS=y
|
||||
CONFIG_DFU_TFTP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_DFU_SF=y
|
||||
CONFIG_RCAR_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_I2C=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_RENESAS_SDHI=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_BITBANGMII=y
|
||||
CONFIG_BITBANGMII_MULTI=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_RENESAS_RAVB=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_RENESAS_RPC_SPI=y
|
||||
CONFIG_SYSRESET=y
|
||||
|
|
@ -35,6 +35,7 @@ Currently the following boards are supported:
|
|||
| R8A77965 M3-N | Renesas Electronics ULCB | r8a77965_ulcb
|
||||
|---------------+----------------------------------------+-------------------
|
||||
| R8A77970 V3M | Renesas Electronics Eagle | r8a77970_eagle_defconfig
|
||||
| R8A77970 V3M | Renesas Electronics V3MSK | r8a77970_v3msk_defconfig
|
||||
|---------------+----------------------------------------+-------------------
|
||||
| R8A77995 D3 | Renesas Electronics Draak | r8a77995_draak_defconfig
|
||||
'===============+========================================+===================
|
||||
|
|
|
|||
Loading…
Reference in a new issue