Commit graph

710 commits

Author SHA1 Message Date
Jagan Teki
d2436301c5 spi: xilinx_spi: Use GENMASK
Replace numeric mask hexcodes with GENMASK macro
in xilinx_spi

Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:21:43 +05:30
Jagan Teki
76538ec648 spi: tegra: Use GENMASK
Replace numeric mask hexcodes with GENMASK macro
in tegra*.c

Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:21:43 +05:30
Jagan Teki
0ebc0ec620 spi: omap3_spi: Use GENMASK
Replace numeric mask hexcodes with GENMASK macro
in omap3_spi

Cc: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:21:43 +05:30
Jagan Teki
bad490a242 spi: fsl_qspi: Use GENMASK
Replace numeric mask hexcodes with GENMASK macro
in fsl_qspi

Cc: York Sun <yorksun@freescale.com>
Cc: Haikun Wang <Haikun.Wang@freescale.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:21:43 +05:30
Jagan Teki
95e77d904e spi: designware_spi: Use GENMASK
Replace numeric mask hexcodes with GENMASK macro
in designware_spi

Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:21:43 +05:30
Jagan Teki
a9d3b78023 spi: atmel_spi: Use GENMASK
Replace numeric mask hexcodes with GENMASK macro
in atmel_spi

Cc: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:21:42 +05:30
Jagan Teki
5ea392d43b spi: xilinx_spi: Use BIT macro
Replace numerical bit shift with BIT macro
in xilinx_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:21:42 +05:30
Jagan Teki
847720c4e1 spi: ti_qspi: Use BIT macro
Replace numerical bit shift with BIT macro
in ti_qspi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Reviewed-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:21:33 +05:30
Jagan Teki
f692248f90 spi: tegra: Use BIT macro
Replace numerical bit shift with BIT macro
in tegra*.c

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Warren <twarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:21:28 +05:30
Jagan Teki
ccaa948501 spi: sh_qspi: Use BIT macro
Replace numerical bit shift with BIT macro
in sh_qspi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:21:28 +05:30
Jagan Teki
3e1b4dcf1c spi: omap3_spi: Use BIT macro
Replace numerical bit shift with BIT macro
in omap3_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:21:28 +05:30
Jagan Teki
a048d4bbb1 spi: mpc8xxx_spi: Use BIT macro
Replace numerical bit shift with BIT macro
in mpc8xxx_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:21:28 +05:30
Jagan Teki
69fd4c386c spi: ich: Use BIT macro
Replace numerical bit shift with BIT macro
in ich

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:21:16 +05:30
Jagan Teki
29e6abd94b spi: fsl: Use BIT macro
Replace numerical bit shift with BIT macro
in fsl_*spi.c

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: York Sun <yorksun@freescale.com>
Cc: Haikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:19:29 +05:30
Jagan Teki
431a9f0286 spi: designware_spi: Use BIT macro
Replace numerical bit shift with BIT macro
in designware_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:19:29 +05:30
Jagan Teki
b7e83b087c spi: cadence_qspi_apb: Use BIT macro
Replace numerical bit shift with BIT macro
in cadence_qspi_apb

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:19:29 +05:30
Jagan Teki
c0d1ea4acd spi: bfin_spi6xx: Use BIT macro
Replace numerical bit shift with BIT macro
in bfin_spi6xx

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:19:29 +05:30
Jagan Teki
a48c4eb6a7 spi: atmel_spi: Use BIT macro
Replace numerical bit shift with BIT macro
in atmel_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:19:29 +05:30
Jagan Teki
9cf2ffb3c3 spi: zynq_[q]spi: Use GENMASK macro
GENMASK macro used on zynq_spi.c and zynq_qspi.c

GENMASK is used to create a contiguous bitmask([hi:lo]).
Ex: (0x7 << 3) => GENMASK(5, 3)

Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:19:15 +05:30
Jagan Teki
736b4df15d spi: zynq_[q]spi: Use BIT macro
Used BIT macro on zynq_spi.c and zynq_qspi.c

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:18:48 +05:30
Jagan Teki
e5e0d68f27 spi: zynq_qspi: Minor cleanups
- Use __func__ on debug
- Removed unnecessary comment
- Fix function name in debug as zynq_qspi_xfer instead of spi_xfer

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:03 +05:30
Jagan Teki
86e99b9861 spi: zynq_spi: Remove unneeded headers
- Removed unneeded inclusion of header files
- Add "Xilinx" on license text

Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:03 +05:30
Jagan Teki
2775e91835 spi: zynq_qspi: Fix to configure CPOL, CPHA mask
priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:03 +05:30
Jagan Teki
191269987c spi: zynq_spi: Store cs value into private data
Store cs value into private data and use it while activating
chipselect instead of passing through function.

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:02 +05:30
Jagan Teki
dda6241a1d spi: zynq_spi: Rename baudrate divisor mask name
Rename ZYNQ_SPI_CR_BRD_MASK to ZYNQ_SPI_CR_BAUD_MASK
for more readable.

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:02 +05:30
Jagan Teki
46ab8a6a13 spi: zynq_spi: Add config reg shift named macros
Update the numerical values for baudrate and chipselect
with config reg shift named macro's

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:02 +05:30
Jagan Teki
78a025ace8 spi: Kconfig: Add Zynq QSPI controller entry
Add Zynq QSPI controller Kconfig entry.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2015-10-25 20:17:02 +05:30
Jagan Teki
46d0a9913c spi: Add zynq qspi controller driver
Added zynq qspi controller driver for Xilinx Zynq APSOC,
this driver is driver-model driven with devicetree support.

=> sf probe
SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total 16 MiB
=> mw.b 0x100 0xCC 0x1000000
=> sf update 0x100 0x0 0x1000000
device 0 whole chip
16777216 bytes written, 0 bytes skipped in 59.842s, speed 289262 B/s
=> sf read 0x3000000 0x0 0x1000000
device 0 whole chip
SF: 16777216 bytes @ 0x0 Read: OK
=> cmp.b 0x3000000 0x100 0x1000000
Total of 16777216 byte(s) were the same

Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:01 +05:30
Simon Glass
bcbe3d1579 dm: Rename dev_get_parentdata() to dev_get_parent_priv()
The current name is inconsistent with other driver model data access
functions. Rename it and fix up all users.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2015-10-23 09:42:28 -06:00
Thomas Chou
15a56f9cb7 spi : convert altera_spi to driver model
Convert altera_spi to driver model

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-10-23 07:36:56 +08:00
George McCollister
5ac98cb9bd x86: spi: Add support for Wildcat Point
Add the Wildcat Point ID so Broadwell U based boards can use SPI.

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:27 -06:00
Mirza Krak
5cb1b7b395 spi: tegra20: Add support for mode selection
Respect the mode passed in set_mode ops.

Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-10-11 16:43:06 +05:30
Jagan Teki
a22bba81e4 spi: zynq_spi: Fix to configure CPOL, CPHA mask
priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-11 16:43:06 +05:30
Jagan Teki
d5f60737db spi: xilinx_spi: Fix to configure CPOL, CPHA mask
priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-11 16:43:06 +05:30
Heiko Schocher
92a3188d7d bitops: introduce BIT() definition
introduce BIT() definition, used in at91_udc gadget
driver.

Signed-off-by: Heiko Schocher <hs@denx.de>
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-09-11 17:15:32 -04:00
Simon Glass
cf92e05c01 Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h header
Now that we have a new header file for cache-aligned allocation, we should
move the stack-based allocation macro there also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 17:15:20 -04:00
Simon Glass
1b2fd5bf4e rockchip: Add SPI driver
Add a SPI driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
4e9838c102 dm: Use dev_get_addr() where possible
This is a convenient way for a driver to get the hardware address of a
device, when regmap or syscon are not being used. Change existing callers
to use it as an example to others.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-08-31 07:57:26 -06:00
Tom Rini
952bd79b53 Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-08-18 08:25:24 -04:00
Vignesh R
8ddd9c485f spi: ti_qspi: Use DMA to read from qspi flash
ti_qspi uses memory map mode for faster read. Enabling DMA will increase
read speed by 3x @48MHz on DRA74 EVM.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-08-17 23:29:15 +05:30
vishalm@ti.com
a39cfe717c ti: qspi: set flash quad bit based on quad support flag
Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag,
instead of platform.

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-08-17 23:29:14 +05:30
Thomas Abraham
77b55e8cfc ARM: exynos: move SoC sources to mach-exynos
Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow
reuse of existing code for ARMv8 based Exynos platforms.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-08-17 13:06:52 +09:00
Nikita Kiryanov
2ff97625cb spi: omap3_spi: add am43xx support to omap3_spi
Add support for AM43XX to the omap3_spi driver.

Cc: Jagan Teki <jteki@openedev.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-08-12 20:48:02 -04:00
York Sun
fdb9f349be lib/fdtdec: Fix compiling warning caused by changing fdt_addr_t type
fdt_addr_t is changed to phys_addr_t. The format in debug should be updated
to %pa to match the type.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Simon Glass <sjg@chromium.org>
2015-08-06 07:31:13 -06:00
Simon Glass
c7d50e7fb9 exynos: spi: Convert the timeout to debug()
Since the timeout is reported through normal channels, and is sometimes
expected (e.g. if the bus is being probed for a non-existent device),
don't display the message in the driver.

In general, drivers should not write to the console as this limits their
usefulness in error conditions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:14 -06:00
Michal Simek
80fd9792f5 spi: zynq_spi: Simplify debug macro
Trivial fix.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:28 +02:00
Michal Simek
40b383fa84 spi: Fix zynq SPI binding
Zynq is using Cadence IP where binding is documented in the Linux kernel
and there is no reason to use different binding.
Synchronize it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:22 +02:00
Simon Glass
6f849c3012 dm: spi: Make local functions static
Several functions in this file should be marked as static. Update them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-21 17:39:27 -06:00
Haikun Wang
b1d9e46a0b fdt: armv8: Fix build warnings on armv8
Fix below build warnings on armv8,
drivers/spi/fsl_dspi.c: In function ‘fsl_dspi_ofdata_to_platdata’:
drivers/spi/fsl_dspi.c:667:2:
warning: format ‘%x’ expects argument of type ‘unsigned int’,
	but argument 2 has type ‘fdt_addr_t’ [-Wformat=]
debug("DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n",
		    ^
lib/fdtdec.c: In function ‘fdtdec_get_addr_size’:
lib/fdtdec.c:105:4:
warning: format ‘%lx’ expects argument of type ‘long unsigned int’,
but argument 3 has type ‘fdt_size_t’ [-Wformat=]
debug("addr=%08lx, size=%08lx\n",
			    ^

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-20 07:21:47 -06:00
Tom Rini
605e15db2b Merge git://git.denx.de/u-boot-x86 2015-07-15 10:41:20 -04:00
Simon Glass
5078792807 dm: spi: Correct BIOS protection logic for ICH9
The logic is incorrect and currently has no effect. Fix it so that we can
write to SPI flash, since by default it is write-protected.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
2015-07-14 18:03:19 -06:00
Simon Glass
e1e332c8f2 dm: spi: Correct status register access width
The status register on ICH9 is a single byte, so use byte access when
writing to it, to avoid updating the control register also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-07-14 18:03:19 -06:00
Simon Glass
5d4a757ca5 dm: spi: Correct minor nits in ICH driver
Tidy up three minor problems in this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-07-14 18:03:15 -06:00
Vikas Manocha
70bb2b1415 spi: cadence_qspi: support FIFO width other than 4 bytes
This patch makes the code compatible with FIFO depths other than 4
bytes. It also simplify read/write FIFO loops.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
2015-07-03 13:50:53 +05:30
Vikas Manocha
90a2f71711 spi: cadence_qspi: get sram size from device tree
sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
2015-07-03 13:50:53 +05:30
Vikas Manocha
c0535c0ef0 spi: cadence_qspi: move the sram partition in init
There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read & half for write once at initialization.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
2015-07-03 13:50:53 +05:30
Angelo Dureghello
8aa5f1d971 spi: cf_qspi: fix clamp macro type check compilation warnings
Fix compilation warnings for redefined 'clamp' macro and non-uniform
clamp macro types.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
2015-07-01 22:58:50 +05:30
Jagan Teki
4495830c58 spi: Kconfig: Add TEGRA20_SLINK entry
Added TEGRA20_SLINK entry on Kconfig with help description.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
2015-07-01 21:39:05 +05:30
Jagan Teki
2f3e6f8cc1 spi: Kconfig: Add TEGRA20_SFLASH entry
Added TEGRA20_SFLASH entry on Kconfig with help description.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
2015-07-01 21:39:05 +05:30
Jagan Teki
5bf9a2d3dd spi: Kconfig: Add TEGRA114_SPI entry
Added TEGRA114_SPI entry on Kconfig with help description.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
2015-07-01 21:39:05 +05:30
Jagan Teki
456360102c spi: Kconfig: Add ICH_SPI entry
Added ICH_SPI entry on Kconfig with help description.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-01 21:39:05 +05:30
Jagan Teki
c354eee8d0 spi: Kconfig: Add EXYNOS_SPI entry
Added EXYNOS_SPI entry on Kconfig with help description.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-07-01 21:39:05 +05:30
Jagan Teki
91c22d046c spi: Kconfig: Add FSL_QSPI entry
Added FSL_QSPI entry on Kconfig with help description.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Peng Fan <Peng.Fan@freescale.com>
Cc: Haikun Wang <haikun.wang@freescale.com>
2015-07-01 21:39:04 +05:30
Jagan Teki
3debffa704 spi: Kconfig: Add FSL_ESPI entry
Added FSL_ESPI entry on Kconfig with help description.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Haikun Wang <haikun.wang@freescale.com>
2015-07-01 21:39:04 +05:30
Jagan Teki
94ea308d75 spi: Kconfig: Add FSL_DSPI entry
Added FSL_DSPI entry on Kconfig with help description.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Haikun Wang <haikun.wang@freescale.com>
2015-07-01 21:39:04 +05:30
Jagan Teki
e4976af865 spi: Kconfig: Show dm-spi drivers if DM_SPI set
DM supported spi drivers are enbled only when DM_SPI enabled,
so added DM_SPI if condition in Kconfig to show thoese only
when it enabled.

Also re-order the config items as incresing alphabetic order.

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-07-01 21:39:04 +05:30
Jagan Teki
1360004233 spi: Makefile: Use object file alphabetic order
Use object files as incresing alphabetic order, so-that it's
easy for readability.

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-07-01 21:39:04 +05:30
Jagan Teki
f924a20908 spi: Kconfig: Add TI_QSPI entry
Added TI_QSPI entry on Kconfig with help description.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-07-01 21:39:04 +05:30
Jagan Teki
075143d3cf spi: Kconfig: Add XILINX_SPI entry
Added XILINX_SPI entry on Kconfig with help description.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Michal Simek <michal.simek@xilinx.com>
2015-07-01 21:39:03 +05:30
Jagan Teki
de8230535b spi: Add Kconfig menu entry
Added Kconfig menu ... endmenu enties for spi support.

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-07-01 21:39:03 +05:30
Jagan Teki
df30a425bb spi: Kconfig: Add Zynq SPI controller entry
Add Zynq SPI controller Kconfig entry.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Marek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2015-07-01 21:15:03 +05:30
Jagan Teki
5f24d123c8 spi: xilinx_spi: Add asm/io.h include file
This patch includes asm/io.h for readl and writel calls.

build errors:
drivers/spi/xilinx_spi.c: In function 'xilinx_spi_probe':
drivers/spi/xilinx_spi.c:119:2: warning: implicit declaration of function 'writel' [-Wimplicit-function-declaration]
drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer':
drivers/spi/xilinx_spi.c:193:2: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration]

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Michal Simek <michal.simek@xilinx.com>
2015-07-01 21:15:03 +05:30
Jagan Teki
9505c36ed0 dm: spi: xilinx_spi: Convert to driver model
This converts the xilinx spi driver to use the driver model.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
2015-07-01 21:15:03 +05:30
Jagan Teki
cdc9dd0750 spi: zynq_spi: Add fdt support in driver
Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying "okay" on respective board dts to use
the devicetree generated platdata.

Ex:
&spi1 {
	status = "okay";
};

Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
2015-07-01 21:15:03 +05:30
Jagan Teki
b1c82da266 dm: spi: zynq_spi: Convert to driver model
This converts the zynq spi driver to use the driver model.

Minimal functional changes like using meaningful name on
structure members wrt mainlined dm spi drivers.
- input_hz -> frequency
- req_hz -> freq
- base -> regs

Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
2015-07-01 21:15:03 +05:30
Jagan Teki
ff6e31d3a1 spi: davinci_spi: Driver cleanup
Arrange driver code in more readable format[1] for easy accessing
and readable.
[1] http://patchwork.ozlabs.org/patch/265683/

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Rex Chang <rchang@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
2015-07-01 21:15:03 +05:30
Jagan Teki
e6d2fbf70a spi: davinci_spi: Move header code to driver
Move the header code into driver for more readable and
easy to access it.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Rex Chang <rchang@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
2015-07-01 21:15:02 +05:30
Jagan Teki
a7b6ef05bf spi: xilinx_spi: Driver clean-up
- Zap unneeded macros
- Re-arrange the code
- Removed __attribute__((weak))
- Replace __func__ macro with func names to save macro transition.
- Re-arranged comment lines.
- Arrange driver code in more readable format[1]

[1]  http://patchwork.ozlabs.org/patch/265683/

Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-07-01 21:15:02 +05:30
Jagan Teki
f93542a873 spi: xilinx_spi: Move header code to driver
Move the header code into driver for more readable and
easy to access it.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-07-01 21:15:02 +05:30
Jagan Teki
f23d532b63 spi: Zap oc_tiny_spi driver
Zap oc_tiny_spi driver since the boards used this driver
is no longer been active.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
2015-07-01 21:15:02 +05:30
Jagan Teki
4d934a9ffd spi: Zap ftssp010_spi driver
Zap ftssp010_spi driver since the boards used this driver
is no longer been active.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Kuo-Jung Su <dantesu@faraday-tech.com>
Cc: Axel Lin <axel.lin@ingics.com>
2015-07-01 21:15:02 +05:30
Jagan Teki
4ad479e3d6 spi: Zap andes_spi driver
Zap andes_spi driver since the boards used this driver
is no longer been active.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Macpaul Lin <macpaul@andestech.com>
2015-07-01 21:15:02 +05:30
Simon Glass
20edd1ac7a tegra: spi: Support slow SPI rates
Use the oscillator as the source clock when we cannot achieve a low-enough
speed with the peripheral clock. This happens when we request 3MHz on a SPI
clock, for example.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-06-09 09:56:13 -07:00
Simon Glass
635c2515c3 tegra: spi: Drop the claim_bus() method to correct delays
At present the driver does not properly honour the requested SPI CS
deactivation delay since the SPI bus is changed in the claim_bus() method.

Everything the claim_bus() method does can be done when the device is probed
(setting the speed and mode) and at the start of a new transfer (where the
fifo_status is already cleared). So drop this method.

Also, until the delay is complete, we should not touch the bus, so make sure
that spi_cs_activate() is called before other things are done in the xfer()
method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-06-09 09:56:13 -07:00
Simon Glass
60e2809a84 dm: spi: Avoid setting the speed with every transfer
Only set the speed if it has changed from last time. Since the speed will
be 0 when the device is probed it will always be changed on the first
transfer after the device is probed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-05-05 20:58:18 -06:00
Tom Rini
536266231a Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga 2015-04-28 20:48:43 -04:00
David Dueck
611c9ba2b8 spi: omap3: Fix timeout handling
The timeout value is never reset during the transfer. This means that when
transferring more data we eventually trigger the timeout.

This was reported on the mailing list:
"Spansion SPI flash read timeout with AM335x"

Signed-off-by: David Dueck <davidcdueck@googlemail.com>
CC: Tom Rini <trini@konsulko.com>
CC: Stefan Roese <sr@denx.de>
CC: Andy Pont <andy.pont@sdcsystems.com>
Tested-by: David Dueck <davidcdueck@googlemail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-04-27 21:08:42 +05:30
Simon Glass
9694b72442 dm: spi: Correct SPI claim/release_bus() methods
These methods should be passed a slave device, not a bus. This matches the
old SPI interface. It is important to know which device is claiming the bus
so passing a bus is not that useful.

Reported-by: Haikun Wang <haikun.wang@freescale.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-04-23 15:23:45 +05:30
Siva Durga Prasad Paladugu
8c48a68346 zynq: spi: Remove unnecessary error condition
Removed the unnecessary error check from spi_xfer
as the bitlen zero is possible now to deassert the
chip select for which no data is required to be transfered.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-04-22 16:49:51 +05:30
Marek Vasut
96bfdf01ca spi: Add Cadence QSPI controller Kconfig entry
Add Cadence QSPI controller Kconfig entry.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-04-21 12:23:38 +02:00
Marek Vasut
67d7a9d643 spi: Add Designware SPI controller Kconfig entry
Add DWC SPI controller Kconfig entry.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-04-21 12:23:36 +02:00
Simon Glass
892cac72e4 sandbox: Move CONFIG_SANDBOX_SPI to Kconfig
Move this over to Kconfig and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:38 -06:00
Haikun.Wang@freescale.com
5bc4830896 dm: spi: Convert Freescale QSPI driver to driver model
Move the Freescale QSPI driver over to driver model.

Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Tested-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:18 -06:00
Haikun.Wang@freescale.com
a891937110 dm: spi: Convert Freescale DSPI driver to driver model
Move the Freescale DSPI driver over to driver model.

Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:18 -06:00
Simon Glass
ba4575626e dm: x86: spi: Convert ICH SPI driver to driver model
Convert this driver over to use driver model. Since all x86 platforms use
it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent
code and remove the old x86 spi_init() function.

Note that this does not make full use of the new PCI uclass as yet. We still
scan the bus looking for the device. It should move to finding its details
in the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:14 -06:00
Simon Glass
e564f054af dm: core: Add dev_get_uclass_priv() to access uclass private data
Add a convenience function to access the private data that a uclass stores
for each of its devices. Convert over most existing uses for consistency
and to provide an example for others.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-16 19:27:42 -06:00
Simon Glass
87108cf20a x86: spi: Add support for lynxpoint
Add Lynxpoint to the driver so that the Asus Chromebox can be supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-04-16 19:27:40 -06:00
Albert ARIBAUD \(3ADEV\)
981219eebe lpc32xx: add LPC32xx SSP support (SPI mode)
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-04-10 14:23:20 +02:00
Axel Lin
52091ad146 spi: designware_spi: revisit FIFO size detection again
By specification the FIFO size would be in a range 2-256 bytes. From TX Level
prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes.
Hence there are currently two issues:
  a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be
     either 0 or 1 byte;
  b) FIFO size is incorrectly decreased by 1 which already done by meaning of
     TX Level register.

Fixes: 501943696e (spi: designware_spi: Fix detecting FIFO depth)
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-03-30 01:42:49 +05:30
Axel Lin
1478aeb32d spi: cf_spi: Staticize local functions
Make local functions static and remove unneeded forward declarations.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-03-30 01:42:49 +05:30
Axel Lin
bb1662760e spi: cf_spi: Use to_cf_spi_slave to resolve cfslave from slave
Don't assume slave is always the first member of struct cf_spi_slave.
Use container_of instead of casting first structure member.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-03-30 01:42:49 +05:30
Ravi Babu
46122960f0 qspi: dra7x: enable quad mode read for ti-qspi driver
This patch enables QUAD read mode for qspi to improve the
read performace while loading the binaries from qspi.

Signed-off-by: Ravi Babu <ravibabu@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-03-30 01:39:20 +05:30
Axel Lin
81a66446c3 spi: ftssp010_spi: Use to_ftssp010_spi() to ensure free correct address
Don't assume slave is always the first member of struct ftssp010_spi.
Use to_ftssp010_spi() to ensure free correct address in spi_free_slave().

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-03-30 01:39:20 +05:30
Axel Lin
aa8306a90e spi: davinci: Remove duplicate code to set bus and cs for slave
It's done in spi_alloc_slave().

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-03-30 01:39:20 +05:30
Axel Lin
a46988f11f spi: cf_qspi: Fixup to_cf_qspi_slave macro
The third parameter of container_of is the name of the member within the struct.
Current code only works if the parameter passed to to_cf_qspi_slave named slave.
Fix it.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-03-30 01:39:20 +05:30
Simon Glass
f94a1bed07 dm: Expand and complete Kconfig in drivers/
Expand the help messages for each driver. Add missing Kconfig for I2C,
SPI flash and thermal.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-02-12 10:35:33 -07:00
Bin Meng
728b393f3b x86: Add SPI support to quark/galileo
The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:45 -07:00
Simon Glass
5093badbb5 x86: spi: Support ValleyView in ICH SPI driver
The base address is found in a different way and the protection bit is also
in a different place. Otherwise it is very similar.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06 12:07:38 -07:00
Simon Glass
d0cff03e18 dm: spi: Move slave details to child platdata
At present we go through various contortions to store the SPI slave's chip
select in its private data. This only exists when the slave is active so
must be set up when it is probed. Until the device is probed we don't
actually know what chip select it will appear on.

However, now that we can support per-child platform data, we can use that
instead. This allows us to set up the chip select when the child is bound,
and avoid the messy contortions.

Unfortunately this is a fairly large change and it seems to be difficult to
break it down further.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:56 -07:00
Simon Glass
440714eeb8 dm: spi: Set up the spi_slave device pointer in child_pre_probe()
At present we use struct spi_slave as our device pointer in a lot of places
to avoid changing the old SPI API. At some point this will go away.

But for now, it is better if the SPI uclass sets up this pointer, rather
than relying on passing it into the device when it is probed. We can use the
new uclass child_pre_probe() method to do this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:56 -07:00
Simon Glass
19a25f672c dm: spi: Move the per-child data size to the uclass
This is common to all SPI drivers and specifies a structure used by the
uclass. It makes more sense to define it in the uclass.

Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:55 -07:00
Simon Glass
9cc36a2b89 dm: core: Add a flag to control sequence numbering
At present we try to use the 'reg' property and device tree aliases to give
devices a sequence number. The 'reg' property is often actually a memory
address, so the sequence numbers thus-obtained are not useful. It would be
better if the devices were just sequentially numbered in that case. In fact
neither I2C nor SPI use this feature, so drop it.

Some devices need us to look up an alias to number them within the uclass.
Add a flag to control this, so it is not done unless it is needed.

Adjust the tests to test this new behaviour.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-29 17:09:55 -07:00
Simon Glass
050fb909b6 dm: spi: Remove use of fdtdec GPIO support
These functions are going away, so use the new uclass support instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:52 -07:00
Simon Glass
8e899af059 x86: spi: Add device tree support
As a temporary measure before the ICH driver moves over to driver model,
add device tree support to the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:45 -07:00
Peng Fan
5f7f70c171 qspi:fsl implement AHB read
The QSPI controller in i.MX 6SoloX and Vybrid supports reading data using
IP register and AHB bus.

The original driver only supports reading data from IP interface. The IC
team suggests to use AHB read which is faster then IP read. Using AHB read,
we can directly memcpy, a "missed" access to the buffer will cause the
controller to clear the buffer and use the SEQID stored in bfgencr register
to initiate a read from flash device.

Since AHB bus is 64 bit width, we can not set MCR register using 32bit. In
order to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit Little
endian but not 32bit Little endia.

Introduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to
use AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore it.
Actually if Vybrid is migrated to use AHB read, this option can be removed and
IP read function can be discared. The reason to introduce this option
is that only i.MX SOC is tested in my side, no Vybrid platform for me.

In spi_setup_slave, the original piece code to set AHB is deleted, since
Vybrid platform does not use this to intiate AHB read. Instead, add
qspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-09 00:03:28 +05:30
Axel Lin
78c80114b5 spi: ftssp010_spi: Simplify code flow in ftssp010_[wait|wait_tx|wait_rx]
No functional change, just simplify the code a bit.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-08 12:02:55 +05:30
Axel Lin
1dc7d00f27 spi: cadence_qspi: Fix checking return value of fdt_first_subnode()
fdt_first_subnode() returns -FDT_ERR_NOTFOUND if no subnode found.
0 is supposed to be a valid offset returns from fdt_first_subnode().

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-07 12:30:54 +05:30
Peng Fan
a235878387 spi:fsl-quadspi support bank register read write
To support bigger than 16MB size qspi flashes, spi framework uses bank
switch to access higher bank or lower bank.

In this patch, QSPI_CMD_BRRD, QSPI_CMD_BRWR, QSPI_CMD_WREAR, QSPI_CMD_RDEAR
is initialized in LUT register with related pad and length configuration.
qspi_op_pp is originally for page programming, this patch reuses this function
for bank register switch and renamed it with qspi_op_write.

Since bank or EAR register is only 1 byte length, however original qspi_op_pp
or now renamed qspi_op_write only support 4 bytes lenght as the access unit,
this will trigger data abort exception when access EAR or bank register.
This is because upper framework passes a 1 bytes pointer to qspi_op_write,
however qspi_op_write treat it as an int pointer. This patch fixes this for
accessing EAR or bank register.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-07 12:25:05 +05:30
Marek Vasut
7411486253 dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'.
Fix the naming before we have to support both names.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-06 16:02:58 +05:30
Axel Lin
501943696e spi: designware_spi: Fix detecting FIFO depth
Current code tries to find the highest valid fifo depth by checking the value
it wrote to DW_SPI_TXFLTR. There are a few problems in current code:
1) There is an off-by-one in dws->fifo_len setting because it assumes the latest
   register write fails so the latest valid value should be fifo - 1.
2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary
   to test fifo == 257. In the case fifo is 257, it means the latest valid
   setting is fifo = 256. So after the for loop iteration, we should check
   fifo == 2 case instead of fifo == 257 if detecting the FIFO depth fails.
This patch fixes above issues.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-06 15:52:27 +05:30
Peng Fan
ba4dc8ab72 imx:qspi add 4K erase support
Add 4k erase command support for qspi driver. reuse the 64k erase function,
but change the function name from qspi_op_se to qspi_op_erase, since it
supports 64k and 4k erase.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:52:32 +05:30
Peng Fan
b93ab2ee75 arm:mx6sx add QSPI support
Add QSPI support for mx6solox.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:52:32 +05:30
Peng Fan
ed0c81c654 QuadSPI: use correct amba_base
According cs, use different amba_base to choose the corresponding
flash devices.  If not, `sf probe 1:0` and `sf probe 1:1` will
choose the same flash device, but not different flash devices.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:52:32 +05:30
Peng Fan
53e3db7f64 QuadSPI: use QSPI_CMD_xx instead of flash opcodes
Use QSPI_CMD_xx instead of flash opcodes

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:52:32 +05:30
Tom Rini
3bfbf32b6f Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2014-12-16 09:41:00 -05:00
Bin Meng
7e7740397d x86: ich-spi: Add Intel Tunnel Creek SPI controller support
Add Intel Tunnel Creek SPI controller support which is an ICH7
compatible device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00
Bin Meng
996467172e x86: ich-spi: Set the tx operation mode for ich 7
ICH 7 SPI controller only supports byte program (02h) for SST flash.
Word program (ADh) is not supported.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-13 15:08:04 -07:00
Bin Meng
fa388bca3e x86: ich-spi: Set the rx operation mode for ich 7
ICH 7 SPI controller only supports array read command (03h).
Fast array read command (0Bh) is not supported.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-13 15:08:04 -07:00
Bin Meng
15c7c6b31a x86: ich-spi: Fix a bug of reading from a non-64 bytes aligned address
The ich spi controller driver spi_xfer() tries to align reading
address to 64 bytes when doing spi data in, which causes a bug of
either infinite loop or a huge size memcpy().

Actually the ich spi controller does not have such requirement of
64 bytes alignment when reading data from spi slave devices.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-12-13 15:08:04 -07:00
Stefan Roese
a72f80208d spi: designware_spi: Some fixes / changes
As suggested by Pavel, here some fixes to the designware SPI driver:

- Spelling fixes
- Comment for timeout added
- Removed n_bytes completely (bits_per_word is enough for this)
- Unput clock now not defined via macro. The function to
  get the clock value is now called directly from within the driver

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:47 +01:00
Stefan Roese
5bef6fd79f spi: Add designware master SPI DM driver used on SoCFPGA
This patch adds the driver for the Designware master SPI controller. This
IP core is integrated on the Altera SoCFPGA. This implementation is a
driver model (DM) implementation. So multiple SPI drivers can be used.
Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
used to connect the SPI NOR flashes. Without DM, using multiple SPI
drivers is not possible.

This driver is very loosely based on the Linux driver. Most of the Linux
driver is removed. Only the polling loop for the transfer is really used
from this driver, as we don't support interrupts and DMA right now.

This is tested on the SoCrates SoCFPGA board using the SPI pins on the
P14 header.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:47 +01:00
Stefan Roese
10e8bf88c0 spi: Add Cadence QSPI DM driver used by SoCFPGA
This driver is cloned from the Altera Rockerboard.org U-Boot
repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some
modification to support the U-Boot driver model (DM).

As mentioned above, in this new version I ported this driver to the
new driver model (DM). One big advantage of this move is that now
multiple SPI drivers can be enabled on one platform. And since the
SoCFPGA also has the Designware SPI master controller integrated,
this feature is really needed to support both controllers.

Because of this, this series needs the DT support for SoCFPGA
to be applied. For DT based probing in the SPI DM.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:46 +01:00
Felipe Balbi
d11ac4b56d arm: omap: add support for am57xx devices
just add a few ifdefs around because this
device is very similar to dra7xxx.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:14 -05:00
Tom Rini
1739564e75 Merge git://git.denx.de/u-boot-dm
Conflicts:
	drivers/serial/serial-uclass.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-11-24 12:01:48 -05:00
Masahiro Yamada
b41411954d linux/kernel.h: sync min, max, min3, max3 macros with Linux
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does.  This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.

Many of references of those macros must be fixed to suppress warnings.
We have two options:
 - Use min, max, min3, max3 only when the arguments have the same type
   (or add casts to the arguments)
 - Use min_t/max_t instead with the appropriate type for the first
   argument

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
2014-11-23 06:48:30 -05:00
Simon Glass
6b18656aff dm: spi: Use device_bind_driver() instead of our own function
The SPI function does the same thing, so we may as well just use the new
generic function. The 'cs' parameter was not actually used, so can be
dropped.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Heiko Schocher <hs@denx.de>
2014-11-22 10:16:48 +01:00
Simon Glass
ff56bba2d6 dm: spi: Correct handling of SPI chip selects in sandbox
This code was not updated when the chip select handling was adjusted. Fix
it to call the correct function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Heiko Schocher <hs@denx.de>
2014-11-22 10:16:47 +01:00
Heiko Schocher
f11dea4f3d spi, atmel: move CONFIG_SYS_SPI_WRITE_TOUT into common header
move CONFIG_SYS_SPI_WRITE_TOUT into drivers/spi/atmel_spi.h
and define a default value. Delete this define in the board
config files, where it is possible (all boards use currently
the same value).

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-11-17 08:47:16 -05:00
Markus Niebel
027a9a0024 SPI: mxc_spi: delay initialisation until claim bus
it is not correct to init for a specific slave in spi_setup_slave.
instead buffer the values and delay init until spi_claim_bus.

Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-27 22:37:03 +05:30
Markus Niebel
ba3451d3d8 SPI: mxc_spi: remove second reset from ECSPI config handler
the second reset prevents other registers to be written.
This will prevent to have the correct signal levels for
SCLK before writing to the config reg in spi_xchg_single.

Tested with GPIO based chipselect and SPI_MODE_3 on i.MX6S

Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-27 22:37:03 +05:30
Marek Vasut
cdcdad851f spi: altera: Move the config options to the top
Just move the configuration options scattered all over the driver
to the top of the source file. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-27 22:37:03 +05:30
Marek Vasut
bc76b821f0 spi: altera: Clean up the use of variable d
The variable d is used in rather questionable way. Rework the code
a bit so it's clearer what it does. Also, rename the variable from
d to data to make it's name less mysterious. Finally, change it's
data type to uint32_t , since it's accessed as a 32bit number.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-27 22:37:03 +05:30
Marek Vasut
80d7333808 spi: altera: Zap endless loop
The driver contained an endless loop when waiting for TX completion,
this is a bad idea since if the hardware fails, the loop might spin
forever. Add timeout and handle it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-27 22:37:03 +05:30
Marek Vasut
37dcc130e0 spi: altera: Clean up most checkpatch issues
This patch just zaps most of the checkpatch cries present in the
driver. There is one more left, which will be addressed separately.
There is no functional change.

This patch also adds a bunch of newlines all around the place, this
is to make the code much more readable.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-27 22:37:03 +05:30
Marek Vasut
2e13da13a9 spi: altera: Clean up bit definitions
Clean up the definitions of bits in the Altera SPI driver, there
is no need to put braces around numbers afterall. No functional
change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-27 22:37:02 +05:30
Marek Vasut
eef67029d6 spi: altera: Use struct-based register access
Zap the offset-based register access and use the struct-based one
as this is the preferred method.

No functional change, but there are some line-over-80 problems in
the driver, which will be addressed later.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-27 22:37:02 +05:30
Tom Rini
0ce4af99c0 Merge branch 'master' of git://git.denx.de/u-boot-imx 2014-10-27 09:08:42 -04:00
Masahiro Yamada
da333ae73c dm: add entries to Kconfig
Create entries of CONFIG_DM, CONFIG_DM_SERIAL, CONFIG_DM_GPIO
and CONFIG_DM_SPI.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-10-23 21:43:09 -06:00
Stefan Roese
4fd7717e8e spi: kirkwood_spi.c: Change KW_SPI_BASE to MVEBU_SPI_BASE
This makes is possible to use this SPI driver from other MVEBU SoC's as well.
As the upcoming Armada XP support will do.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
2014-10-23 09:59:21 -04:00
Stefan Roese
4aceea2088 spi: kirkwood_spi.c: Compile MPP (pin-mux) only for kirkwood SoC's
Compile the pin multiplexing only on Kirkwood platforms. As the
Armada XP doesn't need it.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
2014-10-23 09:59:21 -04:00
Stefan Roese
3e972cb9ba arm: marvell: Move arch-kirkwood/spi.h to arch-mvebu/spi.h
This move makes it possible to use this kirkwood SPI driver from other
MVEBU platforms as well. This will be used by the upcoming Armada XP
support.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
2014-10-23 09:59:20 -04:00
Stefan Roese
3dc23f7852 arm: marvell: Move arch/kirkwood.h to arch/soc.h
This move makes is possible to use this header not only from kirkwood
platforms but from all Marvell mvebu platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
2014-10-23 09:59:20 -04:00
Simon Glass
fda6fac39b dm: tegra: spi: Convert to driver model
This converts the Tegra SPI drivers to use driver model. This is tested
on:

- Tegra20 - trimslice
- Tegra30 - beaver
- Tegra124 - dalmore

(not tested on Tegra124)

Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:36:52 -06:00
Simon Glass
73186c9460 dm: exynos: Convert SPI to driver model
Move the exynos SPI driver over to driver model. This removes quite a bit
of boilerplate from the driver, although it adds some for driver model.

A few device tree additions are needed to make the SPI flash available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:49 -06:00
Simon Glass
623b638607 dm: spi: Add soft_spi implementation
Add a new implementation of soft_spi that uses device tree to specify the
GPIOs. This will replace soft_spi_legacy for boards which use driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:48 -06:00
Simon Glass
44ba6b0ecc dm: spi: Remove SPI_INIT feature
This feature provides for init of a single SPI port for the soft SPI
feature. It is not really compatible with driver model since it assumes a
single SPI port. Also, inserting SPI init into the driver by means of
a #define is not very nice.

This feature is not used by any active boards, so let's remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:48 -06:00
Simon Glass
a666f39e4e dm: spi: Rename soft_spi.c to soft_spi_legacy.c
Reserve the 'normal' name for use by driver model, and rename the old
driver so that it is clear that it is for 'legacy' drivers only.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:48 -06:00
Simon Glass
49b5d6e6e2 dm: sandbox: spi: Move to driver model
Adjust the sandbox SPI driver to support driver model and move sandbox over
to driver model for SPI.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:48 -06:00
Simon Glass
c60e1f2547 dm: sandbox: Add a SPI emulation uclass
U-Boot includes a SPI emulation driver already but it is not explicit, and
is hidden in the SPI flash code.

Conceptually with sandbox's SPI implementation we have a layer which
creates SPI bus transitions and a layer which interprets them, currently
only for SPI flash. The latter is actually an emulation, and it should be
possible to add more than one emulation - not just SPI flash.

Add a SPI emulation uclass so that other emulations can be plugged in to
support different types of emulated devices on difference buses/chip
selects.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:46 -06:00
Simon Glass
d7af6a4851 dm: spi: Add a uclass for SPI
Add a uclass which provides access to SPI buses and includes operations
required by SPI.

For a time driver model will need to co-exist with the legacy SPI interface
so some parts of the header file are changed depending on which is in use.
The exports are adjusted also since some functions are not available with
driver model.

Boards must define CONFIG_DM_SPI to use driver model for SPI.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
(Discussed some follow-up comments which will address in future add-ons)
2014-10-22 10:36:46 -06:00
Eric Nelson
3acb011c3c ARM: i.MX: provide declaration for board_spi_cs_gpio
Provide a public declaration of the board_spi_cs_gpio()
callback for i.MX SPI chip selects to prevent the warning
"Should it be static?" when compiling with "make C=1".

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2014-10-21 10:47:14 +02:00
Masahiro Yamada
ed36323f6d kconfig: add blank Kconfig files
This would be useful to start moving various config options.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-09-24 18:30:28 -04:00
Stefan Roese
bf9b86dc47 spi: kirkwood_spi.c: cosmetic: Fix minor coding style issues
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Tested-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24 17:48:56 +05:30
Stefan Roese
0299046e5b spi: kirkwood_spi.c: Make global variable static
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Tested-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24 17:48:27 +05:30
Stefan Roese
c032174f82 spi: kirkwood_spi.c: Some fixes and cleanup
This patch introduces the clrsetbits_le32() accessor functions in the
kirkwood SPI driver. Note that it also includes a fix:

-	 writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl);
+	 writel(KWSPI_SMEMRDY, &spireg->ctrl);

Here the bit KWSPI_CSN_ACT (0x1) should have been cleared. Instead
0xfffffffe is written into this control register. This is the main
reason to use the clrsetbits() functions now. As they make clearing
bits much less error prone.

Additionally KWSPI_IRQUNMASK is not used in spi_cs_activate() and
spi_cs_deactivate() any more. Its the wrong macro but has the same
value as the correct one (KWSPI_CSN_ACT).

This is in preparation for use of this driver on the Marvell Armada XP
platform as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Tested-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24 17:47:53 +05:30
Nikita Kiryanov
155fa9af95 spi: mxc: fix sf probe when using mxc_spi
MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
across multiple transactions. This is set up by embedding the GPIO information
in the CS value:

cs = (cs | gpio << 8)

This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is required, invoking "sf probe <cs>" will not work, because
the CS argument doesn't have the GPIO information in it. Instead, the user must
use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force
cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must
type "sf probe 15872".

This is inconsistent with the description of the sf probe command, and forces
the user to be aware of implementaiton details.

Fix this by introducing a new board function: board_spi_cs_gpio(), which will
accept a naked CS value, and provide the driver with the relevant GPIO, if one
is necessary.

Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Eric Benard <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24 17:25:39 +05:30
Heiko Schocher
f659b57361 spi, spi_mxc: do not hang in spi_xchg_single
if status register do never set MXC_CSPICTRL_TC, spi_xchg_single
endless loops. Add a timeout here to prevent endless hang.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Dirk Behme <dirk.behme@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Simon Glass
22052c6236 spi: Support half-duplex mode in FDT decode
This parameter should also be supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Simon Glass
a4e29db257 exynos: spi: Fix calculation of SPI transaction start time
The SPI transaction delay is supposed to be measured from the end of one
transaction to the start of the next. The code does not work that way, so
fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Sergey Kostanbaev
7237d22baa arm: ep9315: Return back Cirrus Logic EDB9315A board support
This patch returns back support for old ep93xx processors family

Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com>
Cc: albert.u.boot@aribaud.net
2014-07-04 23:45:48 +02:00
Albert ARIBAUD
304f936aea Merge remote-tracking branch 'u-boot-samsung/master'
Conflicts:
	boards.cfg

Conflict was trivial between goni maintainer change and
lager_nor removal.
2014-07-01 20:52:51 +02:00
Albert ARIBAUD
e99f30e105 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-07-01 15:11:18 +02:00
Albert ARIBAUD
ed1d98d801 Merge branch 'u-boot/master' into 'u-boot-arm/master' 2014-06-25 10:39:58 +02:00
Akshay Saraswat
e76d2a81bc Exynos: SPI: Fix reading data from SPI flash
SPI recieve and transfer code in exynos_spi driver has a logical bug.
We read data in a variable which can hold an integer. Then we assign
this integer 32 bit value to another variable which has data type uchar.
Latter represents a unit of our recieve buffer. Everytime when we write
a value to our recieve buffer we step ahead by 4 units when actually we
wrote to one unit. This results in the loss of 3 bytes out of every 4
bytes recieved. This patch intends to fix this bug.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-06-23 07:47:05 +09:00
Axel Lin
7a4861fad0 spi: davinci: Fix register address for SPI1_BUS
Fix a trivial copy-paste bug.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
2014-06-19 17:53:59 -04:00
Tom Rini
28b62f0de3 Merge branch 'master' of git://git.denx.de/u-boot-spi 2014-06-11 11:40:11 -04:00
Alison Wang
6b57ff6fd5 arm: vf610: Add QSPI driver support
Add Freescale QSPI driver support for VF610.

Signed-off-by: Alison Wang <Huan.Wang@freescale.com>
Signed-off-by: Chao Fu <b44548@freescale.com>
2014-06-09 09:18:09 +02:00
Andrew Ruder
c1c0dd2644 spi: soft_spi: Support NULL din/dout buffers
This mirrors the conventions used in other SPI drivers (kirkwood,
davinci, atmel, et al) where the din/dout buffer can be NULL when the
received/transmitted data isn't important.  This reduces the need for
allocating additional buffers when write-only/read-only functionality is
needed.

In the din == NULL case, the received data is simply not stored.  In the
dout == NULL case, zeroes are transmitted.

Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-06-08 23:12:27 +05:30
Tom Rini
55e8250bd3 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-06-08 07:58:41 -04:00
Sourav Poddar
ce3cc8ecf5 ti: qspi: populate slave device to set flash quad bit.
The patch populates the slave data which will be used by flash driver to
set the  flash quad enable bit.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
2014-06-06 17:46:14 -04:00
Hou Zhiqiang
afb907061a powerpc/espi: remove 80us delay to improve transfer performance
Replace 80 mircoseconds delay with polling flag ESPI_EV_TXE.

Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 12:56:20 -07:00
Albert ARIBAUD
c9aab0f9dd Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-04-21 21:01:35 +02:00
Karicheri, Muralidharan
2bcdf84d58 spi: davinci: add support for multiple bus and chip select
Currently davinci spi driver supports only bus 0 cs 0.
This patch allows driver to support bus 1 and bus 2 with
configurable number of chip selects. Also defaults are
selected in a way to avoid regression on other platforms
that uses davinci spi driver and has only one spi bus.

Signed-off-by: Rex Chang <rchang@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-04-17 17:24:39 -04:00
Poddar, Sourav
b545a98f5d spi: ti_qspi: Add delay for successful bulk erase.
Bulk erase is not happening properly on dra7 due to erase timing constraints,
add a delay so that erase timing constraints are properly met.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Yebio Mesfin <ymesfin@ti.com>
2014-04-17 17:20:18 -04:00
Stephen Warren
70ad375ee4 ARM: tegra: Tegra20 pinmux cleanup
This renames all the Tegra20 pinmux pins and functions so they have a
prefix which matches the type name.

The entries in tegra20_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-17 08:41:05 -07:00
Albert ARIBAUD
ab6423cae0 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Trivial merge conflict, needed to manually remove
local_info as per commit 41364f0f.

Conflicts:
	board/samsung/common/board.c
2014-03-25 10:53:15 +01:00
Simon Glass
6e16d90aca sandbox: Add implementation of spi_setup_slave_fdt()
This function is needed when CONFIG_OF_SPI is defined.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:50 -06:00
Axel Lin
7dfc4dbd2d spi: atmel_dataflash: Simplify AT91F_SpiEnable implementation
Refactor the code a bit to make it better in readability.
Remove the comments because now the intention of the code is pretty clear.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-03-17 21:54:57 +05:30
Vasili Galka
ce6889a997 drivers/spi/omap3: Bug fix of premature write transfer completion
The logic determining SPI "write" transfer completion was faulty. At
certain conditions (e.g. slow SPI clock freq) the transfers were
interrupted before completion. Both EOT and TXS flags of channel
status registeer shall be checked to ensure that all data was
transferred. Tested on AM3359 chip.

Signed-off-by: Vasili Galka <vasili@visionmap.com>
2014-03-12 16:22:12 -04:00
Tom Rini
4c89a369c7 Merge branch 'master' of git://git.denx.de/u-boot-spi 2014-02-21 08:00:22 -05:00
Sonic Zhang
d6a320d5bb blackfin: add spi and i2c specific get clock functions
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-02-20 06:46:56 +01:00
Sourav Poddar
bb7cd0ddf9 spi: ti_qspi: Add delay before xfer for am43xx
Without this delay, write/read is failing.
Looks like, the WIP always remain set and hence a timeout
occurs leading to the error.

Without this patch, device does not get probed also.
Here is the log.

U-Boot#
U-Boot#
U-Boot#
U-Boot# sf probe 0
SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff
Failed to initialize SPI flash at 0:0
U-Boot# sf probe 0

While with this patch, log is
U-Boot# sf probe 0
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000
U-Boot# sf erase 0 0x80000
SF: 524288 bytes @ 0x0 Erased: OK
U-Boot# mw 81000000 0xdededede 0x40000
U-Boot# sf write 81000000 0 0x40000
SF: 262144 bytes @ 0x0 Written: OK
U-Boot# sf read 82000000 0 0x40000
SF: 262144 bytes @ 0x0 Read: OK
U-Boot# md 0x82000000

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-02-18 22:41:09 +05:30
Sourav Poddar
570533b820 spi: ti_qspi: Add AM43xx specifics changes
Add AM43xx specific changes.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-02-18 22:41:09 +05:30
Markus Niebel
5d584ccec1 spi: spi-mxc: implement clk control for ECSPI to fix SPI_MODE_3
SPI_MODE_3 requires clk high when inactive. The SCLK_CTL
field of the config reg was not configured in case of CPOL.
Fix configuration so that SPI_MODE_3 which uses CPOL configures
the clk line to be high in inactive state.

Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-02-18 22:29:26 +05:30
Michal Simek
999c39a45f spi: xilinx: Move timeout calculation out of the loop
Timeout calculation should be out of the data loop.
This patch increase spi bandwidth for 30%.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-02-18 22:24:28 +05:30
Tom Rini
4913fc23f0 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-01-16 13:50:16 -05:00
Nobuhiro Iwamatsu
22e75d6d60 spi: sh_qspi: Add header file that defines the address of registers
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-01-16 08:07:20 +09:00
Axel Lin
12f00caf61 spi: sh_spi: Use sh_spi_clear_bit() instead of open-coded
We have a sh_spi_clear_bit() function, there's no reason not to use it.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-11 12:21:31 +05:30
Kuo-Jung Su
66cb9eb1d6 spi: Add Faraday SPI controller support
The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF. However This
patch implements only the SPI mode.

NOTE:
The DMA and CS/Clock control logic has been altered
since hardware revision 1.19.0. So this patch
would first detects the revision id of the underlying
chip, and then switch to the corresponding software
control routines.

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
CC: Tom Rini <trini@ti.com>
2014-01-11 12:21:30 +05:30
Yen Lin
60acde43d7 spi: tegra: clear RDY bit prior to every transfer
The RDY bit indicates that a transfer is complete. This needs to be
cleared by SW before every single HW transaction, rather than only
at the start of each SW transaction (those being made up of n HW
transactions).

It seems that earlier HW may have cleared this bit autonomously when
starting a new transfer, and hence this code was not needed in practice.
However, this is generally a good idea in all cases. In Tegra124, the
HW behaviour appears to have changed, and SW must explicitly clear this
bit. Otherwise, SW will believe that transfers have completed when they
have not, and may e.g. read stale data from the RX FIFO.

Signed-off-by: Yen Lin <yelin@nvidia.com>
[swarren, rewrote commit description, unified duplicate RDY clearing code
and moved it right before the start of the HW transaction, unconditionally
exit loop after reading RX data, rather than checking if TX FIFO is empty,
since it is guaranteed to be]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-12-19 00:00:51 +05:30
Nobuhiro Iwamatsu
16f47c9c51 spi: Add support SH Quad SPI driver
This patch adds a driver for Renesas SoC's Quad SPI bus.
This supports with 8 bits per transfer to use with SPI flash.

Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-12-18 23:23:41 +05:30
Tom Rini
65b7fe28a1 Merge branch 'spi' of git://git.denx.de/u-boot-x86 2013-12-10 09:36:23 -05:00
Mike Frysinger
6122813fa2 sandbox: spi: Add SPI emulation bus
This adds a SPI framework for people to hook up simulated SPI clients.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-12-09 12:22:18 -07:00
Simon Glass
0efc02499f spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT node
This allows us to put the SPI flash chip inside the SPI interface node,
with U-Boot finding the correct bus and chip select automatically.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-12-09 12:22:12 -07:00
Axel Lin
9bac8f7769 spi: bfin_spi6xx: Remove unnecessary test for bus and pins[bus]
For invalid bus number, current code returns NULL in the default case of
switch-case statements. In additional, pins[bus] is always not NULL because
it is the address of specific row of the two-dimensional array.
Thus this patch removes these unnecessary test.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-12-06 16:06:51 +08:00
Axel Lin
727cbe14b2 spi: bfin_spi: Remove unnecessary test for bus and pins[bus]
For invalid bus number, current code returns NULL in the default case of
switch-case statements. In additional, pins[bus] is always not NULL because
it is the address of specific row of the two-dimensional array.
Thus this patch removes these unnecessary test.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-12-06 16:06:51 +08:00
Nikita Kiryanov
5753d09b10 spi: omap3: add support for more word lengths
Current implementation only supports 8 bit word lengths, even though
omap3 can handle anything between 4 and 32.

Update the spi interface to support changing the SPI word length,
and implement it in omap3_spi driver to support the full range of
possible word lengths.
This implementation is backwards compatible by defaulting to the old
behavior of 8 bit word lengths.
Also, it required a change to the omap3_spi non static I/O functions,
but since they are not used anywhere else, no collateral changes are required.

Cc: Tom Rini <trini@ti.com>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2013-11-12 10:02:44 +01:00
Nikita Kiryanov
54a759c880 spi: omap3: remove semicolon from #define
Remove unnecessary semicolon from #define SPI_WAIT_TIMEOUT

Cc: Tom Rini <trini@ti.com>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Gerhard Sittig <gsi@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2013-11-12 10:00:36 +01:00
Masahiro Yamada
710f1d3d5f drivers: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 13:26:01 -04:00
Timo Herbrecher
6d5ce1bd00 spi: mxc_spi: Fix double incrementing read pointer for unaligned buffers
If dout buffer is not 32 bit-aligned or data to transmit is not multiple
of 32 bit the read data pointer is already incremented on single byte reads.

Signed-off-by: Timo Herbrecher <t.herbrecher@gateware.de>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-16 00:14:30 +05:30
Jagannadha Sutradharudu Teki
e7b1e452ff spi: Add GPL-2.0+ SPDX-License-Identifier for missing files
Added GPL-2.0+ SPDX-License-Identifier for missed spi
source files.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-16 00:14:01 +05:30
Wolfgang Denk
93e1459641 Coding Style cleanup: replace leading SPACEs by TABs
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: Tom Rini <trini@ti.com>
2013-10-14 16:06:54 -04:00
Wolfgang Denk
3765b3e7bd Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:53 -04:00
Rajeshwari Shinde
c4a796329d spi: exynos: Support word transfers
Since SPI register access is so expensive, it is worth transferring data
a word at a time if we can. This complicates the driver unfortunately.

Use the byte-swapping feature to avoid having to convert to/from big
endian in software.

This change increases speed from about 2MB/s to about 4.5MB/s.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-08 18:18:12 +05:30
Rajeshwari Shinde
120af1572a spi: exynos: Minimise access to SPI FIFO level
Accessing SPI registers is slow, but access to the FIFO level register
in particular seems to be extraordinarily expensive (I measure up to
600ns). Perhaps it is required to synchronise with the SPI byte output
logic which might run at 1/8th of the 40MHz SPI speed (just a guess).

Reduce access to this register by filling up and emptying FIFOs
more completely, rather than just one word each time around the inner
loop.

Since the rxfifo value will now likely be much greater that what we read
before we fill the txfifo, we only fill the txfifo halfway. This is
because if the txfifo is empty, but the rxfifo has data in it, then writing
too much data to the txfifo may overflow the rxfifo as data arrives.

This speeds up SPI flash reading from about 1MB/s to about 2MB/s on snow.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-08 18:18:11 +05:30
Rajeshwari Shinde
8d203afdd3 spi: exynos: Support a delay after deactivate
For devices that need some time to react after a spi transaction
finishes, add the ability to set a delay.

Implement this as a delay on the first/next transaction to avoid
any delay in the fairly common case where a SPI transaction is
followed by other processing.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-08 18:18:11 +05:30
Matt Porter
1d0933eaf9 spi: add TI QSPI driver
Adds a SPI master driver for the TI QSPI peripheral.
- Added quad read support.
- Added memory mapped support.

Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-07 17:55:51 +05:30
Marek Vasut
a928a36ff9 spi: mxs_spi: Configure chipselect after block reset
The chipselect must be written into the CTRL0 register after the SSP
block is reset, otherwise the block will always use ChipSelect #0.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-08-27 19:39:39 +05:30
Prabhakar Kushwaha
997399fa42 powerpc: Fix CamelCase checkpatch warnings
85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions.
because of this code checkpatch script generates "WARNING: Avoid CamelCase".

Convert variables name to normal naming convention and modify board, driver
files with updated the new structure.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:57:51 -07:00
Jagannadha Sutradharudu Teki
1465d055f9 spi: Add zynq spi controller driver
Zynq spi controller driver supports 2 buses and
3 chipselects on each bus.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-08-07 01:09:47 +05:30
Axel Lin
583fe6c3d8 spi: mpc8xxx_spi: Use DIV_ROUND_UP instead of open-coded
Use DIV_ROUND_UP to simplify the code.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
2013-08-06 23:58:24 +05:30
Axel Lin
a444aa7a1c spi: fsl_espi: Use DIV_ROUND_UP instead of open-coded
Use DIV_ROUND_UP to simplify the code.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
2013-08-06 23:58:09 +05:30
Axel Lin
327b5c9f7c spi: bfin_spi: Use DIV_ROUND_UP instead of open-coded
Use DIV_ROUND_UP to simplify the code.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-07-31 16:56:04 +08:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Tom Rini
fbbbc86e8e Merge branch 'master' of git://git.denx.de/u-boot-arm
Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and
serial.

Conflicts:
	arch/arm/dts/exynos5250.dtsi

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-12 10:36:48 -04:00
Albert ARIBAUD
e6c7f86f03 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-06-28 17:51:13 +02:00
Dirk Behme
9a30903b44 spi: mxc_spi: Update pre and post divider algorithm
The spi clock divisor is of the form x * (2**y),  or  x  << y, where x is
1 to 16, and y is 0 to 15. Note the similarity with floating point numbers.
Convert the desired divisor to the smallest number which is >= desired divisor,
and can be represented in this form. The previous algorithm chose a divisor
which could be almost twice as large as needed.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
2013-06-26 16:23:30 +02:00
Dirk Behme
8d4c4ffb95 spi: mxc_spi: Fix pre and post divider calculation
Fix two issues with the calculation of pre_div and post_div:

1. pre_div: While the calculation of pre_div looks correct, to set the
CONREG[15-12] bits pre_div needs to be decremented by 1:

The i.MX 6Dual/6Quad Applications Processor Reference Manual (IMX6DQRM
Rev. 0, 11/2012) states:

CONREG[15-12]: PRE_DIVIDER
0000 Divide by 1
0001 Divide by 2
0010 Divide by 3
...
1101 Divide by 14
1110 Divide by 15
1111 Divide by 16

I.e. if we want to divide by 2, we have to write 1 to CONREG[15-12].

2. In case the post divider becomes necessary, pre_div will be divided by
16. So set pre_div to 16, too. And not 15.

Both issues above are tested using the following examples:

clk_src = 60000000 (60MHz, default i.MX6 ECSPI clock)

a) max_hz == 23000000 (23MHz, max i.MX6 ECSPI read clock)

-> pre_div =  3 (divide by 3 => CONREG[15-12] == 2)
-> post_div = 0 (divide by 1 => CONREG[11- 8] == 0)
               => 60MHz / 3 = 20MHz SPI clock

b) max_hz == 2000000 (2MHz)

-> pre_div =  16 (divide by 16 => CONREG[15-12] == 15)
-> post_div = 1  (divide by  2 => CONREG[11- 8] == 1)
               => 60MHz / 32 = 1.875MHz SPI clock

c) max_hz == 1000000 (1MHz)

-> pre_div =  16 (divide by 16 => CONREG[15-12] == 15)
-> post_div = 2  (divide by  4 => CONREG[11- 8] == 2)
               => 60MHz / 64 = 937.5kHz SPI clock

d) max_hz == 500000 (500kHz)

-> pre_div =  16 (divide by 16 => CONREG[15-12] == 15)
-> post_div = 3  (divide by  8 => CONREG[11- 8] == 3)
               => 60MHz / 128 = 468.75kHz SPI clock

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
2013-06-26 16:22:51 +02:00
Hung-ying Tyan
f3424c554c cros: exynos: add SPI support for cros_ec
This patch adds SPI support for carrying out the cros_ec protocol.

Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:13:24 -04:00
Axel Lin
9675fed474 spi: mxc_spi: Use DIV_ROUND_UP at appropriate places
This change slightly improves readability.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-06-22 23:08:01 +05:30
Axel Lin
0cb8394f81 spi: cf_qspi: Use DIV_ROUND_UP at appropriate place
This change slightly improves readability.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-06-22 23:08:01 +05:30
Tom Rini
f0df254663 Merge branch 'master' of git://git.denx.de/u-boot-spi 2013-06-13 15:18:35 -04:00
Axel Lin
ba1d1c2d9b spi: tegra20_sflash: Remove redundant code to set bus and cs of struct spi_slave
It's done in spi_alloc_slave(), thus remove the redundant code.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-06-13 22:55:30 +05:30
Axel Lin
d6f64d4a11 spi: tegra114_spi: Convert to use spi_alloc_slave()
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-06-13 22:55:24 +05:30
Axel Lin
0368292954 spi: armada100_spi: Remove unnecessary NULL test for dout and din
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-06-13 22:55:18 +05:30
Rajeshwari Shinde
e4eaef8910 spi: exynos: Support SPI_PREAMBLE mode
Support interfaces with a preamble before each received message.

We handle this when the client has requested a SPI_XFER_END, meaning
that we must close of the transaction. In this case we read until we
see the preamble (or a timeout occurs), skipping all data before and
including the preamble. The client will receive only data bytes after
the preamble.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-06-03 00:04:40 +05:30
Albert ARIBAUD
a19b0dd62d Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	common/cmd_fpga.c
	drivers/usb/host/ohci-at91.c
2013-05-30 14:45:06 +02:00
Scott Jiang
d4d4f90377 bfin: discard invalid data and clear RXS in bf5xx spi driver
There may be dirty data in RDBR, so we should discard invalid data.
This operation also clears RXS bit in STAT register.

Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13 16:26:27 +08:00
Scott Jiang
e76276df74 bfin: Remove spi dma function in bf5xx.
BF5xx rx dma causes spi flash random read error.
Accually spi controller has problems both on tx and rx dma.
So remove spi dma support in u-boot.

Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-05-13 16:26:27 +08:00
Bo Shen
e0d2d3bd29 spi: atmel_spi: using ip version to check whether has wdrbt
Using IP version to check whether it has wdrbt bit in mode register

Tested in at91sam9x5ek and at91sam9n12ek.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
[fix warning about incompatible parameter]
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-12 16:36:11 +02:00
Stefan Roese
0499218dbc imx: Move some header files from arch-mxs to imx-common
The following headers are moved to a i.MX common location:

- regs-common.h
- regs-apbh.h
- regs-bch.h
- regs-gpmi.h
- dma.h

This way this header can be re-used also by other i.MX platforms.
For example the i.MX6 which will need it for the upcoming NAND
support.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:22:22 +02:00
Albert ARIBAUD
8dc16cf9dd Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-04-14 10:38:37 +02:00
Fabio Estevam
0f1411bc8d spi: mxc_spi: Set master mode for all channels
The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi
clock glitch durant reset) solved, is back now and itwas re-introduced by
commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling).

Actually the glitch is happening due to always toggling between slave mode
and master mode by configuring the CHANNEL_MODE bits in this reset function.

Since the spi driver only supports master mode, set the mode for all channels
always to master mode in order to have a stable, "glitch-free" SPI clock line.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-13 17:46:42 +02:00
Albert ARIBAUD
1812201997 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	drivers/video/exynos_fb.c
2013-04-12 22:07:57 +02:00
Albert ARIBAUD
fed029f3c3 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-04-04 15:44:57 +02:00
Albert ARIBAUD
be08abc242 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-04-04 11:49:32 +02:00
Dirk Behme
d36b39bf0d spi: mxc_spi: Fix ECSPI reset handling
Reviewing the ECSPI reset handling shows two issues:

1. For the enable/reset bit (MXC_CSPICTRL_EN) in the control reg
   (ECSPIx_CONGREG) the i.MX6 technical reference manual states:

   -- cut --
   ECSPIx_CONREG[0]: EN: Writing zero to this bit disables the block
   and resets the internal logic with the exception of the ECSPI_CONREG.
   -- cut --

   Note the exception mentioned: The CONREG itself isn't reset.

   Fix this by manually writing the reset value 0 to the whole register.
   This sets the EN bit to zero, too (i.e. includes the old
   ~MXC_CSPICTRL_EN).

2. We want to reset the whole SPI block here. So it makes no sense
   to first read the old value of the CONREG and write it back, later.
   This will give us the old (historic/random) value of the CONREG back.
   And doesn't reset the CONREG.

   To get a clean CONREG after the reset of the block, too, don't use
   the old (historic/random) value of the CONREG while doing the reset.
   And read the clean CONREG after the reset.

This was found while working on a SPI boot device where the i.MX6 boot
ROM has already initialized the SPI block. The initialization by the
boot ROM might be different to what the U-Boot driver wants to configure.
I.e. we need a clean reset of SPI block, including the CONREG.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-04 10:23:09 +02:00
York Sun
472d546054 Consolidate bool type
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.

All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.

Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-04-01 16:33:52 -04:00
Vivek Gautam
7d17958408 spi: exynos: Fix compiler warnings for non-dt systems
Enclosing process_nodes() and spi_get_config() inside
CONFIG_OF_CONTROL, since they are compiled only for DT systems.

This fixes following warning:
exynos_spi.c:391:12: warning: 'process_nodes' defined but not used [-Wunused-function]

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-29 11:16:25 +09:00
Albert ARIBAUD
009d75ccc1 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	drivers/spi/tegra20_sflash.c
	include/fdtdec.h
	lib/fdtdec.c
2013-03-28 18:50:01 +01:00
Allen Martin
77c42e80b9 tegra114: add SPI driver
Add driver for tegra114 SPI controller.  This controller is not
compatible with either the tegra20 or tegra30 controllers, so it
requires a new driver.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:07 -07:00
Allen Martin
78f47b7353 spi: add common fdt SPI driver interface
Add a common interface to fdt based SPI drivers.  Each driver is
represented by a table entry in fdt_spi_drivers[].  If there are
multiple SPI drivers in the table, the first driver to return success
from spi_init() will be registered as the SPI driver.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:06 -07:00
Allen Martin
6b3a03e112 tegra20: spi: move fdt probe to spi_init
Make the tegra20 SPI driver similar to the tegra30 (and soon to be
tegra114) SPI drivers in preparation of common fdt SPI driver front
end.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:06 -07:00
Allen Martin
7a49ba6e5b tegra: spi: pull register structs out of headers
Move register structs from headers into .c files and use common name.
This is in preparation of making common fdt front end for SPI
drivers.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:05 -07:00
Allen Martin
2a3c5bc29c tegra: spi: remove non fdt support
Remove non fdt support from tegra20 and tegra30 SPI drivers in
preparation of new common fdt based SPI driver front end.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:05 -07:00
Allen Martin
ff1da6fb5f tegra: spi: rename tegra SPI drivers
Rename tegra SPI drivers to tegra20_flash and tegra20_slink in
preparation for commonization and addition of tegra114_spi.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:05 -07:00
Allen Martin
9000652da0 tegra: remove support for UART SPI switch
This feature was only used for tegra20 seaboard that had a pinmux
conflict on the SPI pins.  These boards were never manufactured, so
remove this support to clean up SPI driver.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:05 -07:00
Simon Glass
5e6fb69778 x86: spi: Set maximum write size for ICH
This SPI controller can only write 64 bytes at a time. Add this restriction
in so that 'sf write' works correct for blocks larger than 64 bytes.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:37 -07:00
Simon Glass
1853030e21 x86: spi: Add Intel ICH driver
This supports Intel ICH7/9. The Intel controller is a little unusual in
that it is mostly intended for use with SPI flash, and has some
optimisations and features specifically for that application. In
particular it is not possible to support ongoing transactions that
continue over many calls with SPI_XFER_BEGIN and SPI_XFER_END.

This driver supports writes of up to 64 bytes at a time, the limit
for the controller. Future work will improve this.

Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:36 -07:00
Simon Glass
d3504fee73 spi: Use spi_alloc_slave() in each SPI driver
Rather than each driver having its own way to allocate a SPI slave,
use the new allocation function everywhere. This will make it easier
to extend the interface without breaking drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:36 -07:00
Simon Glass
ba6c3ce9bd spi: Add function to allocate a new SPI slave
At present it is difficult to extend the SPI structure since all
drivers allocate it themselves, and few of them zero all fields. Add
a new function spi_alloc_slave() which can be used by SPI drivers
to perform this allocation, and thus ensure that all drivers can
better cope with SPI structure changes.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:36 -07:00
Albert ARIBAUD
6579d15c58 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-03-15 15:18:31 +01:00
Marek Vasut
d3f26a2700 mxs: spi: Remove CONFIG_MXS_SPI_DMA_ENABLE
The CONFIG_MXS_SPI_DMA_ENABLE is no longer relevant as the SPI DMA
has proven to work correctly. Remove this configuration option.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-03-07 17:22:56 +01:00
Marek Vasut
c96e78ccfe mxs: spi: Fix the MXS SPI for mx23
The MX23 has slightly different register layout. Adjust the SPI
driver to match the layout, both the PIO and DMA part.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-03-07 17:22:56 +01:00
Marek Vasut
3430e0bd2a mxs: mmc: spi: dma: Better wrap the MXS differences
This patch streamlines the differences between the MX23 and MX28 by
implementing a few helper functions to handle different DMA channel
mapping, different clock domain for SSP block and fixes a few minor
bugs.

First of all, the DMA channel mapping is now fixed in dma.h by defining
the actual channel map for both MX23 and MX28. Thus, MX23 now does no
longer use MX28 channel map which was wrong. Also, there is a fix for
MX28 DMA channel map, where the last four channels were incorrect.

Next, because correct DMA channel map is in place, the mxs_dma_init_channel()
call now bases the channel ID starting from SSP port #0. This removes the
need for DMA channel offset being added and cleans up the code. For the
same reason, the SSP0 offset can now be used in mxs_dma_desc_append(), thus
no need to adjust dma channel number in the driver either.

Lastly, the SSP clock ID is now retrieved by calling mxs_ssp_clock_by_bus()
which handles the fact that MX23 has shared SSP clock for both ports, while
MX28 has per-port SSP clock.

Finally, the mxs_ssp_bus_id_valid() pulls out two implementations of the
same functionality from MMC and SPI driver into common code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-03-07 17:22:56 +01:00
Scott Jiang
4a207e8b9a blackfin: add bf6xx spi driver
Spi driver for bf60x is different from old one, so implement a new
driver for it.

Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
2013-03-04 13:42:07 +08:00
Tom Rini
951c6baaf4 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-02-12 10:18:31 -05:00
Allen Martin
b19f57491a tegra: add SPI SLINK driver
Add driver for tegra SPI "SLINK" style driver.  This controller is
similar to the tegra20 SPI "SFLASH" controller.  The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices.  In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH.  Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.

This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings.  Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.

To enable this driver, use CONFIG_TEGRA_SLINK

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Allen Martin
8f1b46b104 tegra: spi: add fdt support to tegra SPI SFLASH driver
Add support for configuring tegra SPI driver from devicetree.
Support is keyed off CONFIG_OF_CONTROL.  Add entry in seaboard dts
file for spi controller to describe seaboard spi.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Jason Wu
85e9c65f8a spi: xilinx_spi: Perform software reset during slave setup
to make sure it is in the clear state.

Signed-off-by: Jason Wu <huanyu@xilinx.com>
2013-02-04 12:09:49 +01:00
Otavio Salvador
bf48fcb61b mxs: clock: Use 'mxs' prefix for methods
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Marek Vasut
14e26bcfa7 mxs: ssp: Pull out the SSP bus to regs conversion
Create function which converts SSP bus number to SSP register pointer.
This functionality is reimplemented multiple times in the code, thus
make one common implementation. Moreover, make it a switch(), since the
SSP ports are not mapped in such nice linear fashion on MX23, therefore
having it a switch will simplify things there.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:19 +01:00
Albert ARIBAUD
1199c377cf Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-01-14 15:21:00 +01:00
Albert ARIBAUD
612404c28a Merge 'u-boot-atmel/master' into 'u-boot-arm/master' 2013-01-09 20:01:48 +01:00
Albert ARIBAUD
9d86f0c30b kirkwood: make MPP arrays static const
This saves stack and code memory for local copy, and
consumes initialized data memory. For 22 of the 29
kirkwood-based boards, this results in a global saving
of about 30 bytes. For 7 of them, it results in an
increase of 6 to 14 bytes.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-01-09 04:12:10 +05:30
Rajeshwari Shinde
4d3acb9df3 SPI: EXYNOS: Add FDT support to driver.
This patch adds FDT support to the SPI driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-08 10:54:34 +09:00
ajoy
cc1182beea OMAP3 SPI : Fixed bugs related to SPI transfer
Added posted writes (read after writes) to effect the
change immediately for channel confiuration and channel
enable register

Disable the channel to purge receieve data in TX_ONLY
mode transfer otherwise rx data will get affected by
the next immediate RX_ONLY mode transfer

Wait for the EOT bit to be set after last byte has been
loaded to TX shift register in the the TX_ONLY mode.This
ensures TX data has been completely shifted out

Disable the channel in RX_ONLY mode before reading the
last data from  RXX register to prevent the SPI slave
to transmit next word

Signed-off-by: Ajoy Kumar Das <akdas75@yahoo.in>
Cc: Tom Rini <trini@ti.com>
Cc: jacopo mondi <j.mondi@voltaelectronics.com>
2012-12-10 08:55:25 -07:00
Bo Shen
ac81e1ccf7 spi: atmel: sam9m10g45 also support WDRBT bit
The at91sam9m10g45 also support WDRBT bit, add support for it

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-12-09 22:40:13 +01:00
Albert ARIBAUD
b8a7c46796 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2012-11-25 13:01:58 +01:00
Fabio Estevam
3cea335c34 spi: mxc_spi: Fix spi clock glitch durant reset
Measuring the spi clock line on a scope shows a 'glitch' during the reset of the
spi.

Fix this by toggling only the MXC_CSPICTRL_EN bit, so that the clock line becomes
always stable.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-11-19 08:49:00 +01:00
Fabio Estevam
de5bf02cb1 spi: mxc_spi: Fix handling of chip select
In decode_cs() function the polarity of the chip select must be taken into
account.

Also, for the case of low active chip select, the CS was activated too early.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-11-19 08:49:00 +01:00
Rajeshwari Shinde
1bf43b829e SPI: Add SPI Driver for EXYNOS.
This patch adds SPI driver for EXYNOS.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: jy0922.shim@samsung.com
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:21 +09:00
Albert ARIBAUD
c68436fa42 Merge remote-tracking branch 'u-boot-ti/master' 2012-10-26 07:00:28 +02:00
Peter Korsgaard
22cbeed454 omap3_spi: introduce CONFIG_OMAP3_SPI_D0_D1_SWAPPED
D0/D1 Swapped or not is a board property, not anything specific to
the am33xx SoC, so add a custom define for it.

At the same time correct the bit handling for the swapped mode
(DPE0 should be cleared and SI/DPE1 set).

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
2012-10-25 11:30:50 -07:00
Shaohui Xie
9905757e29 powerpc/espi: remove write command length check
Current espi controller driver assumes the command length of write command is
not equal to '1', it was made based on SPANSION SPI flash, but some SPI flash
driver such as SST does use write command length as '1', so write command on
SST SPI flash will not work. And the length check for write command is not
necessary for SPANSION, though it's harmless for SPANSION, it will stop write
operation on flashes like SST, so we remove the check.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 15:52:46 -05:00
Tom Warren
150c24936b Tegra20: Move some include files to arch-tegra for sharing with Tegra30
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs
that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20'
'root' file.

All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15 11:54:06 -07:00
Tom Rini
495dbd72dd Merge branch 'master' of git://git.denx.de/u-boot-arm 2012-09-21 14:53:13 -07:00
Albert ARIBAUD
d193c1b6eb Merge remote-tracking branch 'u-boot-imx/master' 2012-09-21 00:26:19 +02:00
Richard Retanubun
59d0612252 ColdFire: Queued SPI driver
This patch adds a driver for Freescale Colfire Queued SPI bus.
Coded to work with 8 bits per transfer to use with SPI flash.
CPOL, CPHA, and CS_ACTIVE_HIGH can be configured.

Tested with MCF5270 which have 4 chip selects.

Activate by #define CONFIG_CF_QSPI in board config.

Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>
2012-09-20 20:39:27 +08:00
Ira W. Snyder
f138ca1373 mpc8xxx_spi: fix SPI support on MPC8308RDB
The MPC8308RDB Reference Manual states that no bits in the SPMODE
register are allowed to change while the enable (EN) bit is set.

This driver changes the character length bits (LEN) while the enable
(EN) bit is set. Clearing the EN bit while changing the LEN bits makes
the driver work correctly on MPC8308RDB.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-09-18 16:16:44 -05:00
Stephan Linz
03afad2fc9 spi: xilinx: Remove unused variable
Warning is:

xilinx_spi.c: In function 'spi_setup_slave':
xilinx_spi.c:81: warning: unused variable 'regs'

Signed-off-by: Stephan Linz <linz@li-pro.net>
CC: Michal Simek <monstr@monstr.eu>
2012-09-11 09:24:56 +02:00
Tom Warren
29f3e3f248 Tegra: Change Tegra20 to Tegra in common code, prep for T30
Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.

Upcoming Tegra30 port will use common code/defines/names where possible.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2012-09-10 13:01:24 -07:00
Marek Vasut
e9f7eafd3c MX28: SPI: Fix the DMA chaining
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation.

Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.

Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.

Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2012-09-06 14:17:55 +02:00
Marek Vasut
88d1555968 MX28: SPI: Fix the DMA DCache race condition
This patch fixes dcache-related problem. The problem manifested
when dcache was enabled and the following command issued twice:

mw 0x42000000 0 0x4000 ; sf probe ; sf read 0x42000000 0x0 0x10000 ; sha1sum 0x42000000 0x10000

The SHA1 checksum was correct during the first call. Yet with
every subsequent call of the above command, it differed and was
wrong.

It turns out this was because of a race condition. On the first
time the command was called, no cacheline contained any data from
the destination memory location. The DMA transfered data into the
location and the cache above the location was invalidated. Then the
checksum was computed, but that meant the data were loaded into data
cache.

On any subsequent call, the DMA again transfered data into the same
destination. Yet during the transfer, some of the DCache lines were
evicted and written back into the main memory. Once the DMA transfer
completed, the data cache was invalidated over the memory location as
usual. But the data that were to be loaded back into the data cache
by subsequent SHA1 checksuming were corrupted.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2012-09-06 14:17:55 +02:00
Valentin Longchamp
8203b201ea kw_spi: fix clock prescaler computation
The computation was not correct with low clock values: setting a 1MHz
clock would result in an overlap that would then configure a 25Mhz
clock.

This patch implements a correct computation method according to the
kirkwood functionnal spec. table 600 (Serial Memory Interface
Configuration Register).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2012-09-03 17:28:51 +05:30
Bo Shen
65c575506d spi: atmel: add WDRBT bit to avoid receive overrun
The atmel at91sam9x5 series spi has feature to avoid receive overren

Using the patch to enable it

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01 17:06:14 +02:00
Marek Vasut
2c4321444a MX28: SPI: Supercharge the SPI driver
This change implements DMA chaining into SPI driver. This allows
the transfers to go much faster, while also fixing SF issues.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:29 +02:00
Matt Sealey
c6b52c4927 spi: fix mxs_spi_slave structure allocation to clear memory
Use calloc() instead of malloc() to allocate the mxs_spi_slave structure.
Clearing the memory is necessary since most of the time this gets done
super early in boot, but on warm reboots, and when SPI probing is done
long after the init stages it could actually pick up previously used memory,
and things like the chipselect polarity and other data end up being filled
with trash data if not explicitly set by the board files.

This solves a semi-random, almost unreproducable error whereby SPI devices
act very, very strangly on boot.

Signed-off-by: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:27 +02:00
Matt Sealey
784097ae5a spi: fix mxc_spi_slave structure allocation to clear memory
Use calloc() instead of malloc() to allocate the mxc_spi_slave structure.
Clearing the memory is necessary since most of the time this gets done
super early in boot, but on warm reboots, and when SPI probing is done
long after the init stages it could actually pick up previously used memory,
and things like the chipselect polarity and other data end up being filled
with trash data if not explicitly set by the board files.

This solves a semi-random, almost unreproducable error whereby SPI devices
act very, very strangly on boot. Tested on Efika MX over several years..

Signed-off-by: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:27 +02:00
Benoît Thébaudeau
cd2004037c mxc_spi: Round up clock divider
Since the input frequency of the API is a maximum that should not be exceeded in
order for the devices to operate properly, the SPI clock divider should be
rounded up, not truncated.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:25 +02:00
Otavio Salvador
fa7a51cb82 mxs: Convert sys_proto.h prefixes to 'mxs'
The sys_proto.h functions (except the boot modes) are compatible with
i.MX233 and i.MX28 so we use 'mxs' prefix for its methods.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:25 +02:00
Allen Martin
00a2749d7b tegra20: rename tegra2 -> tegra20
This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01 14:58:21 +02:00
Tom Rini
a4a99fffd8 am335x evm: Enable support for spi0
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:19 +02:00
Tom Rini
4c0620bf42 am33xx: Add support, update omap3 McSPI driver
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:18 +02:00
Otavio Salvador
9c471142bc mxs: prefix register structs with 'mxs' prefix
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:17 +02:00
Marek Vasut
7c5e6f7a5d MX28: SPI: Add DMA transfer support
The DMA transfers happen only if the transfered data are larger
than 512 bytes. Otherwise PIO is used. This is a small speed
optimization.

The DMA transfer doesn't work if unaligned transfer is requested
due to the limitation of the DMA controller. This has to be fixed
by introducing generic bounce buffer. Therefore the DMA feature
is now disabled by default.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2012-09-01 14:58:16 +02:00
Marek Vasut
ccd4d5a0d4 MX28: SPI: Pull out the PIO transfer function
Pull out all the PIO transfer logic into separate function,
so DMA can be added.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2012-09-01 14:58:16 +02:00
Marek Vasut
c7065fa824 MX28: SPI: Refactor spi_xfer a bit
This makes it easier to adapt for addition of DMA support.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2012-09-01 14:58:16 +02:00
Michal Simek
968766a7e8 spi: Fix merge conflicts - Makefile
The patch "spi: tegra2: rename tegra2_spi.* to tegra_spi.*"
(sha1: edffa63d3d)
renamed tegra2_spi.c to tegra_spi.c

and the patch "Merge branch 'master' of git://git.denx.de/u-boot-microblaze"
(sha1: d978780b2e)

has wrongly resolved confict.

This patch fix it.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2012-08-07 23:08:14 +02:00
Wolfgang Denk
d978780b2e Merge branch 'master' of git://git.denx.de/u-boot-microblaze
* 'master' of git://git.denx.de/u-boot-microblaze:
  microblaze: Wire up SPI driver
  spi: microblaze: Adds driver for Xilinx SPI controller
  microblaze: intc: Clear interrupt code
  microblaze: Call serial multi initialization
  microblaze: Move __udelay implementation
  microblaze: Remove extern from board.c
  microblaze: Wire up dts configuration
  fdt: Add board specific dts inclusion
  microblaze: Move individual board linker scripts to common script in cpu tree.
  microblaze: Add gpio.h
  microblaze: Add missing undefs for UBI and UBIFS
  microblaze: Expand and correct configuration comments
  microblaze: Enable ubi support
  microblaze: Avoid compile error on systems without cfi flash
  microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTION

Conflicts:
	drivers/spi/Makefile

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-31 22:01:08 +02:00
Stephan Linz
09aac75e4d spi: microblaze: Adds driver for Xilinx SPI controller
This is an improved version of the driver patch original
submitted by Graeme Smecher <graeme.smecher@mail.mcgill.ca>

The changes are:
    - remove hard coded Xilinx BSP defines (XPAR_SPI_*) and
      use CONFIG_SYS_SPI_BASE from config.h instead
    - add extensive register struct definitions
    - remove offset calculation for register access and
      use the new register struct instead
    - move default SPI controller configuration from
      spi_setup_slave() to spi_claim_bus()
    - add spi_set_speed()
    - insert SPI controller deactivation in spi_release_bus()
    - protect while loops in spi_xfer() with counter / timeouts
    - support SPI mode flags: LSB_FIRST, CPHA, CPOL, LOOP

Come from:
    http://patchwork.ozlabs.org/patch/71797/

Signed-off-by: Stephan Linz <linz@li-pro.net>
Tested-by: Michal Simek <monstr@monstr.eu>
2012-07-31 07:14:04 +02:00
Fabio Estevam
148ca64f32 spi: mxs: Allow other chip selects to work
MXS SSP controller may have up to three chip selects per port: SS0, SS1 and SS2.

Currently only SS0 is supported in the mxs_spi driver.

Allow all the three chip select to work by selecting the desired one
in bits 20 and 21 of the HW_SSP_CTRL0 register.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-05-15 08:31:35 +02:00
Fabio Estevam
79cb14ab39 spi: mxs: Introduce spi_cs_is_valid()
Introduce spi_cs_is_valid() for validating spi bus and chip select numbers.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-05-15 08:31:35 +02:00
Wolfgang Denk
bc6f6c87b6 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: (146 commits)
  arm: Use common .lds file where possible
  arm: add a common .lds link script
  arm: Remove unneeded setting of LDCSRIPT
  Define CPUDIR for the .lds link script
  arm: Remove zipitz2 link script
  Allow arch directory to contain .lds without requiring Makefile
  OMAP: Remove omap1610inn-based boards
  arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix build warnings
  board/ti/beagle/beagle.c: Fix build warnings
  sdrc.c: Fix typo in do_sdrc_init() for SPL
  tegra: i2c: Add I2C driver
  tegra: fdt: i2c: Add extra I2C bindings for U-Boot
  tegra: i2c: Select I2C ordering for Seaboard
  tegra: i2c: Enable I2C on Seaboard
  tegra: i2c: Select number of controllers for Tegra2 boards
  tegra: i2c: Initialise I2C on Nvidia boards
  tegra: Enhance clock support to handle 16-bit clock divisors
  fdt: Add function to allow aliases to refer to multiple nodes
  tegra: Rename NV_PA_PMC_BASE to TEGRA2_PMC_BASE
  tegra: fdt: Enable FDT support for Ventana
  tegra: fdt: Enable FDT support for Seaboard
  tegra: usb: Enable USB on Seaboard
  tegra: usb: Add common USB defines for tegra2 boards
  tegra: usb: Add USB support to nvidia boards
  arm: Check for valid FDT after console is up
  fdt: Avoid early panic() when there is no FDT present
  tegra: usb: Add support for Tegra USB peripheral
  tegra: fdt: Add function to return peripheral/clock ID
  usb: Add support for txfifo threshold
  tegra: usb: fdt: Add USB definitions for Tegra2 Seaboard
  tegra: usb: fdt: Add additional device tree definitions for USB ports
  tegra: fdt: Add clock bindings for Tegra2 Seaboard
  tegra: fdt: Add clock bindings
  tegra: fdt: Add additional USB binding
  fdt: Add tegra-usb bindings file from linux
  fdt: Add staging area for device tree binding documentation
  tegra: fdt: Add device tree file for Tegra2 Seaboard from kernel
  tegra: fdt: Add Tegra2x device tree file from kernel
  arm: fdt: Add skeleton device tree file from kernel
  fdt: Add basic support for decoding GPIO definitions
  fdt: Add functions to access phandles, arrays and bools
  fdt: Tidy up a few fdtdec problems
  fdt: Add tests for fdtdec
  fdt: Add fdtdec_find_aliases() to deal with alias nodes
  arm: Tegra2: Fix ELDK42 gcc failure with inline asm stack pointer load
  net: fec_mxc: allow use with cache enabled
  net: force PKTALIGN to ARCH_DMA_MINALIGN
  i.MX28: Enable caches by default
  i.MX28: Make use of the bounce buffer
  i.MX28: Do data transfers via DMA in MMC driver
  MMC: Implement generic bounce buffer
  i.MX28: Add cache support to MXS NAND driver
  i.MX28: Add cache support into the APBH DMA driver
  ARM926EJS: Implement cache operations
  board/vpac270/onenand.c: Fix build errors
  nhk8815: fix build errors
  atmel-boards: add missing atmel_mci.h
  ARM: highbank: setup env from boot source register
  ARM: highbank: change env config to use nvram
  ARM: highbank: add reset support
  ARM: highbank: Add boot counter support
  ARM: highbank: change TEXT_BASE to 0x8000
  ARM: highbank: fix us_to_tick calculation
  ARM: highbank: add missing get_tbclk
  ARM: highbank: fix warning for calxedaxgmac_initialize
  net: calxedaxgmac: fix build due to missing __aligned definition
  EXYNOS: Add structure for Exynos4 DMC
  EXYNOS: SMDK5250: Support all 4 UARTs
  ARM: fix s3c2410 timer code
  ARM: davinci: fixes for cam_enc_4xx board
  omap3_spi: receive transmit mode
  calimain, enbw_cmc: Fix typo in comments
  Davinci: ea20: use gpio framework to access gpios
  OMAP3: mt_ventoux: sets its own mtdparts
  OMAP3: mt_ventoux: updated timing for FPGA
  twl4030: fix potential power supply handling issues
  NAND: TI: fix warnings in omap_gpmc.c
  cam_enc_4xx: Rename 'images' to 'imgs'
  arm: Add Prep subcommand support to bootm
  OMAP3: twister: add support to boot Linux from SPL
  SPL: call cleanup_before_linux() before booting Linux
  OMAP3: SPL: do not call I2C init if no I2C is set.
  Add cache functions to SPL for armv7
  devkit8000: Implement and activate direct OS boot
  omap/spl: change output of spl_parse_image_header
  omap-common/spl: Add linux boot to SPL
  devkit8000/spl: init GPMC for dm9000 in SPL
  omap-common: Add NAND SPL linux booting
  devkit8000: add config for spl command
  Add cmd_spl command
  mx53ard: Initialize return code with error
  mx53: Make PLL2 to be the parent of UART clock
  configs: imx: Use CONFIG_SF_DEFAULT_CS
  mx28evk: Provide default values for SPI bus and chip select
  USB: ehci-mx6: Add proper IO accessors
  mx6: Read silicon revision from register
  i.MX28: Drop __naked function from spl_mem_init
  mxs_spi: Return proper timeout error
  i.MX28: Make the stabilization delays shorter
  pmic_i2c: Return error in case of invalid pmic_i2c_tx_num
  mx6: Remove duplicate definition of ANATOP_BASE_ADDR
  mx6: Fix reset cause for Power On Reset case
  i.MX6: mx6qsabrelite: add MACH_TYPE_MX6Q_SABRELITE
  i.MX6: mx6q_sabrelite: add CONFIG_REVISION_TAG
  i.MX28: Enable additional DRAM address bits
  mx6q: mx6qsabrelite: setup_spi() should be called in board_init to allow use for environment
  mx31: add "ARM11P power gating" to get_reset_cause
  mx31pdk: Fix CONFIG_SYS_MEMTEST_END
  efikamx: Fix CONFIG_SYS_MEMTEST_END
  mx53smd: Fix CONFIG_SYS_MEMTEST_END
  mx53evk: Fix CONFIG_SYS_MEMTEST_END
  mx51evk: Fix CONFIG_SYS_MEMTEST_END
  i.MX6: mx6qsabrelite: add ext2 support
  imximage: Remove overwriting of flash_offset
  IXP: Fix GPIO_INT_ACT_LOW_SET()
  IXP: Fix NAND build warning on PDNB3 and SCPU
  IXP: Move PDNB3 and SCPU from Makefile to boards.cfg
  IXP: Squash warnings in IXP NPE
  IXP: Fix missing MACH_TYPE_{ACTUX?,PNB3,DVLHOST}
  IXP: Make IXP buildable with arm-linux- toolchains
  Examples: Properly append LDFLAGS to LD command
  SPL: Enable YMODEM support on BeagleBone and AM335x EVM
  SPL: Add YMODEM over UART load support
  SPL: Add README.omap3
  README: document more SPL config options
  spl.c: Use __noreturn decorator
  config.mk: Check for -fstack-usage support
  config.mk: Make cc-option create a file under include/generated
  ...
2012-03-30 18:09:08 +02:00
jacopo mondi
08b5ab073d omap3_spi: receive transmit mode
Implementation of receive-transmit mode for
omap3 MCSPI.

Introduces full duplex communication, needed by
some spi devices (such as enc28j60).

Signed-off-by: jacopo mondi <mondi@cs.unibo.it> <j.mondi@voltaelectronics.com>
2012-03-27 22:05:29 +02:00
Fabio Estevam
d9fb6a4c7e mxs_spi: Return proper timeout error
Instead of returning -1, it is preferred to return -ETIMEDOUT in case of timeouts.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-03-27 09:41:16 +02:00
Yoshihiro Shimoda
c1d4ad9417 sh_spi: Add 4 chip select signals supporting
The module has 4 chip select signals. This patch supports it.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-03-26 10:09:31 +09:00
Eric Nelson
08c61a589b mxc_spi: move machine specifics into CPU headers
Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU

Introduce two new macros to control conditional setup
     MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x)
     MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Jason Liu <jason.hui@linaro.org>
2012-02-27 21:19:23 +01:00
Ian Campbell
3f8435516b kirkwood_spi: correct access to irq_mask register
Problem appears to have been present since day one but masked because alignment
aborts were not enabled. ca4b55800e "arm, arm926ejs: always do cpu critical
inits" turned on alignment aborts and uncovered this latent problem.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-By: Jason Cooper <u-boot@lakedaemon.net>
Tested-By: Holger Brunck <holger.brunck@keymile.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2012-02-12 10:11:27 +01:00
Matthias Fuchs
2638b50b18 mx28: fix i.MX28 spi driver
The generic spi flash driver (drivers/mtd/spi/spi_flash.c) uses the
spi low level driver's spi_xfer() function with len=0 to deassert the
SPI flash' chip select. But the i.MX28 spi driver rejects this call
due to len=0.

This patch implements an exception for len=0 with the SPI_XFER_END
flag set. This results in an extra read with the chip select being
deasserted afterwards. There seems to be no way to deassert the signal
by hand.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-02-12 10:11:27 +01:00
Valentin Longchamp
24934fea0c kw_spi: add weak functions board_spi_claim/release_bus
This allows a final, board specific, step in the claim/relase_bus
function for the SPI controller, which may be needed for some hardware
designs.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
2012-07-07 14:07:32 +02:00
Valentin Longchamp
ac486e3ba1 kw_spi: support spi_claim/release_bus functions
These two function nows ensure that the MPP is configured correctly for
the SPI controller before any SPI access, and restore the initial
configuration when the access is over.

Since the used pins for the SPI controller can differ (2 possibilities
for each signal), the used pins are configured with CONFIG_SYS_KW_SPI_MPP.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
2012-07-07 14:07:32 +02:00
Valentin Longchamp
ca880679dd kw_spi: backup and reset the MPP of the chosen CS pin
This was not done before, and in the case of a shared pin (for MPP0
between NF_IO[2] and CSn) this could lead to problems.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
2012-07-07 14:07:31 +02:00
Tom Warren
edffa63d3d spi: tegra2: rename tegra2_spi.* to tegra_spi.*
In anticipation of Tegra3 support, start removing/renaming
Tegra2-specific files. No functional changes (yet).
Also updated copyright to 2012.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:20 +02:00
Tom Warren
078078cfa9 spi: Tegra2: Seaboard: fix UART corruption during SPI transactions
Simon Glass's proposal to fix this on Seaboard was NAK'd, so I
removed his NS16550 references and added a small delay before
SPI/UART muxing. Tested on my Seaboard with large SPI reads/writes
and saw no corruption (crc's matched) and no spurious comm chars.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
2012-07-07 14:07:17 +02:00
Simon Glass
4560c7decc tegra2: spi: Support SPI / UART switch
Add the SPI / UART switch logic into the Tegra2 SPI driver so that it
can co-exist with the NS16550 UART.

We need the ns16550.h header for NS16550_t for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24 10:23:31 +01:00
Tom Warren
9112ef8d89 tegra2: spi: Add SPI driver for Tegra2 SOC
This driver supports SPI on Tegra2, running at 48MHz.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-12-24 10:23:30 +01:00
Anatolij Gustschin
eba46d69b3 drivers/spi/atmel_spi.c: Fix GCC 4.6 warning
Fix:
atmel_spi.c: In function 'spi_xfer':
atmel_spi.c:139:7: warning: variable 'ret' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-11-16 21:28:25 +01:00
Marek Vasut
ec33de3d12 iMX28: Add SPI driver
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
2011-11-11 11:36:57 +01:00
Wolfgang Denk
87a5d60103 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  ARM: Add Calxeda Highbank platform
  dkb: make mmc command as default enabled
  Marvell: dkb: add mmc support
  ARM: pantheon: add mmc definition
  davinci: remove config.mk file from the sources
  ARM:AM33XX: Add support for TI AM335X EVM
  ARM:AM33XX: Added timer support
  ARM:AM33XX: Add emif/ddr support
  ARM:AM33XX: Add clock definitions
  ARM:AM33XX: Added support for AM33xx
  omap3/emif4: fix registers definition
  davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM
  davinci: emac: add support for more than 1 PHYs
  davinci: emac: add new features to autonegotiate for EMAC
  da850evm: Move LPSC configuration to board_early_init_f()
  omap4_panda: Build in cmd_gpio support on panda
  omap: Don't use gpio_free to change direction to input
  mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset
  OMAP3: overo : Add environment variable optargs to bootargs
  OMAP3: overo: Move ethernet CS4 configuration to execute based on board id
  OMAP3: overo : Use ttyO2 instead of ttyS2.
  da830: add support for NAND boot mode
  dm36x: revert cache disable patch
  dm644X: revert cache disable patch
  devkit8000: Add malloc space
  omap: spl: fix build break due to changes in FAT
  OMAP3 SPL: Provide weak omap_rev_string
  omap: beagle: Use ubifs instead of jffs2 for nand boot
  omap: overo: Disable pull-ups on camera PCLK, HS and VS signals
  omap: overo: Configure mux for gpio10
  SPL: Add DMA library
  omap3: Add interface for omap3 DMA
  omap3: Add DMA register accessors
  omap3: Add Base register for DMA
  arm, davinci: add missing LSPC define for MMC/SD1
  U-Boot/SPL: omap4: Make ddr pre-calculated timings as default.
  DaVinci: correct MDSTAT.STATE mask
  omap4: splitting padconfs into common, 4430 and 4460
  omap4: adding revision detection for 4460 ES1.1
  omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL
  gplug: fixed build error as a result of code cleanup patch
  kirkwood_spi: add dummy spi_init()
  gpio: mvmfp: reduce include platform file
  ARM: orion5x: reduce dependence of including platform file
  serial: reduce include platform file for marvell chip
  ARM: kirkwood: reduce dependence of including platform file
  ARM: armada100: reduce dependence of including platform file
  ARM: pantheon: reduce dependence of including platform file
  Armada100: Add env storage support for Marvell gplugD
  Armada100: Add SPI flash support for Marvell gplugD
  Armada100: Add SPI support for Marvell gplugD
  SPI: Add SPI driver support for Marvell Armada100
  dreamplug: initial board support.
  imx: fix coding style
  misc: pmic: drop old Freescale's pmic driver
  MX31: mx31pdk: use new pmic driver
  MX31: mx31ads: use new pmic driver
  MX31: mx31_litekit: use new pmic driver
  MX5: mx53evk: use new pmic driver
  MX5: mx51evk: use new pmic driver
  MX35: mx35pdk: use new pmic driver
  misc: pmic: addI2C  support to pmic_fsl driver
  misc: pmic: use I2C_SET_BUS in pmic I2C
  MX5: efikamx/efikasb: use new pmic driver
  MX3: qong: use new pmic driver
  RTC: Switch mc13783 to generic pmic code
  MX5: vision2: use new pmic driver
  misc: pmic: Freescale PMIC switches to generic PMIC driver
  misc:pmic:samsung Enable PMIC driver at GONI target
  misc:pmic:max8998 MAX8998 support at a new PMIC driver.
  misc:pmic:core New generic PMIC driver
  mx31pdk: Remove unneeded config
  mx31: provide readable WEIM CS accessor
  MX51: vision2: Set global macros
  I2C: Add i2c_get/set_speed() to mxc_i2c.c
  ARM: Update mach-types
  devkit8000: Add config to enable SPL MMC boot
  devkit8000: protect board_mmc_init
  arm, post: add missing post_time_ms for arm
  cosmetic, post: Codingstyle cleanup
  arm, logbuffer: make it compileclean
  tegra2: Enable MMC for Seaboard
  tegra2: Add more pinmux functions
  tegra2: Rename PIN_ to PINGRP_
  tegra2: Add more clock functions
  tegra2: Clean up board code a little
  tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
2011-10-28 00:15:19 +02:00
Marek Vasut
2e8f6419aa GCC4.6: Squash warnings in kirkwood_spi.c
kirkwood_spi.c:125:2: warning: format '%08X' expects type 'unsigned int', but
argument 4 has type 'const void *'
kirkwood_spi.c:125:2: warning: format '%08X' expects type 'unsigned int', but
argument 5 has type 'void *'
kirkwood_spi.c:160:5: warning: format '%08x' expects type 'unsigned int', but
argument 2 has type 'void *'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-27 23:54:07 +02:00
Marek Vasut
5cc08a179f GCC4.6: Squash warnings in fsl_espi.c
fsl_espi.c: In function 'spi_setup_slave':
fsl_espi.c💯 warning: format '%d' expects type 'int', but argument 3 has type
'long unsigned int'
fsl_espi.c: In function 'spi_xfer':
fsl_espi.c:237: warning: format '%08x' expects type 'unsigned int', but argument
5 has type 'const void *'
fsl_espi.c:237: warning: format '%08x' expects type 'unsigned int', but argument
7 has type 'void *'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-27 23:54:05 +02:00
Michael Walle
efa4e43a40 kirkwood_spi: add dummy spi_init()
The spi_init() function is missing. Add it.

Signed-off-by: Michael Walle <michael@walle.cc>
2011-10-27 21:56:33 +02:00
Lei Wen
a7efd719f4 ARM: kirkwood: reduce dependence of including platform file
For files like the drivers/serial/serial.c, it must include the
platform file, as the CONFIG_SYS_NS16550_COM1 must reference to the
definition in the platform definition files.

Include the platform definition file in the config file, so that it
would decouple the dependence for the driver files.

Signed-off-by: Lei Wen <leiwen@marvell.com>
2011-10-27 21:56:33 +02:00
Ajay Bhargav
51100cfcca SPI: Add SPI driver support for Marvell Armada100
This patch provides support for SPI emulated over SSP for Marvell
Armada100 SOC.

Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
2011-10-27 21:56:32 +02:00
Mike Frysinger
e2f014503e Blackfin: bfin_spi: fix build error when DEBUG is defined
The new debug() changes pointed out debug code that rotted a little.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-16 14:22:19 -04:00
Stefano Babic
d8e0ca851b IMX: uniform GPIO interface using GPIO framework
IMX processors has a slightly different interface
to access GPIOs and do not make use of the provided GPIO
framework. The patch substitutes mxc_ specific
functions and make use of the API in asm/gpio.h

Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-09-04 11:36:11 +02:00
Reinhard Meyer
0c42791476 AT91/SPI: fix atmel_dataflash_spi.c to allow building without warnings
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-08-03 13:00:56 +02:00
Macpaul Lin
fafc245401 andes_spi: add andes_spi interface
andes_spi is an spi interface developed by Andes Tech.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-07-25 23:40:11 +02:00
Stefano Babic
9f008bb47d MX31: Cleanup clock function
The patch provide the same API used with other i.MX
processors and get rid of mx31_ functions.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-07-18 14:41:48 +02:00
Reinhard Meyer
576e7a10c4 ATMEL spi_dataflash driver - fix to build again
The rework effort for ATMEL (AT91/AVR32) accidentially broke build of
this driver. Fix this to make it build again. However this driver should
be reworked as soon as possible!

Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-06-21 22:26:22 +02:00
Helmut Raiger
61a58a16f8 mxc_spi.c: typo fixed
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
2011-06-21 22:26:21 +02:00
Reinhard Meyer
a0cfd18876 ATMEL: fix dataflash (dirty) this file should be converted to struct SoC access
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18 07:56:51 +02:00
Reinhard Meyer
329f0f52fa ATMEL: fix related common atmel driver files
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18 07:56:51 +02:00
Wolfgang Denk
aeabdeb7a3 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2011-04-30 22:45:55 +02:00
Thomas Chou
dea6386b71 spi: add new driver for OpenCores tiny_spi
This patch adds support for OpenCores tiny_spi.

http://opencores.org/project,tiny_spi

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2011-04-30 20:58:36 +02:00
Mingkai Hu
273feafefd powerpc: eSPI and eSPI controller support
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Singed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-29 07:34:09 -05:00
Wolfgang Denk
f38536f913 Merge branch 'master' of git://git.denx.de/u-boot-arm 2011-04-27 21:48:09 +02:00
Stefano Babic
8627111543 IMX: MX31: Cleanup include files and drop nasty #ifdef in drivers
As exception among the i.MX processors, the i.MX31 has headers
without general names (mx31-regs.h, mx31.h instead of imx-regs.h and
clock.h). This requires several nasty #ifdef in the drivers to
include the correct header. The patch cleans up the driver and
renames the header files as for the other i.MX processors.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-04-27 19:38:05 +02:00
Thomas Chou
6c3eb43a0f bfin_spi: add spi_set_speed
The new speed will be applied by spi_claim_bus.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-25 01:45:42 -04:00