Commit graph

659 commits

Author SHA1 Message Date
Shengzhou Liu
c35f869394 net/fm: add 2.5G SGMII support
As auto-negotiation is not supported for 2.5G SGMII, we need
to add a new type PHY_INTERFACE_MODE_SGMII_2500 to differentiate
SGMII-1G and SGMII-2.5G with different setting for auto-negotiation.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-19 18:17:12 -08:00
Shaohui Xie
ae6b458306 driver/net/fm/memac_phy: set NEG bit for external MDIOs
NEG bit default is '1' for external MDIOs as per FMAN-v3 RM, but on some
platforms, e.g. T2080QDS, this bit is '0', which leads to MDIO failure
on XAUI PHY, so set this bit definitely to align with the RM.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-14 11:12:13 -08:00
Shaohui Xie
ff5fb2a36d Fman/mEMAC: mEMAC fix for 10G MAC and PHY
1. use Payload length check disable when enable MAC;
2. add XGMII support for setting MAC interface mode;
3. only enable auto negotiation for Non-XGMII mode;
4. return 0xffff if clause 22 is used to read 10G phy_id;

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-By: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-14 11:12:13 -08:00
Dirk Eibach
b97cd6814e ppc4xx: Handle i2c stuck on combined xfer
ppc4xx i2c master gets stuck on errors while repeated start is
active. Can be easily reproduced by "i2c md" on an unpopulated
i2c address. There is not stop condition given, scl remains
pulled low.
The only way out seems to be doing a stop manually and then a
soft reset.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-11-10 06:44:30 +01:00
Marek Vasut
5038d7f189 ppc: Zap Hymod board
Remove this board as this is the only one last user of eeprom_probe(),
which is pretty non-standard stuff.

This patch also removes all the PHP, SQL and CSS stuff from U-Boot,
which probably makes U-Boot a bit less IoT ;-)

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
2014-10-27 14:35:55 +01:00
Anatolij Gustschin
c6832a9635 powerpc: mpc512x: fix boot breakage
Commit d6b11fd1 (powerpc: remove MBX and MBX860T boards support)
removed mbxbar field in "struct sysconf512x" by mistake and broke
booting on mpc5121 boards. Fix it.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2014-10-27 14:35:53 +01:00
Ruchika Gupta
7cad2e38d6 powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot
By default, PAMU's (IOMMU) are enabled in case of secure boot.
Disable/bypass them once the control reaches the bootloader.

For non-secure boot, PAMU's are already bypassed in the default
SoC configuration.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-10-16 14:17:42 -07:00
Ruchika Gupta
b9eebfade9 fsl_sec: Add hardware accelerated SHA256 and SHA1
SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's
The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam.
The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to
enable initialization of this hardware IP.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-10-16 14:17:07 -07:00
Ruchika Gupta
028dbb8db1 fsl_sec : Change accessor function to take care of endianness
SEC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of SEC IP.

So update acessor functions with common SEC acessor functions to take care
both type of endianness.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-10-16 14:16:50 -07:00
Ruchika Gupta
48ef0d2a10 fsl_sec : Move SEC CCSR definition to common include
Freescale SEC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the CCSR defintion of
SEC to common include

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-10-16 14:16:25 -07:00
Masahiro Yamada
9ed3246e19 powerpc: ppc4xx: remove board support for bluestone
This board has been orphaned for more than 6 months.

It is the last board defining CONFIG_APM821XX.
The code inside #ifdef CONFIG_APM821XX should be removed too.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-10-10 09:44:43 -04:00
Claudiu Manoil
93f26f130e net: Merge asm/fsl_enet.h into fsl_mdio.h
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.

To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
2014-09-08 10:30:33 -07:00
Boschung, Rainer
60b295672d powerpc: macros for e500mc timer regs added
For e500mc cores the watchdog timer period has to be set by means of a
6bit value, that defines the bit of the timebase counter used to signal
a watchdog timer exception on its 0 to 1 transition.
The macro used to set the watchdog period TCR_WP, was redefined for e500mc
to support 6 WP setting.

The parameter (x) given to the macro specifies the prescaling factor of
the time base clock (fTB):

watchdog_period = 1/fTB * 2^x

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01 14:18:07 -07:00
Tang Yuantian
7cb7272365 mpc85xx/t104x: Enable L2 and CPC cache when resume
When resume from deep sleep, uboot needs to enable L2 and CPC
cache, or they would be keeping unusable in kernel because
kernel didn't enble or initialized them.
This patch didn't change the existing L2 cache enabling code,
just put them in a function.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
Shaohui Xie
e55782eccc powerpc/t4240qds: fix offset of serdes when checking reference clock
T4240 has 4 serdes, each serdes has 4k memory space, two PLLs.
We use PLL1CR0 to check the serdes reference clock.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
York Sun
8340e7ac86 driver/ddr: Fix DDR4 driver for ARM
Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Sandeep Singh
d43a386a91 powerpc/mpc85xx: Removed support for G4060
G4060 has no PA cores, hence removing its support.

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Zhao Qiang
38d67a4e55 qe: move immap_qe.h from arch directory into common directory
ls1021 is arm-core and supports qe too.
Move immap_qe.h into common directory for both arm and powerpc.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Sandeep Singh
377ffcfabf powerpc/mpc85xx: Add workaround to enable TDM on T1040
This is a workaround for 32 bit hardware limitation of TDM.
T1040 has 36 bit physical addressing, TDM DMAC register
are 32 bit wide but need to store address of CCSR space
which lies beyond 32 bit address range. This workaround
creats a LAW to enable access of TDM DMA to CCSR by
mapping CCSR to overlap with DDR.
A hole of 16M is created in memory using device tree. This
workaround law is set only if "tdm" is defined in hwconfig.
Also disable POST tests and add LIODN for TDM

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 13:45:07 -07:00
Shaveta Leekha
b6808cd82d powerpc/serdes: Add the workaround for erratum A-007186
SerDes PLL is calibrated at reset. When the junction temperature
delta from the time the PLL is calibrated exceeds +56C/-66C,
jitter may increase and can cause PLL to unlock.

This workaround overwrite the SerDes registers with new values,
to calibrate SerDes registers.
These values are known to work fine for all temperature ranges.

This workaround is valid for B4, T4 and T2 platforms, so
added in their config.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
[York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 13:45:07 -07:00
York Sun
9855b3beca powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-06-05 13:45:07 -07:00
Masahiro Yamada
3fe1a8545b powerpc: hiddendragon: remove orphan board
This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)

Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denx <wd@denx.de>
2014-05-30 14:03:24 -04:00
ramneek mehresh
80ba6a6f2a mpc85xx/p1020:Define number of USB controllers used on P1020RDB-PD platform
P1020 SoC which has two USB controllers, but only first one is used
on this platform.

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:27 -05:00
Shaveta Leekha
9c3fdd883a powerpc/mpc85xx: Added B4460 support
B4460 differs from B4860 only in number of CPU cores,
hence used existing support for B4860.
B4460 has 2 PPC cores whereas B4860 has 4 PPC cores.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:26 -05:00
Chunhe Lan
f1a96ec1a9 fsl/pci: Add workaround for erratum A-005434
By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are
mapped to 0xF, which is local memory. But for BSC9132, 0xF
is CCSR, 0x0 is local memory.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:26 -05:00
Shengzhou Liu
5122dfae5d powerpc/85xx: add T4080 SoC support
The T4080 SoC is a low-power version of the T4160.
T4080 combines 4 dual-threaded Power Architecture e6500
cores with single cluster and two memory complexes.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-05-13 08:26:54 -07:00
Shengzhou Liu
c665c473b6 powerpc/t208x: enable errata A006261, A006593, A006379
Enable errata A006261, A006593, A006379 for T208x.
Additionally enable CONFIG_CMD_ERRATA for T2080RDB.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-05-13 08:26:54 -07:00
Aneesh Bansal
e47c2a6851 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDB
Secure Boot Target is added for T2080RDB

Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
2014-05-13 08:26:54 -07:00
Aneesh Bansal
4067815998 powerpc/mpc85xx: SECURE BOOT- secure boot target for t1040rdb
T1040RDB.h file is removed and a unified file T104xRDB.h is created.
Hence macro CONFIG_T1040 is renamed to CONFIG_T104x.

Signed-off-by: Gaurav Kumar Rana <gaurav.rana@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
2014-05-13 08:24:32 -07:00
Masahiro Yamada
8e2615752e bd_info: remove bi_barudrate member from struct bd_info
gd->bd->bi_baudrate is a copy of gd->baudrate.

Since baudrate is a common feature for all architectures,
keep gd->baudrate only.

It is true that bi_baudrate was passed to the kernel in that structure
but it was a long time ago.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Michal Simek <monstr@monstr.eu> (For microblaze)
2014-05-12 15:19:45 -04:00
vijay rai
0c12a1592c powerpc/85xx: Enhance get_sys_info() to check clocking mode
T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode.

In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock
(100MHz) to the following PLLs:
• Platform PLL
• Core PLLs
• USB PLL
• DDR PLL, etc

The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or
DIFF_SYSCLK (differential) is selected as the clock input to the chip.

get_sys_info has been enhanced to add the diff_sysclk so that the
various drivers can be made aware of ths diff sysclk configuration and
act accordingly.

Other changes:
-single_src to ddr_refclk_sel, as it is use for checking ddr reference clock
-Removed the print of single_src from get_sys_info as this will be
-printed whenever somebody calls get_sys_info which is not appropriate.
-Add print of single_src in checkcpu as it is called only once during initialization

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:52 -07:00
Tang Yuantian
5aef4c86f3 mpc85xx: Add support for the supplement configuration unit register
The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers in addition to those
available in the device configuration unit.
The base address for this unit is 0x0F_C000.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
York Sun
c3678b0937 powerpc/mpc85xx: Add workaround for erratum A007212
Erratum A007212 for DDR is about a runaway condition for DDR PLL
oscilliator. Please refer to erratum document for detail.
For this workaround to work, DDR PLL needs to be disabled in RCW.
However, u-boot needs to know the expected PLL ratio. We put the
ratio in a reserved field RCW[18:23]. U-boot will skip this workaround
if DDR PLL ratio is set, or the reserved field is not set.

Workaround for erratum A007212 applies to selected versions of
B4/T4 SoCs. It is safe to apply the workaround to all versions. It
is helpful for upgrading SoC without changing u-boot. In case DDR
PLL is disabled by RCW (part of the erratum workaround), we need this
u-boot workround to bring up DDR clock.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Nikhil Badola
11856919f2 fsl/usb: Workaround for USB erratum-A007075
Put a delay of 5 millisecond after reset so that ULPI phy
gets enough time to come out of reset. Erratum A007075 applies
to following SOCs and their variants, if any
        P1010 rev 1.0
        B4860 rev 1.0, 2.0
        P4080 rev 2.0, 3.0

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
York Sun
34e026f9b1 driver/ddr/fsl: Add DDR4 support to Freescale DDR driver
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Zhao Qiang
2a44efeb21 QE/U-QE: Add U-QE support
Modify code to adapt to both u-qe and qe.

U_QE is a kind of cutted QE.
the differences between U_QE and QE
	1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs.
	2. IMMR: have different immr base addr.
	3. iopin: U_QE doesn't need to config iopin.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Aneesh Bansal
2d8db6d315 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB
Secure Boot Target is added for T1040QDS and T1040RDB
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and
CONFIG_T1040RDB

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Aneesh Bansal
ca4819df83 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS
Secure Boot Target is added for T2080QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00
Aneesh Bansal
796a781001 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS
Secure Boot Target is added for T4240QDS and T4160QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00
Aneesh Bansal
fb4a2409b4 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
   So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
   code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
   keeping area. This configuration is to be disabled once in uboot.
   Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
   As a result cache invalidation function was getting skipped in
   case CPC is configured as SRAM.This was causing random crashes.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00
Aneesh Bansal
f978f7c203 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS
Add NOR, SPI and SD secure boot targets for BSC9132QDS.

Changes:
- Debug TLB entry is not required for Secure Boot Target.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00
Alexander Graf
fa08d39517 PPC 85xx: Add qemu-ppce500 machine
For KVM we have a special PV machine type called "ppce500". This machine
is inspired by the MPC8544DS board, but implements a lot less features
than that one.

It also provides more PCI slots and is supposed to be enumerated by
device tree only.

This patch adds support for the generic ppce500 machine and tries to
rely solely on device tree for device enumeration.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:45 -07:00
Alexander Graf
f29f804a93 PPC: 85xx: Generalize DDR TLB mapping function
The DDR mapping function really is just a generic virtual -> physical
mapping function. Generalize it so it can support any virtual starting
offset and IO maps just the same.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:45 -07:00
Masahiro Yamada
d6b11fd1f0 powerpc: remove MBX and MBX860T boards support
Enough time has passed since these boards were moved to Orphan. Remove.

 - Remove board/mbx8xx/*
 - Remove include/configs/{MBX.h,MBX860T.h}
 - Clean-up if defined(CONFIG_MBX)
 - Move the entries from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-04-18 10:42:29 -04:00
Masahiro Yamada
a146e8b189 powerpc: remove NX823 board support
Enough time has passed since this board was moved to Orphan. Remove.

 - Remove board/nx823/*
 - Remove include/configs/NX823.h
 - Clean-up ifdef(CONFIG_NX823)
 - Move the entry from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-04-18 10:42:29 -04:00
Haijun.Zhang
1336e2d343 mmc:eSDHC: Workaround for data timeout issue on Txxx SoC
1. The Data timeout counter value in eSDHC_SYSCTL register is
not working as it should be, so add quirks to enable this
workaround to fix it to the max value 0xE.

2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround.

* Update of patch for change mmc interface by
	Pantelis Antoniou <panto@antoniou-consulting.com>

Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-04-02 13:25:01 +03:00
Tom Rini
247161b816 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-03-07 20:54:22 -05:00
Priyanka Jain
bf4699db85 powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040
T1040 SoC has SCFG (Supplement Configuration) Block which provides
chip specific configuration and status support. The base address of
SCFG block in T1040 is 0xfc000.
SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register)
at offset 0x28.

Add definition of
-SCFG block
-SCFG_PIXCLKCR register
-Bits definition of SCFG_PIXCLK register

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:53:29 -08:00
Suresh Gupta
9c641a872a powerpc/usb: Workaround for erratum-A006261
USB spec says that the minimum disconnect threshold should be
	over 525 mV. However, internal USB PHY threshold value is below
	this specified value. Due to this some devices disconnect at
	run-time. Hence, phy settings are tweaked to increased disconnect
	threshold to be above 525mV by using this workaround.

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:52:16 -08:00
Shaveta Leekha
7af9a07403 powerpc/b4860: Add workaround for errata A006384 and A006475
SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384)
and at cold temperatures(A006475), workaround recalibrate the
PLLs with some SerDes configuration

Both these errata are only applicable for b4 rev1.
So, make workaround for these errata conditional,
depending upon soc version.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:52:01 -08:00
Shaveta Leekha
6df82e3c0f B4860/B4420: Add PLL_NUM define for B4420/B4860 to use SerDes2 Refclks re-configuration
B4860 has two PLL per SerDes whereas B4420 has one PLL per SerDes,
add their defines in arch/powerpc/include/asm/config_mpc85xx.h

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:50:10 -08:00
Shaveta Leekha
fb07c0a16d board/b4860qds: Add support to make PCIe SATA work on B4860QDS
1) SerDes2 Refclks have been set properly to make
     PCIe SATA to work as it work on SerDes refclk of 100MHz
  2) Mask the SerDes's device reset request before changing
     the Refclks for SerDes1 and SerDes2 for PLL locks to
     happen properly, device reset request bit unmasked
     after SerDes refclks configuration

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:49:45 -08:00
Masahiro Yamada
58dac32764 powerpc: mpc8260: consolidate CONFIG_MPC8260 and CONFIG_8260
Before this commit, CONFIG_MPC8260 and CONFIG_8260
were used mixed-up.

All boards with mpc8260 cpu defined both of them:
  - CONFIG_MPC8260 was defined in board config headers
      and include/common.h
  - CONFIG_8260 was defined arch/powerpc/cpu/mpc8260/config.mk

We do not need to have both of them.
This commit keeps only CONFIG_MPC8260.

This commit does:
 - Delete CONFIG_8260 and CONFIG_MPC8260 definition
   in config headers and include/common.h
 - Rename CONFIG_8260 to CONFIG_MPC8260
    in arch/powerpc/cpu/mpc8260/config.mk.
 - Rename #ifdef CONFIG_8260 to #ifdef CONFIG_MPC8260

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2014-03-07 10:59:06 -05:00
Prabhakar Kushwaha
1b4175d6fa driver/ifc:Change accessor function to take care of endianness
IFC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of IFC IP.

So update acessor functions with common IFC acessor functions to take care
both type of endianness.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:51 -08:00
Nikhil Badola
a4f7cba64e powerpc/usb: Enable dual phy for T1040
Define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE macro for enabling dual
phy in t1040

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:49 -08:00
Prabhakar Kushwaha
5b7672fc49 boards/t1040qds: Adds ethernet support for T1040
Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5
    Define MDIO related configs
    Added eth.c file
    Update t1040.c to support RGMII and SGMII
    Update t1040qds.c to support ethernet
    Define the PHY address

Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: remove dash from commit message]
Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:48 -08:00
Prabhakar Kushwaha
96bda02c9e powerpc/mpc85xx: Update serdes protocols for T1040
T1040 has only one SerDes block. so update the code accordingly.

Also, add support of SerDes Protocol 0x00, 0x06, 0x40, 0x69 0x85,
0xA7 and 0xAA

Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:48 -08:00
Masahiro Yamada
36aa822880 powerpc: delete unused header files
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:07 -05:00
Haijun.Zhang
f28bea0003 eSDHC: Calculate envaddr accroding to the address format
On BSC9131, BSC9132, P1010 : For High Capacity SD Cards (> 2 GBytes), the
32-bit source address specifies the memory address in block address
format. Block length is fixed to 512 bytes as per the SD High Capacity
specification. So we need to convert the block address format
to byte address format to calculate the envaddr.

If there is no enough space for environment variables or envaddr
is larger than 4GiB, we relocate the envaddr to 0x400. The address
relocated is in the front of the first partition that is assigned
for sdboot only.

Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-22 08:56:44 -08:00
Shengzhou Liu
842eaa1361 powerpc/85xx: update erratum a006379
Enable Erratum A006379 for T2080, T2081, T4160, B4420.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 13:39:19 -08:00
Shengzhou Liu
2ffa96d815 powerpc/t208x: fix macro CONFIG_SYS_FSL_NUM_USB_CTRLS
CONFIG_SYS_FSL_NUM_USB_CTRLS is no longer used,
update it to new CONFIG_USB_MAX_CONTROLLER_COUNT.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-01-02 14:10:13 -08:00
Priyanka Jain
b135991a3c powerpc/mpc85xx: Add support for single source clocking
Single-source clocking is new feature introduced in T1040.
In this mode, a single differential clock is supplied to the
DIFF_SYSCLK_P/N inputs to the processor, which in turn is
used to supply clocks to the sysclock, ddrclock and usbclock.

So, both ddrclock and syclock are driven by same differential
sysclock in single-source clocking mode whereas in normal clocking
mode, generally separate DDRCLK and SYSCLK pins provides
reference clock for sysclock and ddrclock

DDR_REFCLK_SEL rcw bit is used to determine DDR clock source
-If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in
 normal clocking mode by DDR_Reference clock

-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
 single source clocking mode by DIFF_SYSCLK

Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
2014-01-02 14:10:13 -08:00
Prabhakar Kushwaha
e03c76c303 powerpc/mpc85xx: Update CONFIG_SYS_FSL_TBCLK_DIV for T1040
The default value of CONFIG_SYS_FSL_TBCLK_DIV is 16.

So, update its value as default.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-11 11:12:54 -08:00
Shengzhou Liu
629d6b32d6 powerpc/mpc85xx: Add T2080/T2081 SoC support
Add support for Freescale T2080/T2081 SoC.

T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- High-speed peripheral interfaces
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
  - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
  - Two serial ATA (SATA 2.0) controllers
  - Two high-speed USB 2.0 controllers with integrated PHY
  - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
  - Enhanced serial peripheral interface (eSPI)
  - Four I2C controllers
  - Four 2-pin UARTs or two 4-pin UARTs
  - Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Differences between T2080 and T2081:
  Feature               T2080 T2081
  1G Ethernet numbers:  8     6
  10G Ethernet numbers: 4     2
  SerDes lanes:         16    8
  Serial RapidIO,RMan:  2     no
  SATA Controller:      2     no
  Aurora:               yes   no
  SoC Package:          896-pins 780-pins

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-11-25 11:44:25 -08:00
Shengzhou Liu
82a55c1ef8 net/fman: Add support for 10GEC3 and 10GEC4
There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080).
This patch adds support for 10GEC3 and 10GEC4.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-11-25 11:43:47 -08:00
York Sun
0b66513b27 Driver/IFC: Move Freescale IFC driver to a common driver
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:47 -08:00
York Sun
9a17eb5b7e Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx
Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:46 -08:00
York Sun
5614e71b49 Driver/DDR: Moving Freescale DDR driver to a common driver
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:43 -08:00
Tang Yuantian
f40fcfd911 mpc85xx: Fix the offset of register address error
The offset of register address within GPIO module is just
CONFIG_SYS_MPC85xx_GPIO_ADDR. So, fix it. The following platforms
are confirmed: MPC8572, P1023, P1020, P1022, P2020, P4080,
P5020, P5040, T4240, B4860.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
2013-11-25 11:40:05 -08:00
Laurentiu TUDOR
8f9fe660fc powerpc/t4240: fix per pci endpoint liodn offsets
Update the code that builds the pci endpoint liodn
offset list so that it doesn't overlap with other
liodns and doesn't generate negative offsets like:

  fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf
                             0xffffffd1 0xffffffd3
                             0xffffffd5 0xffffffd7
                             0xffffffd9 0xffffffdb>;

The update consists in adding a parameter to the
function that builds the list to specify the base
liodn.
On PCI v2.4 use the old base = 256 and, on PCI 3.0
where some of the PCIE liodns are larger than 256,
use a base = 1024. The version check is based on
the PCI controller's version register.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: York Sun <yorksun@freescale.com>
2013-11-13 12:41:28 -08:00
ramneek mehresh
4e2e0df94d powerpc/83xx: Define USB1 and USB2 base addr for MPC834x
Define base addresse for both MPH(USB1) and DR(USB2) controllers
for MPC834x socs

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2013-11-13 12:41:28 -08:00
Priyanka Jain
2967af6816 powerpc/t1040: Update defines to support T1040SoC personalities
T1040 Soc has four personalities:
-T1040 (4 cores with L2 switch)
-T1042:Reduced personality of T1040 without L2 switch
-T1020:Reduced personality of T1040 with less cores(2 cores)
-T1022:Reduced personality of T1040 with 2 cores and without L2 switch

Update defines in arch/powerpc header files, Makefiles and in
driver/net/fm/Makefile to support all T1040 personalities

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: fixed Makefiles]
Acked-by: York Sun <yorksun@freescale.com>
2013-11-13 12:41:08 -08:00
Masahiro Yamada
643aae1406 include: delete include/linux/config.h
Linux Kernel abolished include/linux/config.h long time ago.
(around version v2.6.18..v2.6.19)

We don't need to provide Linux copatibility any more.

This commit deletes include/linux/config.h
and fixes source files not to include this.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-08 15:25:13 -05:00
Masahiro Yamada
0f0f75774e cosmetic: remove empty lines at the top of file
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-08 09:41:37 -05:00
Valentin Longchamp
935b402eae fsl/mpc85xx: define common serdes_clock_to_string function
This allows to share some common code for the boards that use a corenet
base SoC.

Two different versions of the function are available in
fsl_corenet_serdes.c and fsl_corenet2_serdes.c files.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix t1040qds.c]
Acked-by: York Sun <yorksun@freescale.com>
2013-10-24 09:36:18 -07:00
Valentin Longchamp
7e157b0ade mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it
If the DDR3 module supports industrial temperature range and requires
the x2 refresh rate for that temp range, the refresh period must be
3.9us instead of 7.8 us.

This was successfuly tested on kmp204x board with some MT41K128M16 DDR3
RAM chips (no module used, chips directly soldered on board with an SPD
EEPROM).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix minor conflicts in fsl_ddr_dimm_params.h,
	   lc_common_dimm_params.c, common_timing_params.h]
Acked-by: York Sun <yorksun@freescale.com>
2013-10-24 09:35:52 -07:00
ramneek mehresh
77354e9d50 powerpc/usb:Differentiate USB controller base address
Introduce different macros for storing addresses of multiple
USB controllers. This is required for successful initialization
and usage of multiple USB controllers inside u-boot

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2013-10-24 09:35:09 -07:00
ramneek mehresh
f1810d851c powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socs
CONFIG_USB_MAX_CONTROLLER_COUNT macro recently defined for
initializing all USB controllers on a given platform. This
macro is defined for all 85xx socs

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2013-10-24 09:35:03 -07:00
Zhao Qiang
287df01e6a PCIe:change the method to get the address of a requested capability in configuration space.
Previously, the address of a requested capability is define like that
	"#define PCI_DCR	0x78"
But, the addresses of capabilities is different with regard to PCIe revs.
So this method is not flexible.

Now a function to get the address of a requested capability is added and used.
It can get the address dynamically by capability ID.
The step of this function:
	1. Read Status register in PCIe configuration space to confirm that
	   Capabilities List is valid.
	2. Find the address of Capabilities Pointer Register.
	3. Find the address of requested capability from the first capability.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-16 16:15:17 -07:00
York Sun
133fbfa9e6 powerpc/mpc85xx: Add workaround for erratum A006379
Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default
value after POR. The workaround is to set this field before enabling
CPC to 0x1e.

Erratum A006379 applies to
	T4240 rev 1.0
	B4860 rev 1.0, 2.0

Signed-off-by: York Sun <yorksun@freescale.com>
2013-10-16 16:15:17 -07:00
Priyanka Jain
0dd38a35f4 powerpc: Fix CamelCase warnings in DDR related code
Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
has various parameters with embedded acronyms capitalized that trigger the CamelCase
warning in checkpatch.pl

Convert those variable names to smallcase naming convention and modify all files
which are using these structures with modified structures.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
2013-10-16 16:15:16 -07:00
Prabhakar Kushwaha
ce746fe03e powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator
CHASSIS2 architecture never fix clock groups for Cluster and hardware
  accelerator like PME, FMA. These are SoC defined. SoC defines :-
    - NUM of PLLs present in the system
    - Clusters and their Clock group
    - hardware accelerator and their clock group
      if no clock group, then platform clock divider for FMAN, PME

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16 16:13:11 -07:00
Prabhakar Kushwaha
1d384eca61 powerpc/mpc85xx:Update processor defines for T1040
T1040 SoC has
    - DDR controller ver 5.0
    - 2 PLLs
    - 8 IFC Chip select
    - FMAN Muram 192K
    - No Srio
    - Sec controller ver 5.0
    - Max CPU update for its personalities

So, update the defines accordingly.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16 16:13:11 -07:00
Po Liu
0d2cff2d9e powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.h
This patch is for board config file not to add CONFIG_SECURE_BOOT
condition for include the asm/fsl_secure_boot.h.

Signed-off-by: Po Liu <Po.Liu@freescale.com>
2013-10-16 16:13:10 -07:00
Wolfgang Denk
3765b3e7bd Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:53 -04:00
Wolfgang Denk
1b387ef55c SPDX: fix IBM-pibs license identifier
The SPDX License List version 1.19 now contains an official entry for
the IBM-pibs license.  However, instead of our suggestion "ibm-pibs",
the SPDX License List uses "IBM-pibs", with the following rationale:
"The reason being that all other SPDX License List short identifiers
tend towards using capital letters unless spelling a word.  I'd prefer
to be consistent to this end".

Change the license IDs to use the official name.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-09-20 10:30:54 -04:00
York Sun
954a1a4776 powerpc/mpc85xx: Add workaround for erratum A-005125
In a very rare condition, a system hang is possible when the e500 core
initiates a guarded load to PCI / PCIe /SRIO performs a coherent write
to memory. Please refer to errata document for more details. This erratum
applies to the following SoCs and their variants, if any.

BSC9132
BSC9131
MPC8536
MPC8544
MPC8548
MPC8569
MPC8572
P1010
P1020
P1021
P1022
P1023
P2020
C29x

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
2013-09-10 14:31:47 -07:00
Tom Rini
6612ab3395 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2013-08-21 16:27:47 -04:00
Shengzhou Liu
424bf94273 powerpc/sec: Add workaround for SEC A-003571
Multiple read/write transactions initiated by security
engine may cause system to hang.
Workaround: set MCFGR[AXIPIPE] to 0 to avoid hang.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 10:47:07 -07:00
Matthias Fuchs
3fb8588912 ppc4xx: Remove support for PPC405CR CPUs
This patch removes support for the APM 405CR CPU.
This CPU is EOL and no board uses this chip.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2013-08-20 11:35:24 -04:00
Chunhe Lan
9c3f77eb3b fsl_i2c: add workaround for the erratum I2C A004447
This workaround is for the erratum I2C A004447. Device reference
manual provides a scheme that allows the I2C master controller
to generate nine SCL pulses, which enable an I2C slave device
that held SDA low to release SDA. However, due to this erratum,
this scheme no longer works. In addition, when I2C is used as
a source of the PBL, the state machine is not able to recover.

At the same time, delete the reduplicative definition of SVR_VER
and SVR_REV. The SVR_REV is the low 8 bits rather than the low 16
bits of svr. And we use the CONFIG_SYS_FSL_A004447_SVR_REV macro
instead of hard-code value 0x10, 0x11 and 0x20.

The CONFIG_SYS_FSL_A004447_SVR_REV = 0x00 represents that one
version of platform has this I2C errata. So enable this errata
by IS_SVR_REV(svr, maj, min) function.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
2013-08-20 11:15:31 +02:00
Wolfgang Denk
46263f2de4 SPDX-License-Identifier: convert PIBS licensed files
This commit adapts the files that were derived from PIBS (PowerPC
Initialization and Boot Software) codeto using SPDX License
Identifiers.

So far, SPDX has not assigned an official License ID for the PIBS
license yet, so this should be considered preliminary.

Note that the following files contained incorrect license information:

	arch/powerpc/cpu/ppc4xx/4xx_uart.c
	arch/powerpc/cpu/ppc4xx/start.S
	arch/powerpc/include/asm/ppc440.h

These files included, in addition to the GPL-2.0 / ibm-pibs dual
license as inherited from PIBS, a GPL-2.0+ license header which was
obviously incorrect.  This has been removed.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>

Conflicts:
	Licenses/README
Acked-by: Stefan Roese <sr@denx.de>
2013-08-19 15:34:14 -04:00
ramneek mehresh
9dee205d78 fsl/usb: Move USB internal phy definitions to fsl_usb.h
fsl_usb.h file created to share data bewteen usb platform code
and usb ip driver. Internal phy structure definitions moved to
this file

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-14 10:58:01 -07:00
Prabhakar Kushwaha
a4c955bc3b powerpc/mpc85xx:Avoid hardcoded init for serdes block 1 & 2
It is not necessary for all processor to have serdes block 1 & 2.
They may have only one serdes block.

So, put serdes block 1 & 2 related code under defines

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-14 10:57:49 -07:00
Mingkai Hu
3b75e98273 powerpc/85xx: Add C29x SoC support
The Freescale C29x family is a high performance crypto co-processor.
It combines a single e500v2 core with necessary SEC engine. There're
three SoC types(C291, C292, C293) with the following features:

 - 512K L2 Cache/SRAM and 512 KB platform SRAM
 - DDR3/DDR3L 32bit DDR controller
 - One PCI express (x1, x2, x4) Gen 2.0 Controller
 - Trust Architecture 2.0
 - SEC6.0 engine

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>
2013-08-09 12:41:42 -07:00
Zang Roy-R61911
1218f7eb11 powerpc/pcie: remove PCIe version 3.x define for B4860 and B4420
B4860 and B4420 has PCIe version 2.4 IP instead of 3.x

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2013-08-09 12:41:42 -07:00
Zang Roy-R61911
7b4e58440f powerpc/pcie: add PCIe version 3.x support
T4240 PCIe IP is version 3.0 and has some update comparing previous
QorIQ products.

1.  Move Freescale specific register define
to
arch/powerpc/include/asm/fsl_pci.h
and update the register offset define for T4240.

2. add the status/control register define
use status/control register to judge the link status

3. The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is RC or EP mode.

This patch fixes  the PCIe card link up issue on T4240QDS.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:41 -07:00
Shaveta Leekha
40f398a42b powerpc/asm: Move function declaration of 'serdes_get_prtcl' to fsl_serdes.h
It allows files not in the same path to use this function
as required by B4 board file

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
2013-08-09 12:41:41 -07:00
Shaveta Leekha
6fbe988901 powerpc/mpc85xx: Add defines for serdes RSTCTL register
Also change the define name SRDS_RSTCTL_SDPD to
SRDS_RSTCTL_SDEN, which stands for SerDes enable
as mentioned in SerDes module guide

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
2013-08-09 12:41:41 -07:00
Priyanka Jain
f9d379a707 board/bsc9132qds: Configure DSP DDR controller
BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side
DDR. They are mapped to PowerPC and DSP CCSR space respectively.
BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC
and other to DSP side controller.

Configure DSP DDR controller similar to PowerPC side DDR controller as
memories are exactly similar.

Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:40 -07:00
Priyanka Jain
64501c6698 board/bsc9132qds: Add DSP side tlb and laws
BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a
integrated device that contains two powerpc e500v2 cores and two DSP
starcores.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 and M3 memory
-Creating LAW for 1GB DDR which is connected exclusively to DSP-cores

Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:40 -07:00
York Sun
d217a9ad01 powerpc/mpc85xx: Workaround for A-005812
Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can
result in invalid atomic operations. For u-boot, this erratum only impacts
SoCs running in write shadow mode.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:40 -07:00
York Sun
c63e137014 powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:39 -07:00
York Sun
b61e061566 powerpc/mpc8xxx: Add x4 DDR device support
On selected platforms, x4 DDR devices can be supported. Using x4 devices may
lower the performance, but generally they are available for higher density.

Tested on MT36JSF2G72PZ-1G9E1 RDIMM.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:39 -07:00
York Sun
d2ab4bbc7b powerpc/corenet: Move CONFIG_FSL_CORENET out of board header file
Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board
specific feature and belongs to SoC header.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:38 -07:00
Liu Gang
08047937b4 powerpc/t4: Correct LIODN assignment for SRIO
For T4 platform, the SRIO LIODN registers are in SRIO address space
and not in GUTs.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2013-08-09 12:41:38 -07:00
Liu Gang
32f38ee3ed powerpc/b4860: Correct LIODN assignment for SRIO
For B4, the SRIO LIODN registers are in SRIO address space and not
in GUTs.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2013-08-09 12:41:37 -07:00
Liu Gang
b383102040 powerpc/srio: Update the SRIO LIODN registers and ID table macro
For some PowerPC platforms, LIODN registers for SRIO ports are
in SRIO register address space. So the ccsr_rio structure should
be updated for those LIODN registers.

In addition, add a new macro "SET_SRIO_LIODN_BASE" to create
the SRIO LIODN ID table based on the SRIO LIODN register address.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:37 -07:00
Tom Rini
c2120fbfbc Merge branch 'master' of git://git.denx.de/u-boot-i2c
The sandburst-specific i2c drivers have been deleted, conflict was just
over the SPDX conversion.

Conflicts:
	board/sandburst/common/ppc440gx_i2c.c
	board/sandburst/common/ppc440gx_i2c.h

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:50:24 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Dirk Eibach
880540decf i2c, ppc4xx_i2c: switch to new multibus/multiadapter support
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2013-07-23 08:34:56 +02:00
Scott Wood
8212519254 powerpc/mpc85xx: work around erratum A-006593
Erratum A-006593 is "Atomic store may report failure but still allow
the store data to be visible".

The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit
21 to 1'b1.  This may have a small impact on synthetic write bandwidth
benchmarks but should have a negligible impact on real code."

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:49 -05:00
Mingkai Hu
362ee04b79 fsl_ifc: add support for different IFC bank count
Calculate reserved fields according to IFC bank count

1. Move csor_ext register behind csor register and fix res offset
2. Move ifc bank count to config_mpc85xx.h to support 8 bank count
3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile
   error on some devices that does not have IFC controller.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:49 -05:00
Liu Gang
69fdf90010 powerpc/t4qds: Slave module for boot from SRIO and PCIE
When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
	1. Set all the cores in holdoff status.
	2. Set the boot location to one PCIE or SRIO interface by RCW.
	3. Set a specific TLB entry for the boot process.
	4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
	5. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	6. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	7. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:49 -05:00
Liu Gang
5870fe44b2 powerpc/b4860qds: Slave module for boot from SRIO and PCIE
When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
	1. Set all the cores in holdoff status.
	2. Set the boot location to one PCIE or SRIO interface by RCW.
	3. Set a specific TLB entry for the boot process.
	4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
	5. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	6. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	7. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:48 -05:00
Liu Gang
c8b281524b powerpc/boot: Change the macro of Boot from SRIO and PCIE master module
Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.

Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:48 -05:00
Andy Fleming
8bd00c9494 85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT
All the other constants use lowercase 'x' in "MPC85xx", so we
duplicate that here.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:09 -05:00
York Sun
061ffedaaf powerpc/BSC9132: Add IFC bank count
BSC9132 has 3 IFC banks.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:09 -05:00
Priyanka Jain
765b0bdb89 board/bsc9131rdb: Add DSP side tlb and laws
BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:08 -05:00
Scott Wood
a166fbca20 powerpc: fix 8xx and 82xx type-punning warnings with GCC 4.7
C99's strict aliasing rules are insane to use in low-level code such as a
bootloader, but as Wolfgang has rejected -fno-strict-aliasing in the
past, add a union so that 16-bit accesses can be performed.

Compile-tested only.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Wolfgang Denk <wd@denx.de>
2013-06-11 22:01:45 +02:00
Albert ARIBAUD
a19b0dd62d Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	common/cmd_fpga.c
	drivers/usb/host/ohci-at91.c
2013-05-30 14:45:06 +02:00
Ruchika Gupta
39bdaff4f4 SECURE BOOT - Removed deletion of TLB entries code
Boot ROM code creates TLB entries for 3.5G space before entering
the u-boot. Earlier we were deleting these entries after early
initialization of CPU. In recent past, code has been added
to invalidate all these entries before relocation of u-boot code.
So this code to delete TLB entries after CPU initialization
is no longer required.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Acked-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:14 -05:00
Shaveta Leekha
6eaeba23dd powerpc/b4860qds: Add LAW Target ID and Create LAW entry for Maple
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:14 -05:00
Poonam Aggrwal
8fa0102bcf powerpc/B4: Merge B4420 and B4860 in config_mpc85xx.h
B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify
the defines.
- Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere.
- defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G.

Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:14 -05:00
York Sun
f69814397e powerpc/chassis2: Change core numbering scheme
To align with chassis generation 2 spec, all cores are numbered in sequence.
The cores may reside across multiple clusters. Each cluster has zero to four
cores. The first available core is numbered as core 0. The second available
core is numbered as core 1 and so on.

Core clocks are generated by each clusters. To identify the cluster of each
core, topology registers are examined.

Cluster clock registers are reorganized to be easily indexed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:11 -05:00
York Sun
5f208d118a powerpc/mpc8xxx: Add T1040 and variant SoCs
T1040 and variants have e5500 cores and are compliant to QorIQ Chassis
Generation 2. The major difference between T1040 and its variants is the
number of cores and the number of L2 switch ports.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:11 -05:00
York Sun
3d2972feac powerpc/T4160: Merge T4160 and T4240 in config_mpc85xx.h
T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify
the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:11 -05:00
James Yang
9cd95ac74a Add e6500 L2 replacement policy selection
This is compile-time config.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:10 -05:00
Tom Rini
fb651b10d4 Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx 2013-05-15 08:41:04 -04:00
Wolfgang Denk
d6ed322222 Power: remove support for Freescale MPC8220
The Freescale MPC8220 Power Architecture processors have long reached
EOL; Freescale does not even list these any more on their web site.

Remove the code to avoid wasting maitaining efforts on dead stuff.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
2013-05-15 08:41:03 -04:00
Shengzhou Liu
fbe27ce7ba powerpc/85xx: fix build error introduced by serdes_get_prtcl
Removed unused declare serdes_get_prtcl() which was no longer needed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:24 -05:00
Shengzhou Liu
959278083d t4240qds/eth: fixup ethernet for t4240qds
1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
   slots and interfaces.
3, Adding detection of slot present for XGMII interface.
4, There is no PHY for XFI, so removed related phy address settings.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:24 -05:00
York Sun
b62408464b powerpc/mpc85xx: Add T4160 SoC
T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:29 -05:00
Roy Zang
1e501f9136 T4/USB: Add USB 2.0 UTMI dual phy support
T4240 internal UTMI phy is different comparing to previous UTMI PHY
in P3041.
This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for
T4240.
The phy timing is very sensitive and moving the phy enable code to
cpu_init.c will not work.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:28 -05:00
York Sun
45c18853d8 powerpc/mpc85xx: Update corenet global utility block registers
Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse
status register.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:24 -05:00
Andy Fleming
cd7ad62996 powerpc/mpc85xx: Add definitions for HDBCR registers
Makes it a bit easier to see if we've properly set them. While
we're in there, modify the accesses to HDBCR0 and HDBCR1  to actually
use those definitions.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:24 -05:00
Albert ARIBAUD
ec7023db8d Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	drivers/mtd/nand/mxc_nand_spl.c
	include/configs/m28evk.h
2013-05-11 09:25:36 +02:00
York Sun
e22be77a4a powerpc/mpc85xx: Extend workaround for erratum DDR_A003 to other SoCs
Erratum DDR_A003 applies to P5020, P3041, P4080, P3060, P2041, P5040.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:57:33 -05:00
Prabhakar Kushwaha
f153b682b3 powerpc/mpc85xx:IFC Errata A003399 is not valid for BSC913x
As per Errata list of BSC9131 and BSC9132, IFC Errata A003399 is no more
valid. So donot compile its workaround.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:44 -05:00
Xulei
99d7b0a43d powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0)
On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal
multi-bit ECC errors, which has impact on performance, so software should
disable all ECC reporting from USB1 and USB2.

In formal release document, the errata number should be USB14 instead of USB138.

Signed-off-by: xulei <Lei.Xu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: xulei <B33228@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:44 -05:00
Zang Roy-R61911
c5729f0b1f fman/mEMAC: set SETSP bit in IF_MODE regisgter for RGMII speed
Some legacy RGMII phys don't have in band signaling for the
speed information. so set the RGMII MAC mode according to
the speed got from PHY.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Reported-by: John Traill <john.traill@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:44 -05:00
Shengzhou Liu
04feb57f89 powerpc/b4860: Adding workaround errata A-005871
Per the latest errata updated, B4860/B4420 Rev 1.0 has also
errata A-005871, so adding define A-005871 for B4 SoCs.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:43 -05:00
Liu Gang
ada961e2fc powerpc/b4: Fix the wrong register offset of B4 PCIE module
B4420/B4860 PCIE can not work because of the wrong definition of
the PCIE register offset in the file:
	arch/powerpc/include/asm/immap_85xx.h

Add the judgement of B4420/B4860 to make the register offset to:
	#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET         0x200000

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:43 -05:00
Benoît Thébaudeau
0f67e09e9e Add fsl_iim driver
Add a fsl_iim driver common to i.MX and MPC.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:07:41 +02:00
Simon Glass
660c60c4e7 ppc: Enable generic board support
This enables generic board support so that ppc boards can define
CONFIG_SYS_GENERIC_BOARD.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:00 -04:00
Simon Glass
1865286466 Introduce generic link section.h symbol files
We create a separate header file for link symbols defined by the link
scripts. It is helpful to have these all in one place and try to
make them common across architectures. Since Linux already has a similar
file, we bring this in even though many of the symbols there are not
relevant to us.

Each architecture has its own asm/sections.h where symbols specifc to
that architecture can be added. For now everything except AVR32 just
includes the generic header.

One change is needed in arch/avr32/lib/board.c to make this conversion
work.

Reviewed-by: Tom Rini <trini@ti.com> (version 5)
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:58 -04:00
Simon Glass
3929fb0a14 Replace __bss_end__ with __bss_end
Note this is a tree-wide change affecting multiple architectures.

At present we use __bss_start, but mostly __bss_end__. This seems
inconsistent and in a number of places __bss_end is used instead.

Change to use __bss_end for the BSS end symbol throughout U-Boot. This
makes it possible to use the asm-generic/sections.h file on all
archs.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:54 -04:00
Anatolij Gustschin
a615dfda8c mpc512x: Adjust the DRAM init sequence to the datasheet spec
Do maintain a 200 usecs period of stable power and clock before
asserting the CKE signal and sending commands, have at least 200
DRAM clock cycles pass after initialization before data access.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-09 08:23:02 +01:00
Anatolij Gustschin
fcc7fe4251 mpc512x: add ifm ac14xx board
Add new mpc5121e based ac14xx board and a new pinmux config
function for setting individual pinmux bit groups. This
function is used in ac14xx board code.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-09 08:22:57 +01:00
Anatolij Gustschin
5643709ede mpc512x: allow configuring board specific IPS divider
Boards may define own IPS divider in the config file if
the default IPS divider doesn't fit their needs.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-09 08:22:50 +01:00
Anatolij Gustschin
1d63b8ffdb mpc512x: optionally configure DIU, LPC and NFC deviders
If a board config file defines DIU, LPC and NFC deviders,
configure them in the SCFR1 register.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-09 08:22:45 +01:00
Simon Glass
2ab575e05d powerpc: Use generic global_data
Move powerpc over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
e9adeca3fc ppc: arm: Move sdhc_clk into arch_global_data
This is used by both powerpc and arm, but I think it still qualifies as
architecture-specific.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
225ca83dfe ppc: Move kbd_status to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
a0d3c820c4 ppc: Move wdt_last to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
923a662f2f ppc: Move fpga_state to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
7273ccec61 ppc: Remove console_addr from global data
This does not appear to be used, so punt it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
7e15d6dbf3 ppc: Move mirror_hack to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
3a1dc8f125 arm: Move uart_clk to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
6bb9ba7260 ppc: Move dp_alloc_base, dp_alloc_top to arch_global_data
Move these fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
43e60814b3 ppc: Move arbiter fields to arch_global_data
Move arbiter_event_attributes and arbiter_event_address into
arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
3c4c308c00 ppc: Move reset_status to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
1c356135fa ppc: Move mpc8220 clocks to arch_global_data
Move these fields into arch_global_data and tidy up. The bExtUart field
does not appear to be used, so punt it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
fefb098b18 ppc: Move mpc512x clocks to arch_global_data
Move ips_clk and csb_clk into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
b28774966c ppc: Move mpc5xxx clocks to arch_global_data
Move ipb_clk and pci_clk into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
7c80c6c51a ppc: Move used_tlb_cams to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
8670dbc953 ppc: Move used_laws to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
45bae2e3cf ppc: Move CONFIG_QE to arch_global_data
Move the quantative easing fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:42 -05:00
Simon Glass
609e6ec3f6 ppc: m68k: Move i2c1_clk, i2c2_clk to arch_global_data
Move these fields into arch_global_data and tidy up. This is needed for
both ppc and m68k since they share the i2c driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:42 -05:00
Simon Glass
67ac13b1b9 ppc: Move lbc_clk and cpu to arch_global_data
Move these fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Update for bsc9132qds.c, b4860qds.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-04 09:04:57 -05:00
Simon Glass
c6731fe22a ppc: Move mpc83xx clock fields to arch_global_data
Move al mpc83xx fields into arch_global_data and tidy up. Also indent
the nested #ifdef for clarity.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
748cd0591a ppc: Move clock fields to arch_global_data
Move vco_out, cpm_clk, scc_clk, brg_clk into arch_global_data and tidy
up. Leave pci_clk on its own since this should really depend only on
CONFIG_PCI and not any particular chip type.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
9fb23624a6 ppc: Remove extra pci_clk fields from global_data
PPC has several of these fields, selected by chip type, although only one
is ever compiled in.

Instead, use a single field. It would be nice if this could be selected
by CONFIG_PCI, but some chips (e.g. mpc5xxx) use pci_clk even when
CONFIG_PCI is not enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
1206c18403 ppc: Move brg_clk to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
5cb48582ac Add architecture-specific global data
We plan to move architecture-specific data into a separate structure so
that we can make the rest of it common.

As a first step, create struct arch_global_data to hold these fields.
Initially it is empty.

This patch applies to all archs at once. I can split it if this is really
a pain.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:49 -05:00
Shengzhou Liu
72bd83cd0a powerpc/t4240: Adding workaround errata A-005871
When CoreNet Fabric (CCF) internal resources are consumed by the cores,
inbound SRIO messaging traffic through RMan can put the device into a
deadlock condition.

This errata workaround forces internal resources to be reserved for
upstream transactions. This ensures resources exist on the device for
upstream transactions and removes the deadlock condition.

The Workaround is for the T4240 silicon rev 1.0.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Vakul Garg
5e95e2d84b powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto'
If property 'fsl,sec-era' is already present, it is updated.
This property is required so that applications can ascertain which
descriptor commands are supported on a particular CAAM version.

Signed-off-by: Vakul Garg <vakul@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Scott Wood
31d084ddda powerpc/mpc85xx: add support for MMUv2 page sizes
e6500 implements MMUv2 and supports power-of-2 page sizes rather than
power-of-4.  Add support for such pages.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Prabhakar Kushwaha
35fe948e3b powerpc/mpc85xx: Add BSC9132/BSC9232 processor support
The BSC9132 is a highly integrated device that targets the evolving
 Microcell, Picocell, and Enterprise-Femto base station market subsegments.

 The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
 core technologies with MAPLE-B2P baseband acceleration processing elements
 to address the need for a high performance, low cost, integrated solution
 that handles all required processing layers without the need for an
 external device except for an RF transceiver or, in a Micro base station
 configuration, a host device that handles the L3/L4 and handover between
 sectors.

 The BSC9132 SoC includes the following function and features:
    - Power Architecture subsystem including two e500 processors with
	512-Kbyte shared L2 cache
    - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
	cache
    - 32 Kbyte of shared M3 memory
    - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
      Processing (MAPLE-B2P)
    - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
      ECC), up to 1333 MHz data rate
    - Dedicated security engine featuring trusted boot
    - Two DMA controllers
         - OCNDMA with four bidirectional channels
         - SysDMA with sixteen bidirectional channels
    - Interfaces
        - Four-lane SerDes PHY
	    - PCI Express controller complies with the PEX Specification-Rev 2.0
        - Two Common Public Radio Interface (CPRI) controller lanes
	    - High-speed USB 2.0 host and device controller with ULPI interface
        - Enhanced secure digital (SD/MMC) host controller (eSDHC)
	    - Antenna interface controller (AIC), supporting four industry
		standard JESD207/four custom ADI RF interfaces
       - ADI lanes support both full duplex FDD support & half duplex TDD
       - Universal Subscriber Identity Module (USIM) interface that
	   facilitates communication to SIM cards or Eurochip pre-paid phone
	   cards
       - Two DUART, two eSPI, and two I2C controllers
       - Integrated Flash memory controller (IFC)
       - GPIO
     - Sixteen 32-bit timers

Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:14 -06:00
Poonam Aggrwal
e1dbdd8152 powerpc/mpc85xx:Add support of B4420 SoC
B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900
and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and
reduced target frequencies.

Key differences between B4860 and B4420
----------------------------------------
B4420 has:
1. Fewer e6500 cores: 1 cluster with 2 e6500 cores
2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
3. Single DDRC
4. 2X 4 lane serdes
5. 3 SGMII interfaces
6. no sRIO
7. no 10G

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Poonam Aggrwal
e394ceb17f powerpc/mpc85xx: Few updates for B4860 cpu changes
- Added some more serdes1 and serdes2 combinations
  serdes1= 0x2c, 0x2d, 0x2e
  serdes2= 0x7a, 0x8d, 0x98
- Updated Number of DDR controllers to 2.
- Added FMAN file for B4860, drivers/net/fm/b4860.c

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Simon Glass
b1f17bf5ff Add strcasecmp() and strncasecmp()
strncasecmp() is present as strnicmp() but disabled. Make it available
and define strcasecmp() also. There is a only a small performance penalty
to having strcasecmp() call strncasecmp(), so do this instead of a
standalone function, to save code space.

Update the prototype in arch-specific headers as needed to avoid warnings.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-11 13:17:34 -07:00
Stefan Roese
083f2e08d2 mpc5200: Add SPL support
This patch adds SPL booting support (NOR flash) for the
MPC5200 platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05 17:30:51 +01:00
Stefan Roese
966b11c749 powerpc: Extract EPAPR_MAGIC constants into processor.h
By extracting these defines into a header, they can be re-used by other
C sources as well. This will be done by the SPL framework OS boot
support.

Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05 17:27:02 +01:00
Timur Tabi
b25f6de7c0 powerpc/85xx: update the work-around for P4080 erratum SERDES-9
The documented work-around for P4080 erratum SERDES-9 has been updated.
It is now compatible with the work-around for erratum A-4580.

This requires adding a few bitfield macros for the BnTTLCRy0 register.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
Yuanquan Chen
c0a4e6b889 powerpc/p4080ds: fix PCI-e x8 link training down failure
Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.

Signed-off-by: Yuanquan Chen <B41889@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
Zang Roy-R61911
9760b274df powerpc/corenet_ds: move SATA config to board configuration
board configuration file is included before asm/config_mpc85xx.h.
however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h.
it will never take effective in the board configuration file for
this kind of code :

 #ifdef CONFIG_FSL_SATA_V2
 ...
 #endif

To solve this problem, move CONFIG_FSL_SATA_V2 to board
configuration header file.

This patch reverts Timur's
commit:3e0529f742e893653848494ffb9f7cd0d91304bf

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
Timur Tabi
d607b9684b powerpc/85xx: implement check for erratum A-004580 work-around
The work-around for erratum A-004580 ("Internal tracking loop can falsely
lock causing unrecoverable bit errors") is implemented via the PBI
(pre-boot initialization code, typically attached to the RCW binary).
This is because the work-around is easier to implement in PBI than in
U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004580, we can do this by verifying
that the values in the specific registers that the work-around says to
update.

This change requires access to the SerDes lane sub-structure in
serdes_corenet_t, so we make it a named struct.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
York Sun
2a5fcb835f powerpc/mpc85xx: Temporary fix for spin table backward compatibility
Once u-boot sets the spin table to cache-enabled memory, old kernel which
uses cache-inhibit mapping without coherence will not work properly. We
use this temporary fix until kernel has updated its spin table code.
For now this fix is activated by default. To disable this fix for new
kernel, set environmental variable "spin_table_compat=no". After kernel
has updated spin table code, this default shall be changed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:06 -06:00
Timur Tabi
0118033b67 powerpc/85xx: implement check for erratum A-004849 work-around
The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a
deadlock under certain traffic patterns causing the system to hang") is
implemented via the PBI (pre-boot initialization code, typically attached
to the RCW binary).  This is because the work-around is easier to implement
in PBI than in U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004849, we can do this by verifying
that the values in the specific registers that the work-around says to
update.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:06 -06:00
Timur Tabi
1956e431f8 powerpc/85xx/p5040: add CONFIG_SYS_PPC64, del CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
The P5040 has an e5500 core, so CONFIG_SYS_PPC64 should be defined in
config_mpc85xx.h.  This macro was absent in the initial P5040 patch because
it crossed paths with the patch that introduced the macro.

Also delete CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC, since it's not used in the
upstream U-Boot.  It's a holdover from the SDK.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:05 -06:00
Andy Fleming
e76cd5d4cf 8xxx: Change all 8*xx_DDR addresses to 8xxx
There were a number of shared files that were using
CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.

This patch does:

s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g

All 85xx, 86xx, and 83xx have been built with this change.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Andy Fleming <afleming@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-27 17:45:17 -06:00
Kim Phillips
cdfdb8d7f3 arch/powerpc/include/asm/io.h: fix warning: preprocessor token __iomem redefined
a fixup __iomem definition in arch code appears to be placed there as a cover
up from a code import from linux when u-boot didn't yet have a compiler.h,
introduced by commit 812711ce6b "Implement
__raw_{read,write}[bwl] on all architectures".

git show 812711ce6b3a386125dcf0d6a59588e461abbb87:include/linux/compiler.h
fatal: Path 'include/linux/compiler.h' exists on disk, but not in '812711ce6b3a386125dcf0d6a59588e461abbb87'.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:35 -07:00
Kim Phillips
eef1cf2d5c include/linux/byteorder: import latest endian definitions from linux
u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives.  Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h.  They come with 'const' added for some swab functions, so
fix those up, too:

include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]

Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).

We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:

macb.c:54:0: warning: "barrier" redefined [enabled by default]

In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)).  This fixes
arch/powerpc/lib/bootm.c:

bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token

powerpc sparse builds yield:

include/common.h:356:22: error: marked inline, but without a definition

the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'

also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]

and:

Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here

and:

In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini <trini@ti.com>
2012-11-04 11:00:34 -07:00
Gerlando Falauto
a88731a6c2 mpc83xx: add support for mpc8309
This processor, though very similar to other members of the
PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides
yet another feature set than any supported sibling.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23 15:23:26 -05:00
Gerlando Falauto
8afad91f15 cleanup: introduce CONFIG_MPC830x
Introduce a new configuration token CONFIG_MPC830x to be shared among
mpc8308 and mpc8309. Define it for existing 8308 boards, and refactor
existing common code so to make future introduction of 8309 simpler.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23 15:23:25 -05:00
Liu Gang
19e4a00965 powerpc/boot: Change the compile macro for SRIO & PCIE boot master module
Currently, the SRIO and PCIE boot master module will be compiled into the
u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this
macro has been included by all the corenet architecture platform boards.
But in fact, it's uncertain whether all corenet platform boards support
this feature.

So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add
a special macro for every board which can support the feature. This
special macro will be defined in the header file
"arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO
and PCIE boot master module should be compiled into the board u-boot image.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 15:52:46 -05:00
York Sun
ffd06e0231 powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:32 -05:00
York Sun
a1d558a20f powerpc/mpc85xx: Add workaround for DDR erratum A004934
After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:29 -05:00
York Sun
eb53941206 powerpc/mpc85xx: software workaround for DDR erratum A-004468
Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:28 -05:00
York Sun
f31cfd1925 powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT
When ECC is enabled, DDR controller needs to initialize the data and ecc.
The wait time can be calcuated with total memory size, bus width, bus speed
and interleaving mode. If it went wrong, it is bettert to timeout than
waiting for D_INIT to clear, where it probably hangs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:27 -05:00
York Sun
123922b1e5 powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation
Fix handling quad-rank DIMMs in a system with two DIMM slots and first
slot supports both dual-rank DIMM and quad-rank DIMM.

For systems with quad-rank DIMM and double dual-rank DIMMs, cs_config
registers need to be enabled to maintain proper ODT operation. The
inactive CS should have bnds registers cleared.

Fix the turnaround timing for systems with all chip-selects enabled. This
wasn't an issue before because DDR was running lower than 1600MT/s with
this interleaving mode.

Fix DDR address calculation. It wasn't an issue until we have multiple
controllers with each more than 4GB and interleaving is disabled.

It also fixes the message of DDR: 2 GiB (DDR3, 64-bit, CL=0.5, ECC off)
when debugging DDR and first DDR controller is disabled. With the fix,
the first enabled controller information will be displayed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:26 -05:00
York Sun
57495e4e5e powerpc/mpc8xxx: Update DDR registers
DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be
set for speed lower than 1250MT/s.

CDR1 and CDR2 are control driver registers. ODT termination valueis for
IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is
	000 -> Termsel off
	001 -> 120 Ohm
	010 -> 180 Ohm
	011 -> 75 Ohm
	100 -> 110 Ohm
	101 -> 60 Ohm
	110 -> 70 Ohm
	111 -> 47 Ohm

Add two write leveling registers. Each QDS now has its own write leveling
start value. In case of zero value, the value of QDS0 will be used. These
values are board-specific and are set in board files.

Extend DDR register timing_cfg_1 to have 4 bits for each field.

DDR control driver registers and write leveling registers are added to
interactive debugging for easy access.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:26 -05:00
Roy Zang
111fd19e3b fm/mEMAC: add mEMAC frame work
The multirate ethernet media access controller (mEMAC) interfaces to
10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII
interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface.

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:25 -05:00
York Sun
d2404141f9 powerpc/mpc85xx: Add B4860 and variant SoCs
Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):

Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
    clusters-each core runs up to 1.2 GHz, with an architecture highly
    optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
    cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
    each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
    including Turbo or Viterbi decoding, Turbo encoding and rate matching,
    MIMO MMSE equalization scheme, matrix operations, CRC insertion and
    check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
    and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
    the e6500 cores, SC3900 FVP cores, memories and external interfaces.
    CoreNet fabric interconnect runs at 667 MHz and supports coherent and
    non-coherent out of order transactions with prioritization and
    bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
  Frame Manager (FMan), which supports in-line packet parsing and general
    classification to enable policing and QoS-based packet distribution
  Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
    of queue management, task management, load distribution, flow ordering,
    buffer management, and allocation tasks from the cores
  Security engine (SEC 5.3)-crypto-acceleration for protocols such as
    IPsec, SSL, and 802.16
  RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
    outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
    bandwidth saving and high utilization of processor elements. The
    9856-Kbyte internal memory space includes the following:
  32 Kbyte L1 ICache per e6500/SC3900 core
  32 Kbyte L1 DCache per e6500/SC3900 core
  2048 Kbyte unified L2 cache for each SC3900 FVP cluster
  2048 Kbyte unified L2 cache for the e6500 cluster
  Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
  Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
    of up to 8 lanes
  Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
    less antenna connection
  Two 10-Gbit Ethernet controllers (10GEC)
  Six 1G/2.5-Gbit Ethernet controllers for network communications
  PCI Express controller
  Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:24 -05:00
York Sun
9e75875849 powerpc/mpc85xx: Add T4240 SoC
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):

12 dual-threaded e6500 cores built on Power Architecture® technology
  Arranged as clusters of four cores sharing a 2 MB L2 cache.
  Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
    v2.06-compliant)
  Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
  CoreNet fabric supporting coherent and non-coherent transactions with
    prioritization and bandwidth allocation amongst CoreNet end-points
  1.6 Tbps coherent read bandwidth
  Queue Manager (QMan) fabric supporting packet-level queue management and
    quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
    support
  Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
    the following functions:
  Packet parsing, classification, and distribution (Frame Manager 1.1)
  Queue management for scheduling, packet sequencing, and congestion
    management (Queue Manager 1.1)
  Hardware buffer management for buffer allocation and de-allocation
    (BMan 1.1)
  Cryptography acceleration (SEC 5.0) at up to 40 Gbps
  RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
  Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
  DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
  Up to four 10 Gbps Ethernet MACs
  Up to sixteen 1 Gbps Ethernet MACs
  Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
  Four PCI Express 2.0/3.0 controllers
  Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
    Type 11 messaging and Type 9 data streaming support
  Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
  Two serial ATA (SATA 2.0) controllers
  Two high-speed USB 2.0 controllers with integrated PHY
  Enhanced secure digital host controller (SD/MMC/eMMC)
  Enhanced serial peripheral interface (eSPI)
  Four I2C controllers
  Four 2-pin or two 4-pin UARTs
  Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:23 -05:00
Andy Fleming
f311838ded powerpc/mpc85xx: Add T4 device definitions
The T4 has added devices to previous corenet implementations:

* SEC has 3 more DECO units
* New PMAN device
* New DCE device

This doesn't add full support for the new devices. Just some
preliminary support.

Move PMAN LIODN to upper half of register

Despite having only one LIODN, the PMAN LIODN is stored in the
upper half of the register. Re-use the 2-LIODN code and just
set the LIODN as if the second one is 0. This results in the
actual LIODN being written to the upper half of the register.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:22 -05:00
York Sun
d1001e3f0c powerpc/corenet2: Add SerDes for corenet2
Create new files to handle 2nd generation Chassis as the registers are
organized differently.

 - Add SerDes protocol parsing and detection
 - Add support of 4 SerDes
 - Add CPRI protocol in fsl_serdes.h
	The Common Public Radio Interface (CPRI) is publicly available
	specification that standardizes the protocol interface between the
	radio equipment control (REC) and the radio equipment (RE) in wireless
	basestations. This allows interoperability of equipment from different
	vendors,and preserves the software investment made by wireless service
	providers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:19 -05:00
York Sun
fd3cebd020 powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2
Corenet 2nd generation Chassis has different RCW and registers for SerDes.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:18 -05:00
York Sun
92230d49da powerpc/e6500: Move QCSP registers for QMan v3
The QCSP registers are expanded and moved from offset 0 to offset 0x1000
for SoCs with QMan v3.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:18 -05:00
York Sun
f8f85b049c powerpc/mpc85xx: expand SERDES reference clock select bit
Expand the reference clock select to three bits
000: 100 MHz
001: 125 MHz
010: 156.25MHz
011: 150 MHz
100: 161.1328125 MHz
All others reserved

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:17 -05:00
York Sun
9a653a9810 powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2
Corenet based SoCs have different core clocks starting from Chassis
generation 2. Cores are organized into clusters. Each cluster has up to
4 cores sharing same clock, which can be chosen from one of three PLLs in
the cluster group with one of the devisors /1, /2 or /4. Two clusters are
put together as a cluster group. These two clusters share the PLLs but may
have different divisor. For example, core 0~3 are in cluster 1. Core 4~7
are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2
are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group
A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have
PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1.

PME and FMan blocks can take different PLLs, configured by RCW.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:16 -05:00
York Sun
f77329cfcf powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2
Chassis generation 2 has different mask and shift. Use macro instead of
magic numbers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
York Sun
6d2b9da19c powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.

Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
York Sun
553ae6f8f2 powerpc/DPAA: Fix compiling error
FSL_HW_PORTAL_PME is used even when CONFIG_SYS_DPAA_PME is not defined.
Remove the #ifdef.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:14 -05:00
Timur Tabi
4905443f1c powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:

Four P5040 single-threaded e5500 cores built
    Up to 2.4 GHz with 64-bit ISA support
    Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
    2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
        support Up to 1600MT/s
    Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
    Packet parsing, classification, and distribution (FMAN)
    Queue management for scheduling, packet sequencing and
    congestion management (QMAN)
    Hardware buffer management for buffer allocation and
    de-allocation (BMAN)
    Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
    20 lanes at up to 5 Gbps
    Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
    Two 10 Gbps Ethernet MACs
    Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
    Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
    Two serial ATA (SATA 2.0) controllers
    Two high-speed USB 2.0 controllers with integrated PHY
    Enhanced secure digital host controller (SD/MMC/eMMC)
    Enhanced serial peripheral interface (eSPI)
    Two I2C controllers
    Four UARTs
    Integrated flash controller supporting NAND and NOR flash
DMA
    Dual four channel
Support for hardware virtualization and partitioning enforcement
    Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
    Secure boot, secure debug, tamper detection, volatile key storage

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:13 -05:00
Timur Tabi
fd946040f1 powerpc/85xx: define SRIO LIODN functions only if SRIO is defined
The P5040 does not have SRIO support, so there are no SRIO LIODNs.
Therefore, the functions that set the SRIO LIODNs should not be compiled.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:13 -05:00
Laurentiu Tudor
e389a377ee powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs
The liodn for the new PCIE controller included in P5040DS is no longer set
through a register in the guts register block but with one in the PCIE
register block itself.  Update the PCIE CCSR structure to add the new liodn
register and add a new dedicated SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:12 -05:00
Liu Gang
d59c557049 powerpc/srio: Workaround for srio erratrm a004034
Erratum: A-004034
Affects: SRIO

Description: During port initialization, the SRIO port performs
lane synchronization (detecting valid symbols on a lane) and
lane alignment (coordinating multiple lanes to receive valid data
across lanes). Internal errors in lane synchronization and lane
alignment may cause failure to achieve link initialization at
the configured port width.

An SRIO port configured as a 4x port may see one of these scenarios:

1.	One or more lanes fails to achieve lane synchronization.
	Depending on which lanes fail, this may result in downtraining
	from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane).

2.	The link may fail to achieve lane alignment as a 4x, even
	though all 4 lanes achieve lane synchronization, and downtrain
	to a 1x. An SRIO port configured as a 1x port may fail to complete
	port initialization (PnESCSR[PU] never deasserts) because of
	scenario 1.

Impact: SRIO port may downtrain to 1x, or may fail to complete
link initialization. Once a port completes link initialization
successfully, it will operate normally.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:12 -05:00
Zang Roy-R61911
4e0be34a85 P4080/esdhc: make the P4080 ESDHC13 errata workaround conditional
P4080 Rev3.0 fixes ESDHC13 errata, so update the code to make the
workaround conditional.
In formal release document, the errata number should be ESDHC13 instead
of ESDHC136.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 03:04:28 -05:00
Chris Packham
168e5bc409 mpc85xx: make gpio_direction_output respect value
Users of familiar with the Linux gpiolib API expect that value parameter
to gpio_direction_output reflects the initial state of the output pin.
gpio_direction_output was always driving the output low, now it drives
it high or low according to the value provided.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 03:03:16 -05:00
Simon Glass
a7e5ee9ebb powerpc: Change bi_baudrate and global data baudrate to int
These don't need to be longs, so change them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:45 -07:00
Stefan Roese
a821d08dca ppc4xx: Remove AP1000 board support
As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: James MacAulay <james.macaulay@amirix.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-15 11:53:59 -07:00
Stefan Roese
dee9c534db ppc4xx: Remove ML2 board support
As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peter De Schrijver <p2@mind.be>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-15 11:53:59 -07:00
Stefan Roese
99bcad1809 ppc4xx: Remove IOP480 support
Since the IOP480 (PPC401/3 variant from PLX) is only used on 2
boards that are not actively maintained, lets remove support
for it completely. This way the ppc4xx code will get a bit cleaner.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-15 11:53:59 -07:00
Tom Rini
5675b50916 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2012-09-25 12:23:55 -07:00
Anatolij Gustschin
e5ab702a6c powerpc: re-add bi_ip_addr to bd_t struct
Since commit 50a47d0523
(net: punt bd->bi_ip_addr) booting old 2.4.x ppc kernels
is broken due to changed offsets of the fields in struct bd_t.
Offsets of the fields after removed bi_ip_addr are wrong,
causing wrong bus clocks and console baudrate configurations
and various other issues. Re-add the bi_ip_addr field to preserve
backward compatibility with older ppc kernels. Setting bi_ip_addr
in board.c is not really needed, grepping in the 2.4 linux tree
shows that bi_ip_addr is not accessed there. Adding bi_ip_addr
to struct bd_t for other arches isn't needed it seems. bd_t is
not used by other arches in the 2.4 linux tree.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
2012-09-02 22:55:59 +02:00
Andy Fleming
98ae9ac434 Revert "powerpc: Fix declaration type for I/O functions"
This reverts commit 20959471b5.
2012-08-23 12:16:57 -05:00
Scott Wood
3ea21536d7 powerpc/85xx: clear out TLB on boot
Instead of just shooting down the entry that covers CCSR, clear out
every TLB entry that isn't the one that we're executing out of.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:57 -05:00
York Sun
7ac3cc20e0 powerpc/mpc8xxx: Move HWCONFIG_BUFFER_SIZE into config.h
Before proper environment is setup, we extract hwconfig and put it into a
buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to
accommodate longer string. Since this macro is used in multiple files, we
move it into arch/powerpc/include/asm/config.h.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:56 -05:00
York Sun
a4c66509f1 powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving
Restructure DDR interleaving option to support 3 and 4 DDR controllers
for 2-, 3- and 4-way interleaving.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
73b5396b25 powerpc/mpc8xxx: Add fine timing support for DDR3
When the DDR3 speed goes higher, we need to utilize fine offset
from SPD.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
709389b654 powerpc/mpc8xxx: fix core id for multicore booting
For the cores with multiple threads, we need to figure out which physical
core a thread belongs. To match the core ids, update PIR registers and
spin tables.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
Kumar Gala
ffdf8890ae Added new ext fields to IFC
In case more than 32 bit address is used, the EXT bit should be set.
Need to fix up address map for IFC #CS for 4, also need to move # of IFC
banks into config_mpc85xx.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
Kumar Gala
50d96e95b4 Add IFC offset for DPAA/Corenet platforms
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
Kumar Gala
5b6b85ae63 Add e6500 processor detection
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
York Sun
123bd96d53 powerpc/mpc8xxx: use topology registers to calculate number of cores
We have actual topology infomation to find out exactly which core is present.
Calculate the number of cores if not specified.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
York Sun
1ca8690d27 powerpc/mpc8xxx: Add immap for topology and rcpm registers
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Prabhakar Kushwaha
3854173aa8 powerpc/mpc85xx: Add IFC LAW target ID for FSL High-End SoC
Freescale's High-End SoC are going to have Integrated Flash controller
(IFC)'s support.

So add IFC LAW target ID support for High-End SoC or corenet SoC.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Prabhakar Kushwaha
e4879afba3 powerpc/mpc85xx:Enable debugger support to missed e500v2 SoC
Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG). Need to define define
CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be
used during boot to work around the limitations.

Enable missed e500v2 SoC i.e. MPC8536, MPC8544, MPC8548 and MPC8572 for
debug support.

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Scott Wood
33eee330cc powerpc/fsl-corenet: work around erratum A004510
Erratum A004510 says that under certain load conditions, modified
cache lines can be discarded, causing data corruption.

To work around this, several CCSR and DCSR register updates need to be
made in a careful manner, so that there is no other transaction in
corenet when the update is made.

The update is made from a locked cacheline, with a delay before to flush
any previous activity, and a delay after to flush the CCSR/DCSR update.
We can't use a readback because that would be another corenet
transaction, which is not allowed.

We lock the subsequent cacheline to prevent it from being fetched while
we're executing the previous cacheline.  It is filled with nops so that a
branch doesn't cause us to fetch another cacheline.

Ordinarily we are running in a cache-inhibited mapping at this point, so
we temporarily change that.  We make it guarded so that we should never
see a speculative load, and we never do an explicit load.  Thus, only the
I-cache should ever fill from this mapping, and we flush/unlock it
afterward.  Thus we should avoid problems from any potential cache
aliasing between inhibited and non-inhibited mappings.

NOTE that if PAMU is used with this patch, it will need to use a
dedicated LAW as described in the erratum.  This is the responsibility
of the OS that sets up PAMU.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Scott Wood
3e978f5dc8 powerpc/fsl-corenet: remove dead variant symbols
These are not supported as individual build targets, but instead
are supported by another target.

The dead p4040 defines in particular had bitrotted significantly.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Timur Tabi
055ce08004 powerpc/85xx: remove support for the Freescale P3060
The P3060 was cancelled before it went into production, so there's no point
in supporting it.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:53 -05:00
Timur Tabi
99abf7ded3 powerpc/85xx: add support for FM2 DTSEC5
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:18 -05:00
Matthew McClintock
9c6b47d53e p1014rdb: set ddr bus width properly depending on SVR
Currently, for NAND boot for the P1010/4RDB we hard code the DDR
configuration. We can still dynamically set the DDR bus width in
the nand spl so the P1010/4RDB boards can boot from the same
u-boot image

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:16 -05:00
York Sun
be7bebeac2 powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list
P1015 is the same as P1011 and P1016 is the same as P1012 from software
point of view. They have different packages but share SVRs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:16 -05:00
Liu Gang
81fa73bab0 powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro
When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.

This has the following advantages:
	1. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just rewrite the new RCW with selected port,
	   then the code will get the port information by reading new RCW.
	2. It will be easier to support other boot location options, for
	   example, boot from PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:14 -05:00
Liu Gang
ff65f12699 powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target
Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
"bootmaster" to "SRIO1" or "SRIO2" using the following command:

		setenv bootmaster SRIO1
		saveenv

The "bootmaster" will enable the function of the SRIO boot master, and
this has the following advantages compared with SRIOBOOT_MASTER build
configuration:
	1. Reduce a build configuration item in boards.cfg file.
	   No longer need to build a special image for master, just use a
	   normal target image and set the "bootmaster" variable.
	2. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just set the corresponding value to "bootmaster"
	   based on the using SRIO port.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:14 -05:00
York Sun
57125f222e powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditional
This erratum applies to the following SoCs:
P4080 rev 1.0, 2.0, fixed in rev 3.0
P2041 rev 1.0, 1.1, fixed in rev 2.0
P3041 rev 1.0, 1.1, fixed in rev 2.0.

Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround
may degrade performance. P4080 erratum CPU22 shares the same workaround.
So it is always enabled for P4080. For other SoCs, it can be disabled by
hwconfig with syntax:

fsl_cpu_a011:disable

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:13 -05:00
Prabhakar Kushwaha
20959471b5 powerpc: Fix declaration type for I/O functions
Prototype declaration of I/O operation functions are not correct. as both
'extern' and function definition are at same place.

Chage protoype declaration as static.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-08-09 22:24:31 +02:00