Commit graph

522 commits

Author SHA1 Message Date
Troy Kisky
af2a35fb1f i.mx: iomux-v3.h: move to imx-common include directory
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31 08:00:19 +02:00
Troy Kisky
d3394ec198 iomux-v3: remove include of mx6x_pins.h
This include is not needed.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-07-31 07:59:56 +02:00
Tetsuyuki Kobayashi
5eb497429e arm: armv7: add compile option -mno-unaligned-access if available
Recent compiler generates unaligned memory access in armv7 default.
But current U-Boot does not allow unaligned memory access, so it causes
data abort exception.
This patch add compile option "-mno-unaligned-access" if it is available.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Tested-by: Gary Thomas <gary@mlbassoc.com>
2012-07-20 14:24:08 +02:00
Zhong Hongbo
448217d4b2 arm: Fix to mistake clean the memory space
In currently, when __bss_start is equal to __bss_end__,
The bss loop will clear all the things in memory space.

But just only when __bss_end__ greater than __bss_start__,
we do the clear bss section operation.

Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-07-20 14:24:08 +02:00
Wolfgang Denk
895f3e0542 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  tegra: define fdt_load/fdt_high variables
  tegra: enable bootz command
  tegra: usb: Fix device enumeration problem of USB1
  tegra: trimslice: set up serial flash pinmux
  tegra: add pin_mux_spi() board initialization function
  tegra: add GMC/GMD funcmux entry for SFLASH
  tegra: bootcmd: start USB only when needed
  tegra: bootcmd enhancements
  tegra: add enterrcm command
  tegra: enable CONFIG_ENV_VARS_UBOOT_CONFIG
  Add env vars describing U-Boot target board
  tegra: usb: fix wrong error check
  tegra: add ULPI on USB2 funcmux entry
  tegra: fix leftover CONFIG_TEGRA2_MMC & _SPI build switches
  tegra: Add Tamonten Evaluation Carrier support
  tegra: Use SD write-protect GPIO on Tamonten
  tegra: Implement gpio_early_init() on Tamonten
  tegra: Allow boards to perform early GPIO setup
  tegra: plutux: Add device tree support
  tegra: medcom: Add device tree support
  tegra: Rework Tamonten support
  beagle: add eeprom expansion board info for bct brettl4

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-10 08:54:41 +02:00
Rajeshwari Shinde
30704dae46 EXYNOS: Fix USB compiler warning
Fixed the compiler warning message.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-07-10 08:50:05 +02:00
Wolfgang Denk
ba662f8998 Merge branch 'master' of git://git.denx.de/u-boot-usb
* 'master' of git://git.denx.de/u-boot-usb:
  CONFIG: EXYNOS5: USB: Enable USB 2.0 on smdk5250
  EXYNOS5: USB: Fix incorrect USB base addresses
  EXYNOS: Add power Enable/Disable for USB-EHCI
  USB: EXYNOS: Set USB 2.0 HOST Link mode
  EXYNOS5: Add structure for PMU registers
  EXYNOS5: Fix system register structure
  USB: EXYNOS: Incorporate EHCI review comments

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-09 23:59:00 +02:00
Stephen Warren
a016e144ed tegra: add GMC/GMD funcmux entry for SFLASH
This is used on TrimSlice.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-09 22:44:33 +02:00
Stephen Warren
9cd3f3adf0 tegra: add enterrcm command
Tegra's boot ROM supports a mode whereby code may be downloaded and flash
programmed over a USB connection. On dev boards, this is typically entered
by holding down a "force recovery" button and resetting the CPU. However,
not all boards have such a button (one example is the Compulab Trimslice),
so a method to enter RCM from software is useful.

This change implements the command "enterrcm" to do this, and enables it
for all Tegra boards by default. Even on boards other than Trimslice,
controlling this over a UART may be useful, e.g. to allow simple remote
control without the need for mechanical button actuators, or hooking up
relays/... to the button.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-09 22:44:33 +02:00
Lucas Stach
f857fff606 tegra: usb: fix wrong error check
loop_count runs down from 10000, so the correct condition to error out
is ==0.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <twarren.nvidia@gmail.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-09 22:44:33 +02:00
Lucas Stach
f97daaa231 tegra: add ULPI on USB2 funcmux entry
This is needed as a prerequisite for Tegra USB ULPI support
within U-Boot.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-09 22:44:33 +02:00
Rajeshwari Shinde
c48ac11322 EXYNOS: Add power Enable/Disable for USB-EHCI
This patch adds functions to enable/disable the power of USB
host controller for EXYNOS5.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
2012-07-09 18:27:55 +02:00
Rajeshwari Shinde
71045da812 USB: EXYNOS: Set USB 2.0 HOST Link mode
This patch adds a function to set usb host mode to USB 2.0 HOST Link
for EXYNOS5

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
2012-07-09 18:27:55 +02:00
Wolfgang Denk
18277f7057 Revert "arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0"
This reverts commit fa042186b9.
It causes build warnings like this:
cpu.c:48:1: warning: -fstack-usage not supported for this target
[enabled by default]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-09 09:19:00 +02:00
Fabio Estevam
5427d29c26 No need to define CONFIG_ARCH_CPU_INIT.
All mx6 based boards should use arch_cpu_init().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-07-07 14:07:44 +02:00
Tetsuyuki Kobayashi
fa042186b9 arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0
save_boot_params_default() in cpu.c accesses uninitialized stack area
when it compiled with -O0 (not optimized).

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Tom Rini <trini@ti.com>
2012-07-07 14:07:36 +02:00
SRICHARAN R
5e9cd44ca0 ARM: OMAP4/5: Move USB clocks to essential group.
USB clocks will be required for fastboot, tftp
related functionalities. Move these clocks to
essential group inorder to have the functionality
working when non-essential clocks are not enabled.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:36 +02:00
SRICHARAN R
dbf8fb6ad1 ARM: OMAP4/5: Move gpmc clocks to essential group.
GPMC clocks are currently getting enabled as a part
non-essential clocks. This will be required during
NOR boot. Move this to essential group to keep the
functionality, when non-essential clocks are not
enabled.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:36 +02:00
SRICHARAN R
254763822e ARM: OMAP4+: Move external phy initialisations to arch specific place.
The external phy is present in the case OMAP5 soc is currently
configured in emif-common.c. This results in having dummy structures
for those Socs which do not have a external phy. So by having a weak
function in emif-common and overriding it in OMAP5, avoids the use
of dummy structures.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:35 +02:00
Sebastien Jan
cc009defa4 omap4: Use a smaller M,N couple for IVA DPLL
This reduced M,N couple corresponds to the advised value from
TI HW team.

Tested on 4460 Pandaboard, it also provides peripheral clocks
closer to the advised values.

Signed-off-by: Sebastien Jan <s-jan@ti.com>
2012-07-07 14:07:35 +02:00
Steve Sakoman
ad0878a749 omap: emif: fix bug in manufacturer code test
Code currently tests for <= 0xff.  Micron manufacturer code is 0xff, so
Micron memory will not be detected!

Signed-off-by: Steve Sakoman <steve@sakoman.com>
2012-07-07 14:07:35 +02:00
Steve Sakoman
55c1284942 omap: emif: deal with rams that return duplicate mr data on all byte lanes
Some rams (Micron for example) return duplicate mr data on all byte lanes.

Users of the get_mr function currently don't deal with this duplicated
data gracefully.  This patch detects the duplicated data and returns only
the expected 8 bit mr data.

Signed-off-by: Steve Sakoman <steve@sakoman.com>
2012-07-07 14:07:35 +02:00
Lokesh Vutla
38f25b125e OMAP4+: Force DDR in self-refresh after warm reset
Errata ID:i727

Description: The refresh rate is programmed in the EMIF_SDRAM_REF_CTRL[15:0]
REG_REFRESH_RATE parameter taking into account frequency of the device.
When a warm reset is applied on the system, the OMAP processor restarts
with another OPP and so frequency is not the same. Due to this frequency
change, the refresh rate will be too low and could result in an unexpected
behavior on the memory side.

Workaround:
The workaround is to force self-refresh when coming back from the warm reset
with the following sequence:
• Set EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
• Set EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM to 0x0
• Do a dummy read (loads automatically new value of sr_tim)
This will reduce the risk of memory content corruption, but memory content
can't be guaranteed after a warm reset.

This errata is impacted on
OMAP4430: 1.0, 2.0, 2.1, 2.2, 2.3
OMAP4460: 1.0, 1.1
OMAP4470: 1.0
OMAP5430: 1.0

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
2012-07-07 14:07:35 +02:00
Lokesh Vutla
784229cc25 OMAP4+: Handle sdram init after warm reset
EMIF and DDR device state are preserved in warmreset.  Redoing the full
initialisation would cause unexpected behaviour.  Do only partial
initialisation to account for frequency change.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
2012-07-07 14:07:34 +02:00
Lokesh Vutla
702395073f ARM: OMAP3+: Detect reset type
Certain modules are not affected by means of
a warm reset and need not be configured again.
Adding an API to detect the reset reason warm/cold.

This will be used to skip the module configurations
that are retained across a warm reset.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:34 +02:00
Tetsuyuki Kobayashi
f8b9d1d30e arm: bugfix: Move vector table before jumping relocated code
Interrupts and exceptions doesn't work in relocated code.
It badly use IRQ_STACK_START_IN in rom area as interrupt stack.
It is because the vecotr table is not moved to ram area.
This patch moves vector table before jumping relocated code.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Tested-by: Tom Rini <trini@ti.com>
2012-07-07 14:07:33 +02:00
Michael Langer
5c23712dbd i.MX6 USDHC: Use the ESDHC clock
The commit "i.mx: fsl_esdhc: add the i.mx6q support" (4692708d) introduces
support for the i.MX6Q MMC host controller USDHC.

MXC_IPG_PERCLK sets the clock to 66MHz. This seems to be the default clock
of the ESDHC IP found in < i.MX6 silicon. However, the default clock for the USDHC
IP found in i.MX6 is 200MHz (MXC_ESDHC_CLK). This difference will cause a 3 times
higher clock on SD_CLK than expected (see fsl_esdh.c -> set_sysctl()).

Signed-off-by: Michael Langer <michael.langer@de.bosch.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <r64343@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-07 14:07:29 +02:00
Fabio Estevam
3f5f200bbe mx53: Fix mask for SATA reference clock
SATA_ALT_REF_CLK field corresponds to bits 1 and 2 of offset 0x180c.

Fix the mask for these bits.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-07 14:07:25 +02:00
Rajeshwari Shinde
c5e3710a18 EXYNOS5: PINMUX: Added default pinumx settings
This patch performs the pinmux configuration in a common file.
As of now only EXYNOS5 pinmux for SDMMC, UART and Ethernet is
supported.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-07-07 14:07:25 +02:00
Minkyu Kang
7775831dd3 Exynos: fix cpuinfo and cpu detecting
Since Exynos architecture have new SoCs,
need to fix cpuinfo correctly.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Chander Kashyap <chander.kashyap@linaro.org>
2012-07-07 14:07:25 +02:00
Lokesh Vutla
7fd5b9bfe4 OMAP5: Change voltages for omap5432
Change voltages for OMAP5432

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:24 +02:00
Lokesh Vutla
753bae8c5d OMAP5: DPLL core lock for OMAP5432
No need to Unlock DPLL initially.
DDR3 can work at normal OPP from initialozation

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:24 +02:00
Lokesh Vutla
784ab7c545 OMAP5: EMIF: Add support for DDR3 device
In OMAP5432 EMIF controlller supports DDR3 device.
This patch adds support for ddr3 device intialization and configuration.
Initialization sequence is done as specified in JEDEC specs.
This also adds support for ddr3 leveling.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:24 +02:00
Lokesh Vutla
43037d7631 OMAP5: ADD precalculated timings for ddr3
Adding precalculated timings for ddr3 with 1cs
adding required registers for ddr3

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:23 +02:00
Lokesh Vutla
eb4e18e89e OMAP5: Configure the io settings for omap5432 uevm board
This patch adds the IO settings required for OMAP5432 uevm's DDR3 pads

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:23 +02:00
Lokesh Vutla
0a0bf7b217 OMAP5: ADD chip detection for OMAP5432 SOC
This patch adds chip detection for OMAP5432

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:23 +02:00
SRICHARAN R
41321fd4d6 ARM: OMAP5: Align memory used for testing to the power of 2
get_ram_size checks the given memory range for valid ram,
but expects the size of memory to be aligned to the power
of 2. In case of OMAP5 evm board the memory available is
2GB - 16MB(used for TRAP section) = 2032MB.

So always ensure that the size of memory used for testing is
aligned to the power of 2.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:22 +02:00
SRICHARAN R
77efdeb758 ARM: OMAP5: dmm: Create a tiler trap section.
The unmapped entries in tiler space are set with
values 0xFF. So creating a DMM section of
size 16MB at 0xFF000000 with ADDRSPACE set to 0x2.

This way all the unmapped entry accesses to tiler
will be trapped by the EMIF and a error response
is sent to the L3 interconnect. L3 errors are
inturn reported to MPU.

Note that here the tiler trap section is overlapping
with the actual ddr physical space and we lose 16MB
out of the total 2GB.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:22 +02:00
SRICHARAN R
e06e914d87 ARM: OMAP4+: dmm: Take care of overlapping dmm and trap sections.
The DMM sections can be overlapping with each other, with
sections 3 to 0 having the highest to lowest priority in that
order. There could also be a section that is used trap the
unmapped Tiler entries and this trap section could be
overlapping with the actual sdram area.

So take care of the above scenarios while calculating the
size of the actual ram.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:21 +02:00
Tom Rini
2ab2810375 am33xx: Do not call init_timer twice
We do not need to call init_timer both in SPL and U-Boot itself, just
SPL needs to initialize the timer.

Signed-off-by: Tom Rini <trini@ti.com>
2012-07-07 14:07:21 +02:00
Tom Warren
76e350b7a3 arm: Tegra: Use ODMDATA from BCT in IRAM
Walk the BIT and BCT to find the ODMDATA word in the
CustomerData field and put it into Scratch20 reg for
use by kernel, etc.

Built all Tegra builds OK; Booted on Seaboard and saw
ODMDATA in PMC scratch20 was the same as the value in my
burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities
will have to specify the odmdata (nvflash --odmdata n) on
the command line or via a cfg file, or built in to their
BCT.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2012-07-07 14:07:21 +02:00
amartin@nvidia.com
f3717ac584 tegra: override compiler flags for low level init code
Override -march setting for tegra to -march=armv4t for files that are
necessary for low level init on tegra.

The recent change to use -march=armv7-a for armv7 caused a regression
on tegra because tegra starts boot on a arm7tdmi processor before
transferring control to the cortex-a9.  While still executing on the
arm7tdmi there are calls to getenv_ulong() and memset() that cause an
illegal instruction exception if compiled for armv7.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:19 +02:00
Simon Glass
27c4a3318f tegra: Correct PLL access in ap20.c and clock.c
Correct this warning seen by Albert:

ap20.c:44:18: warning: array subscript is above array bounds

There is a subtle bug here which currently causes no errors, but might
in future if people use PCI or the 32KHz clock. So take the opportunity
to correct the logic now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:19 +02:00
Stephen Warren
d1e4607901 tegra: add SDMMC1 on SDIO1 funcmux entry
This will be used on TrimSlice.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:18 +02:00
Lucas Stach
a2cfe63eeb tegra: add SDIO1 funcmux entry for UARTA
This is based on top of:
tegra: add alternate UART1 funcmux entry
tegra: add UART1 on GPU funcmux entry

v2: remove enum change

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <twarren@nvidia.com>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:18 +02:00
Stephen Warren
e21649be56 tegra: add UART1 on GPU funcmux entry
TrimSlice uses UART1 on the GPU pingroup.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:18 +02:00
Stephen Warren
b9607e7061 tegra: add alternate UART1 funcmux entry
(In at least some configurations) Whistler uses UART1 on pingroups
UAA, UAB.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:17 +02:00
Matt Porter
a3c3fabb0f arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx
In warm reset conditions on OMAP36xx/AM/DM37xx the rom code
incorrectly sets the DPLL4 clock input divider to /6.5 which
is an invalid value unless the input clock is 13MHz. When a JTAG
emulator is attached, a warm reset is necessary after the emulator
gains control of the process. This results in a loss of serial
output due to the invalid DPLL4 settings.

This patch fixes the issue by resetting the DPLL4 clock input
divider to /1 when the input clock is not 13MHz. AM/DM37x TRM
section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only
used when the input clock is 13MHz.

Signed-off-by: Matt Porter <mporter@ti.com>
2012-05-15 08:31:41 +02:00
Tero Kristo
2d622b03f8 omap4: do not enable auxiliary cores
Booting up these cores (dsp / ivahd / cortex-m3) is bad without
firmware running on them, and they will hang preventing any kind
of sleep transitions later on with the kernel.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:41 +02:00
Tero Kristo
71ee921de0 omap4: do not enable fs-usb module
If this is done in the bootloader, the FS-USB will later be stuck into
intransition state, which will prevent the device from entering idle.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2012-05-15 08:31:41 +02:00
Lucas Stach
b8cb5194f0 tegra2: trivially enable 13 mhz crystal frequency
This is needed for upcoming Toradex Colibri T20 upstream support.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:40 +02:00
Simon Glass
7e91f40dd5 tegra: Add keyboard support to funcmux
Add funcmux support for the default keyboard mapping.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:39 +02:00
Yen Lin
c5179da9f3 tegra: Setup PMC scratch info from ap20 setup
Save SDRAM parameters into the warmboot scratch registers

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:38 +02:00
Yen Lin
6570438a70 tegra: Add warmboot implementation
Add code to set up the warm boot area in the Tegra CPU ready for a
resume after suspend.

Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:38 +02:00
Jimmy Zhang
6860b4a1cc tegra: Add PMU to manage power supplies
Power supplies must be adjusted in line with clock frequency. This code
provides a simple routine to set the voltage to allow operation at maximum
frequency.

- Split PMU code into separate TPS6586X driver

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:38 +02:00
Jimmy Zhang
0e35ad053f tegra: Add EMC support for optimal memory timings
Add support for setting up the memory controller parameters. Boards
can set up an appropriate table in the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:38 +02:00
Simon Glass
d515362d4d tegra: Add tegra_get_chip_type() to detect SKU
We want to know which type of chip we are running on - the Tegra
family has several SKUs. This can be determined by reading a
fuse register, so add this function to ap20.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:37 +02:00
Yen Lin
2a6f036a9a tegra: Add crypto library for warmboot code
Provides an interface to aes.c for the warmboot code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:37 +02:00
Simon Glass
ffc76482c2 tegra: Add functions to access low-level Osc/PLL details
Add clock_ll_read_pll() to read PLL parameters and clock_get_osc_bypass()
to find out if the Oscillator is bypassed. These are needed by warmboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:37 +02:00
Simon Glass
f9f3e1b8df tegra: Move ap20.h header into arch location
We want to include this from board code, so move the header into
an easily-accessible location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:37 +02:00
Simon Glass
a35925b8c1 Add abs() macro to return absolute value
This macro is generally useful to make it available in common.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-05-15 08:31:37 +02:00
Eric Nelson
64e7cdb5e8 i.MX6: add enable_sata_clock()
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:33 +02:00
Dirk Behme
cac833a98c i.MX6: Add ANATOP regulator init
Init the core regulator voltage to 1.2V. This is required for the correct
functioning of the GPU and when the ARM LDO is set to 1.225V. This is a
workaround to fix some memory clock jitter.

Note: This should be but can't be done in the DCD. The bootloader
      prevents access to the ANATOP registers.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Chen <b02280@freescale.com>
CC: Jason Liu <r64343@freescale.com>
CC: Ranjani Vaidyanathan <ra5478@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <festevam@gmail.com>
2012-05-15 08:31:33 +02:00
Fabio Estevam
1fc56f1cb0 mx53loco: Allow to print CPU information at a later stage
Print CPU information within board_late_init().

This is in preparation for adding 1GHz support, which requires programming a PMIC
via I2C. As I2C is only available after relocation, print the CPU information
later at board_late_init(), so that the CPU frequency can be printed correctly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:32 +02:00
Fabio Estevam
70cc86a630 mx5: Add clock config interface
mx5: Add clock config interface

Add clock config interface support, so that we
can configure CPU or DDR clock in the later init

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Signed-off-by: Eric Miao <eric.miao@linaro.org>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-05-15 08:31:32 +02:00
Fabio Estevam
6a376046ef imx-common: Factor out get_ahb_clk()
get_ahb_clk() is a common function between mx5 and mx6.

Place it into imx-common directory.

Cc: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-05-15 08:31:32 +02:00
Stefano Babic
8c38b5d03d MX53: add function to set SATA clock to internal
The MX53 SATA interface can use an internal clock (USB PHY1)
instead of an external clock. This is an undocumented feature, but used
on most Freescale's evaluation boards, such as MX53-loco.

As stated by Freescale's support:

Fuses (but not pins) may be used to configure SATA clocks.
Particularly the i.MX53 Fuse_Map contains the next information
about configuring SATA clocks :
	SATA_ALT_REF_CLK[1:0] (offset 0x180C)

'00' - 100MHz (External)
'01' - 50MHz (External)
'10' - 120MHz, internal (USB PHY)
'11' - Reserved

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
2012-05-15 08:31:30 +02:00
Stefano Babic
d87c85ce43 MX5: Add definitions for SATA controller
Add base address and MXC_SATA_CLK to return
the clock used for the SATA controller.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
2012-05-15 08:31:30 +02:00
Donghwa Lee
37835d4ba8 EXYNOS: add LCD and MIPI DSI clock interface.
To sets up lcd and mipi clock in EXYNOS display driver, added clock interface.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-05-15 08:31:29 +02:00
Donghwa Lee
283591f171 EXYNOS: definitions of system resgister and power management registers.
This is definitions of system registers and power mananagement registers for EXYNOS SoC.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-05-15 08:31:29 +02:00
Tom Rini
8a87a3d72e omap3: Introduce weak misc_init_r
Introduce a __weak misc_init_r function that just runs dieid_num_r().
Remove misc_init_r from cm_t35, mcx, omap3_logic and mt_ventoux as this was
all they did for misc_init_r.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Peter Barada <peter.barada@logicpd.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2012-05-15 08:31:28 +02:00
Tom Rini
aa2889c8c3 omap4+: Remove CONFIG_ARCH_CPU_INIT
OMAP4/5 had an empty arch_cpu_init() so drop that along with
CONFIG_ARCH_CPU_INIT

Signed-off-by: Tom Rini <trini@ti.com>
2012-05-15 08:31:27 +02:00
Aneesh V
f61faeba82 armv7: Use -march=armv7-a and thereby enable Thumb-2
Enable -march=armv7-a for armv7 platforms if the tool-chain
supports it. This in turn results in Thumb-2 code generated
for these platforms if CONFIG_SYS_THUMB_BUILD is enabled.

Signed-off-by: Aneesh V <aneesh@ti.com>
2012-05-15 08:31:26 +02:00
Aneesh V
74236acacc armv7: add appropriate headers for assembly functions
Use ENTRY and ENDPROC with assembly functions to ensure
necessary assembler directives for all functions.

Signed-off-by: Aneesh V <aneesh@ti.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-05-15 08:31:26 +02:00
SRICHARAN R
0696473be7 OMAP5: reset: Use cold reset in case of 5430ES1.0
Warm reset is not functional in case of omap5430ES1.0.
So override the weak reset_cpu function to use
cold reset instead.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:25 +02:00
SRICHARAN R
d417d1db5f OMAP3+: reset: Create a common reset layer.
The reset.S has the function to do a warm reset on OMAP
based socs. Moving this to a reset.c file so that this
acts a common layer to add any reset related functionality
for the future.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:25 +02:00
Balaji T K
f75231b79a arm: omap5: correct boot device mode7 for eMMC
In OMAP5 Boot device mode of 6 and 7 should be mapped to mmc2/eMMC

Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-05-15 08:31:25 +02:00
SRICHARAN R
971f2ba21a OMAP5: ddr: Change the ddr device name.
The ddr part name used in OMAP5 ES1.0 soc is a SAMSUNG part and
not a ELPIDA part. So change this.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:24 +02:00
SRICHARAN R
c1fa3c37af OMAP4/5: device: Add support to get the device type.
Add support to identify the device as GP/EMU/HS.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:24 +02:00
SRICHARAN R
002a2c0c66 OMAP4/5: Make the sysctrl structure common
Make the sysctrl structure common, so that it can
be used in generic functions across socs.
Also change the base address of the system control module, to
include all the registers and not simply the io regs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:24 +02:00
SRICHARAN R
087189fb54 OMAP4/5: Make the silicon revision variable common.
The different silicon revision variable names was defined for OMAP4 and
OMAP5 socs. Making the variable common so that some code can be
made generic.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:24 +02:00
SRICHARAN R
cdd50a8d07 OMAP5: hwinit: Add the missing break statement
The break statement is missing in init_omap_revision function, resulting
in a wrong revision identification. So fixing this.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:24 +02:00
SRICHARAN R
8de17f4617 OMAP5: palmas: Configure nominal opp vdd values
The nominal opp vdd values as recommended for
ES1.0 silicon is set for mpu, core, mm domains using palmas.

Also used the right sequence to enable the vcores as per
a previous patch from Nishant Menon, which can be dropped now.
	http://lists.denx.de/pipermail/u-boot/2012-March/119151.html

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:23 +02:00
SRICHARAN R
f40107345c OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon.
The OMAP5 silicon has new DDR PHY design, which includes a external PHY
as well. So configuring the ext PHY parameters here. Also the EMIF timimg
registers and a couple of DDR mode registers needs to be updated based on
the testing from the actual silicon.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:23 +02:00
SRICHARAN R
6ad8d67de8 OMAP5: io: Configure the io settings for omap5430 sevm board.
The control module provides options to set various signal
integrity parameters like the output impedance, slew rate,
load capacitance for different pad groups. Configure these
as required for the omap5430 sevm board.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:23 +02:00
SRICHARAN R
5f14d9197e OMAP5: clocks: Change clock settings as required for ES1.0 silicon.
Aligning all the clock related settings like the dpll frequencies, their
respective clock outputs, etc to the ideal values recommended for
OMAP5430 ES1.0 silicon.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:23 +02:00
Nishanth Menon
f2ae6c1a83 OMAP4: scale voltage of core before MPU scales
OMAP4 requires that parent domains scale ahead of dependent domains.
This is due to the restrictions in timing closure. To ensure
a consistent behavior across all OMAP4 SoC, ensure that
vdd_core scale first, then vdd_mpu and finally vdd_iva.

As part of doing this refactor the logic to allow for future
addition of OMAP4470 without much ado. OMAP4470 uses different
SMPS addresses and cannot be introduced in the current code
without major rewrite.

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2012-05-15 08:31:22 +02:00
Nishanth Menon
3acb553439 OMAP4460: TPS Ensure SET1 is selected after voltage configuration
TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as part of
boot sequence.
Current configuration results in the following voltage waveform:
                           |---------------| (SET1 default 1.4V)
                           |               --------(programmed voltage)
                           | <- (This switch happens on mux7,pullup)
vdd_mpu(TPS)         -----/ (OPP boot voltage)
                                             --------- (programmed voltage)
vdd_core(TWL6030)    -----------------------/ (OPP boot voltage)
Problem 1)                |<----- Tx ------>|
   timing violation for a duration Tx close to few milliseconds.
Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP.

By using GPIO as recommended as standard procedure by TI, the sequence
changes to:
                                  -------- (programmed voltage)
vdd_mpu(TPS)         ------------/ (Opp boot voltage)
                                   --------- (programmed voltage)
vdd_core(TWL6030)    -------------/ (OPP boot voltage)

NOTE: This does not attempt to address OMAP5 - Aneesh please confirm

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2012-05-15 08:31:22 +02:00
Nishanth Menon
a78274b205 OMAP3+: Introduce generic logic for OMAP voltage controller
OMAP Voltage controller is used to generically talk to
PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code
in multiple SoC code, introduce a common voltage controller
logic which can be re-used from elsewhere.

With this change, we replace setup_sri2c with omap_vc_init which
has the same functionality, and replace the voltage scale
replication in do_scale_vcore and do_scale_tps62361 with
omap_vc_bypass_send_value. omap_vc_bypass_send_value can also
now be used with any configuration of PMIC.

NOTE: Voltage controller controlling I2C_SR is a write-only data
path, so no register read operation can be implemented.

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2012-05-15 08:31:22 +02:00
Jonathan Solnit
bbbc1ae921 ARM:OMAP+:MMC: Add parameters to MMC init
Add parameters to the OMAP MMC initialization function so the board can
mask host capabilities and set the maximum clock frequency.  While the
OMAP supports a certain set of MMC host capabilities, individual boards
may be more restricted and the OMAP may need to be configured to match
the board.  The PRG_SDMMC1_SPEEDCTRL bit in the OMAP3 is an example.

Signed-off-by: Jonathan Solnit <jsolnit@gmail.com>
2012-05-15 08:31:22 +02:00
Marek Vasut
b6e95fd47d CMD: Fix CONFIG_CMD_SAVEBP_WRITE_SIZE -> CONFIG_CMD_SPL_WRITE_SIZE
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: scottwood@freescale.com
2012-04-19 22:01:13 +02:00
Stefano Babic
38fcc71cc5 ARM: add u-boot.imx as target for i.MX SOCs
Freescale SOCs require an header to u-boot.bin

The patch adds u-boot.imx to the default targets
if the imx file is set (IMX_CONFIG).

Signed-off-by: Stefano Babic <sbabic@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
CC: Loïc Minier <loic.minier@linaro.org>
CC: Mike Frysinger <vapier@gentoo.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Tested-by: Dirk Behme <dirk.behme@googlemail.com>
2012-04-16 14:53:59 +02:00
Eric Nelson
4d422fe2dc i.MX6: implement enable_caches()
disabled by default until drivers are fixed

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-04-16 14:53:58 +02:00
Simon Glass
4a0764858b arm: Use common .lds file where possible
Each cpu directory currently has its own .lds file. This is only needed
in most cases because the start.o file is in a different subdir.

Now that we can factor out this difference, we can move most cpus over
to the common .lds file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-03-30 07:43:47 +02:00
Anatolij Gustschin
27ac87d91e arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix build warnings
Fix:
clocks-common.c: In function 'setup_non_essential_dplls':
clocks-common.c:323:6: warning: variable 'sys_clk_khz' set but not used
[-Wunused-but-set-variable]
clocks-common.c: In function 'setup_non_essential_dplls':
clocks-common.c:323:6: warning: variable 'sys_clk_khz' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Tom Rini <trini@ti.com>
2012-03-29 08:19:29 +02:00
Tom Rini
33fbc9cf82 sdrc.c: Fix typo in do_sdrc_init() for SPL
We need to setup CS0 and CS1 not CS0 and CS0 again.

Signed-off-by: Tom Rini <trini@ti.com>
2012-03-29 08:19:29 +02:00
Simon Glass
2e33559f3d tegra: Enhance clock support to handle 16-bit clock divisors
I2C ports have a 16-bit clock divisor. Add code to handle this special
case so that I2C speeds below 150KHz are supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:50 +02:00
Simon Glass
f4589a7d6f tegra: Rename NV_PA_PMC_BASE to TEGRA2_PMC_BASE
Change this name to fit with the current convention in the Tegra
header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:49 +02:00
Simon Glass
87f938c9f7 tegra: usb: Add support for Tegra USB peripheral
This adds basic support for the Tegra2 USB controller. Board files should
call board_usb_init() to set things up.

Configuration is performed through the FDT, with aliases used to set the
order of the ports, like this fragment:

        aliases {
		/* This defines the order of our USB ports */
                usb0 = "/usb@0xc5008000";
                usb1 = "/usb@0xc5000000";
        };

drivers/usb/host files ONLY: Acked-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:48 +02:00
Simon Glass
ed2974493e tegra: fdt: Add function to return peripheral/clock ID
A common requirement is to find the clock ID for a peripheral. This is the
second cell of the 'clocks' property (the first being the phandle itself).

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:48 +02:00
Simon Glass
c3474ef32d tegra: fdt: Add Tegra2x device tree file from kernel
This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git

config.mk is updated to provide this file to boards through the
built-in mechanism:

/include/ ARCH_CPU_DTS

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:47 +02:00
Tom Warren
d8bd820935 arm: Tegra2: Fix ELDK42 gcc failure with inline asm stack pointer load
The 4.2.2 gcc in the ELDK42 release doesn't like the direct SP
load using a constant in tegra2_start. Change it to use a load
thru another reg using mov sp, %0 : : "r"(CONST).

Tested on my Seaboard T20-A03, U-Boot loads and runs OK. Also
compiled all tegra2 builds with both gcc 4.2.2 and 4.4.1 OK.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2012-03-29 08:12:47 +02:00
Rob Herring
0c34e69f57 ARM: highbank: add reset support
Implement reset for highbank platform. Reset is triggered via a wfi
instruction, so enabling armv7 for the compiler is necessary.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-03-28 23:31:23 +02:00
Rob Herring
877012df30 ARM: highbank: Add boot counter support
Add boot counter support using an sysreg which is persistent across reset.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-03-28 23:31:20 +02:00
Rob Herring
ceb2071c6b ARM: highbank: fix us_to_tick calculation
udelay calls were off due to failing to convert us to ns. Fix this and drop
the unnecessary shifts since NS_PER_TICK is only 7ns.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-03-28 23:31:08 +02:00
Rob Herring
f1e2d1762d ARM: highbank: add missing get_tbclk
The get_tbclk function was missing and the recent commit "common: add
possibility for readline_into_buffer timeout" makes it required.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-03-28 23:30:54 +02:00
Stefano Babic
53c4492c0b SPL: call cleanup_before_linux() before booting Linux
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tom Rini <tom.rini@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
2012-03-27 22:05:29 +02:00
Stefano Babic
da521387a4 OMAP3: SPL: do not call I2C init if no I2C is set.
Call i2c initialization in spl_board_init only if I2C
is configured for the board.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tom Rini <tom.rini@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
2012-03-27 22:05:29 +02:00
Stefano Babic
d460587a44 Add cache functions to SPL for armv7
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tom Rini <tom.rini@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
2012-03-27 22:05:29 +02:00
Simon Schwarz
ace73189a5 omap/spl: change output of spl_parse_image_header
This only outputs "Assuming u-boot.bin..." if debug is active.

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
2012-03-27 22:05:28 +02:00
Simon Schwarz
379c19ab70 omap-common/spl: Add linux boot to SPL
This adds Linux booting to the SPL

This depends on CONFIG_MACH_TYPE patch by Igor Grinberg
(http://article.gmane.org/gmane.comp.boot-loaders.u-boot/105809)

Related CONFIGs:
CONFIG_SPL_OS_BOOT
	Activates/Deactivates the OS booting feature
CONFIG_SPL_OS_BOOT_KEY
	defines the IO-pin number u-boot switch - if pressed u-boot is
	booted
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
	Offset in NAND of direct boot kernel image to use in SPL
CONFIG_SYS_SPL_ARGS_ADDR
	Address where the kernel boot arguments are expected - this is
	normaly RAM-begin + 0x100

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
2012-03-27 22:05:28 +02:00
Simon Schwarz
df163a5980 omap-common: Add NAND SPL linux booting
This implements booting of Linux from NAND in SPL

Related config parameters:
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
	Offset in NAND of direct boot kernel image to use in SPL
CONFIG_SYS_SPL_ARGS_ADDR
	Address where the kernel boot arguments are expected - this is
	normally RAM-start + 0x100 (on ARM)

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
2012-03-27 22:05:28 +02:00
Fabio Estevam
67ee3dd35e mx53: Make PLL2 to be the parent of UART clock
Change the parent UART clock to be PLL2, so that U-boot can also boot
a Freescale 2.6.35 kernel for mx53.

FSL kernel and U-boot changed the UART parent from PLL3 to PLL2 to avoid
conflicts with IPU clocks, so that the video resolution can be changed
without affecting the UART clock.

On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded
and this patch fixes this problem.

Tested on a mx53loco board booting a FSL kernel and also a mainline kernel.

Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2012-03-27 09:41:17 +02:00
Fabio Estevam
a768386746 mx6: Read silicon revision from register
Instead of hardcoding the mx6 silicon revision, read it in run-time.

Also, besides the silicon version print the mx6 variant type: quad,dual/solo
or solo-lite.

Tested on a mx6qsabrelite, where it shows:

CPU:   Freescale i.MX6Q rev1.0 at 792 MHz

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <r64343@freescale.com>
2012-03-27 09:41:16 +02:00
Fabio Estevam
cece262209 mx6: Fix reset cause for Power On Reset case
After booting mx6qsabrelite from POR the following is reported:

CPU:   Freescale i.MX61 family rev1.0 at 792 MHz
Reset cause: unknown reset

This is because both the POR and WDOG bits are set after reset.

Fix this by also checking both bits in the POR case.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-03-27 09:41:16 +02:00
Matt Porter
24de357a30 SPL: Add YMODEM over UART load support
Adds support for loading U-Boot from UART using YMODEM protocol.
If YMODEM support is enabled in SPL and the romcode indicates
that SPL loaded via UART then SPL will wait for start of a
YMODEM transfer via the console port.

Signed-off-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-03-26 23:09:25 +02:00
Tom Rini
ad1820a3c6 spl.c: Use __noreturn decorator
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-03-26 23:09:25 +02:00
Wolfgang Grandegger
3f467529ca usb/ehci: Add USB support for the MX6Q
Currently, only USB Host 1 is supported.

Cc: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
2012-03-26 23:09:23 +02:00
Thomas Weber
b199c6e2d7 Remove execute permissions from source files
Signed-off-by: Thomas Weber <weber@corscience.de>
2012-03-04 21:56:15 +01:00
Aneesh V
f1f2c3ca9f armv7: omap3: leave outer cache enabled
Mainline kernel for OMAP3 doesn't enable L2 cache
It expects L2$ to be enabled by ROM-code/bootloader.

Leaving L2$ enabled can be troublesome in cases where
the L2 cache is not under CP15 control, such as in
Cortex-A9. This problem is explained in detail in
the commit dc7100f408

However, this problem doesn't apply to Cortex-A8
because L2$ in Cortex-A8 is under CP15 control and
hence the generic armv7 maintenance opertions work
for it.

As such we can make an exception for OMAP3 and
leave the L2$ enabled when we jump to kernel. This
is done by removing the strongly-linked implementation
of v7_outer_cache_disable() and allowing it to fall
back to the weakly linked implementation that doesn't
do anything.

Signed-off-by: Aneesh V <aneesh@ti.com>
2012-02-27 21:19:25 +01:00
Stefano Babic
782bb0d236 MX5/MX6: add missing get_ticks() and get_tbclk()
commit f31a911fe (arm, post: add missing post_time_ms for arm)
enables get_ticks and get_tbclk for all arm based boards,
MX5/MX6 have not yet implemented.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Liu <jason.hui@linaro.org>
CC: Marek Vasut <marek.vasut@gmail.com>
2012-02-27 21:19:23 +01:00
Aneesh V
c8ff6a9ed9 OMAP4460: Reduce MPU clock speed from 920 to 700
We do not have thermal management or Smartreflex
enabled at U-Boot level. So, it's better to stick
to OPP100 for MPU instead of the OPP Turbo that is
used now. Adjust the VDD_MPU accordingly.

Tested-by: Sebastien Jan <s-jan@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
2012-02-12 10:11:32 +01:00
Peter Meerwald
a4958313fb omap3: fix comment typos
Signed-off-by: Peter Meerwald <p.meerwald@bct-electronic.com>
2012-02-12 10:11:32 +01:00
Govindraj.R
860004c103 OMAP4: clock-common: Move the usb dppl configuration to new func
usb dpll configuration is done only part of non-essential
dppl configuration however if CONFIG_USB_EHCI_OMAP is defined
we may have to configure usb dpll's for proper functioning
of usb modules. So move the usb dppl configuration to a new func.
and utilise the same during essential dpll configuration.

Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
Tested-by: Stefano Babic <sbabic@denx.de>
2012-02-12 10:11:31 +01:00
Govindraj.R
95f8791042 OMAP3+: Clock: Adding ehci clock enabling
Adding ehci clock enabling mechanism part of clock framework.
When essential clocks are enabled during init phase usb host
clocks can also be enabled from clock framework.

Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
Tested-by: Stefano Babic <sbabic@denx.de>
2012-02-12 10:11:31 +01:00
Chander Kashyap
37bb6d89de ARM: EXYNOS: Add support for Exynos5 based SoCs
Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of
SoCs. This patch adds the support for Exynos5.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-02-12 10:11:30 +01:00
Chander Kashyap
5e46f83cc3 Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro
CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4)
architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ
to make it generic for exynos architecture.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-02-12 10:11:30 +01:00
Minkyu Kang
851db35e2d S5P: support generic watchdog timer
This patch adds support the generic watchdog timer for s5pc1xx and exynos4

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: HeungJun, Kim <riverful.kim@samsung.com>
2012-02-12 10:11:29 +01:00
Chander Kashyap
db68bc2c2d Exynos: Fix ARM Clock frequency calculation
Earliar ARM clock frequency was calculated by:
MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL.
It is fixed by calculating it as follows:
ARMCLK=MOUTCORE / (DIVCORE + 1) / (DIVCORE2 + 1)

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-02-12 10:11:28 +01:00
Jason Liu
0d8a749950 i.mx: i.mx5: update imx_get_mac_from_fuse function
FEC does not work on the i.mx51/53evk board, it will hangup
In:    serial
Out:   serial
Err:   serial
Net:

After bisect, it due to the following commit:
be252b6 net: imx: Add multi-FEC support for imx_get_mac_from_fuse
has change the imx_get_mac_from_fuse fucntion prototype, but fail
to update i.mx5, here it does it.

After apply this patch, u-boot works again on i.mx51/53 evk boards.

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-02-12 10:11:27 +01:00
Dechesne, Nicolas
f59021791b OMAP SPL: Fix missing timer_init() call in OMAP4 s_init()
In 8775471bb, the call to timer_init() was removed from common code
and put in OMAP3 s_init() function. As a result the boot was broken
on OMAP4. This patch adds timer_init() in OMAP4 s_init(), that fix
boot on all OMAP4 boards.

Signed-off-by: Nicolas Dechesne <n-dechesne@ti.com>
Tested-by: Robert P. J. Day <rpjday@crashcourse.ca>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <trini@ti.com>
2012-02-12 10:11:23 +01:00
Tom Rini
0ae056510f OMAP3: Correct get_sdr_cs_offset mask
The function get_sdr_cs_offset reads the CS_CFG register in the SDRC
to determine where CS1 is mapped to.  make_cs1_contiguous() will set
CS1 to follow after CS0.  The CS_CFG register has values in bits 9:8
and 3:0 but we had erroneously been testing 5:4 and 3:0 resulting in
incorrect offsets on platforms with less than 128MB as 3:0 describe
128MB hunks and 9:8 describe 32MB offsets after the 128MB hunk.

Tested-by: Grant Erickson <marathon96@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-02-12 10:11:23 +01:00
Pali Rohár
204705111c arm: omap3: Define save_boot_params in lowlevel_init.S for SPL only
Wrap the function save_boot_params with CONFIG_SPL_BUILD.  This will
allow non-SPL boards to define their own save_boot_params functions
in U-Boot itself.

Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
2012-02-12 10:11:22 +01:00
Simon Glass
bd29cb05f2 tegra2: Enable data cache
This enables the data cache on Tegra2 boards.

As discussed on the list, this is better off in the Tegra2 cpu code than in a
particular vendor directory. We should be safe turning on the cache for all
Tegra2 boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12 10:11:22 +01:00
Simon Glass
cf06b13903 tegra: Add SDMMC support to funcmux
This adds support for SDMMC ports to the funcmux. Only one
option is supported: FUNCMUXO_SDMMC_8BIT which selects an 8-bit
wide SDIO interface where available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12 10:11:22 +01:00
Simon Glass
8a1133c607 tegra: Add I2C support to funcmux
Add support to funcmux for selecting I2C functions and programming
the pinmux appropriately.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12 10:11:22 +01:00
Simon Glass
2faf1863de tegra: Add enum to select from available funcmux configs
We want to give a name to each available funcmux config. For now we just
use the pin group names (even through it is verbose) since there seems
to be nothing better.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12 10:11:22 +01:00
Simon Glass
d693969daa tegra: Adjust funcmux config test to permit expansion
We want to support config options other than zero, so move the test to the
end to allow intermediate code to OK such a config.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12 10:11:22 +01:00
Stephen Warren
9057e652c3 tegra2: Fix default RAM size selection in odmdata
A value of 0 in the odmdata RAM size field means default, which is 512MB
not 1GB. Fix this. For reference, see:

http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=blob;\
f=arch/arm/mach-tegra/odm_kit/query/harmony/tegra_devkit_custopt.h;\
h=1ec7010911454f19a5018952fd245785a62c59ad;\
hb=0e52d7fe25b11a656c376a37890be219470661fb

v2: New patch

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12 10:11:22 +01:00
Stephen Warren
4850ab9a4f tegra2: Fix conflicting pinmux for UARTA
Tegra appears to boot with function UARTA pre-selected on mux
group SDB. If two mux groups are both set to the same function,
it's unclear which group's pins drive the RX signals into the
HW module. For UARTA, SDB certainly overrides group IRTX in
practice. To solve this, configure some alternative function on
SDB to avoid the conflict. Also, tri-state the group to avoid
driving any signal onto it until we know what's connected.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12 10:11:22 +01:00
Patil, Rachna
b4116ede36 ARM: AM33XX: Add i2c support
Add i2c driver board hookup for AM335X EVM

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Patil, Rachna <rachna@ti.com>
2012-01-23 11:57:31 +01:00
Andreas Müller
761ca31e47 omap_rev_string: output to stdout
* avoid potential buffer overflows
* allow SPL-build not to output "Texas Instruments Revision detection unimplemented"

Signed-off-by: Andreas Müller <schnitzeltony@gmx.de>
Signed-off-by: Tom Rini <trini@ti.com>
2012-01-16 08:40:13 +01:00
Andreas Müller
8775471bb3 OMAP SPL: call timer_init in s_init to make udelay work earlier
Signed-off-by: Andreas Müller <schnitzeltony@gmx.de>
2012-01-16 08:40:12 +01:00
Chandan Nath
8a8f084e4f ARM:AM33XX: Add SPL support for AM335X EVM
This patch is added to support SPL feature on AM335X
platform. In this patch, MMC1 is configured as boot
device for SPL and support for other devices will be
added in the next patch series.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2012-01-16 08:40:12 +01:00
Chandan Nath
876bdd6d46 ARM:AM33XX: Add mmc/sd support
This patch add supports for mmc/sd driver on AM335X platform.
PLL and pinmux configurations for mmc/sd are configured in this
patch.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-01-16 08:40:12 +01:00
Chandan Nath
fb072a3ead ARM:AM33XX: Fix ddr and timer register offset
This patch is added to update incorrect ddr and timer
register offset.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-01-16 08:40:11 +01:00
Nikita Kiryanov
715462dd7e omap3: make get_board_rev() function weak
Current get_board_rev() function returns a hard coded value which is
obviously incorrect for the majority of boards.
Allow boards to provide a correct implementation by making this function
weak.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2012-01-16 08:40:11 +01:00
Aneesh V
fe7104b307 omap4: fix boot issue on ES2.0 Panda
Fix boot issue on ES2.0 Panda by tuning some
IO settings. The CONTROL_EFUSE_2 register has
to be over-ridden in software for 4430 boards.

Commit 23e9f0723e
wrongly did this for CONTROL_EFUSE_1. Reverting
this and doing it for CONTROL_EFUSE_2.

Signed-off-by: Aneesh V <aneesh@ti.com>
Tested-by: Raúl Porcel <armin76@gentoo.org>
2012-01-16 08:40:11 +01:00
Jason Liu
f2f7745825 imx: mx6q: add aipstz init for off platform periph
Init peripheral access control register of AIPSTZ OPACRx:

Buffer Writes(BW):      0 -> not bufferable,
Supervisor Protect(SP): 0 -> not require supervisor privilege level for accesses.
Write Protect(WP):      0 -> allows write accesses.
Trusted Protect(TP):    0 -> allows unstrusted master

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
2012-01-16 08:40:10 +01:00
Jason Liu
bd2e27c043 i.mx6:imx6q: allign MAC address with burned-in ordering
For the i.mx6q, the burned-in MAC address will be the following odering,

fuse: 0x620[7:0]   MAC_ADDR[7:0]     ---> mac[5]
fuse: 0x620[15:8]  MAC_ADDR[15:8]    ---> mac[4]
fuse: 0x620[23:16] MAC_ADDR[23:16]   ---> mac[3]
fuse: 0x620[31:24] MAC_ADDR[31:24]   ---> mac[2]
fuse: 0x630[7:0]   MAC_ADDR[39:32]   ---> mac[1]
fuse: 0x630[15:8]  MAC_ADDR[47:40]   ---> mac[0]

This patch also fix the error caculation for the fuse bank[0] address

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
2012-01-16 08:40:09 +01:00
Fabio Estevam
be252b654a net: imx: Add multi-FEC support for imx_get_mac_from_fuse
Add multi-FEC support for imx_get_mac_from_fuse by passing dev_id as a parameter.

This feature is important on mx28 SoC for example that has two FEC ports.

Cc: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-01-16 08:40:09 +01:00
Jason Liu
ff167df51c i.mx: i.mx6q: Add the enet clock function
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-01-16 08:40:08 +01:00
Joe Hershberger
365d607033 gpio: Replace ARM gpio.h with the common API in include/asm-generic
ARM boards should use the generic GPIO API
This means changing gpio to unsigned type
Remove the unused gpio_toggle() function which is not part of the API
Comment that free should not modify pin state

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>

fixed merge conflict in da8xx_gpio.c, tegra2_gpio.c, and
extended to the new mxs_gpio.c.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2012-01-09 20:10:32 -06:00
Simon Glass
bb6997f840 tegra: Add support for UART init in cpu board.c
We add a way of initialising the selected of UARTs prior to relocation.
Boards can use the board_init_uart_f() instead of repeating this code
themselves.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24 10:23:32 +01:00
Simon Glass
b5a5b35197 tegra: Add a function mux feature
funcmux permits selection of config options for particular peripherals,
such as the pins that are used for that peripheral, if there are several
options.

Add UART selection to start with.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24 10:23:32 +01:00
Simon Glass
8442fd3c6a tegra: add clock_ll_start_uart() to enable UART prior to reloc
Most boards will want to enable a UART early. This function provides
that feature in Tegra architecture code so the code does not need to be
copied on every board.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24 10:23:32 +01:00
Simon Glass
905ed41aad tegra: Move clock_early_init() to arch_cpu_init()
The clock init is not board specific, so move it into
the cpu code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24 10:23:32 +01:00
Simon Glass
ccdd6eaecb tegra: Move cpu_init_cp15() to arch_cpu_init()
This call is more of an architecture requirement than a board
one, so move it there.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24 10:23:32 +01:00
Thierry Reding
09743ba635 tegra2: Always build with USE_PRIVATE_LIBGCC=yes.
The AVP on Tegra2 doesn't boot properly when U-Boot is linked against
the GCC provided libgcc. To work around this, always build and link
against a private libgcc for Tegra2-based boards.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24 10:23:31 +01:00
Tom Warren
e2132c29d8 arm: Tegra: fix undefined instruction hang immediately after reset
commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't
execute on Tegra, due to the AVP (ARM7TDI) not having a CP15.
Result was an undefined instruction hang just after reset.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Aneesh V <aneesh@ti.com>
2011-12-21 20:36:22 +01:00
Wolfgang Grandegger
5d2947a3fc USB: MX5: add helper functions to enable USB clocks
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Jason Liu <r64343@freescale.com>

V2: Fix spacing in crm_regs.h
2011-12-11 14:49:25 +01:00
Jason Liu
23608e23fd i.mx: add the initial support for freescale i.MX6Q processor
i.MX6Q is freescale quad core processors with ARM cortex_a9 complex.
This patch is to add the initial support for this processor.

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>
2011-12-09 17:30:10 +01:00
Jason Liu
18936ee2ad i.mx: introduce the armv7/imx-common folder
In order to support the coming MX6 platform and to reducde
the duplicated code, we had better move some common files
or functions to the imx-common folder for sharing.

This patch does the following:
- move speed.c file from armv7/mx5/speed.c to armv7/imx-common/speed.c
- move armv7/mx5/timer.c to armv7/imx-common/timer.c, no any new feature
  added but just fix the checkpatch errors in the old file and remove
  the CONFIG_SYS_MX5_CLK32 reference in the file
- create one new file cpu.c file to store the common function with i.mx5/6

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-12-09 17:30:10 +01:00
Chander Kashyap
393cb36199 S5PC2XX: Rename S5pc2XX to exynos
As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15
based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15
based SoC's will be sub-classified as Exynos4 and Exynos5 respectively.

In order to better adapt and reuse code across various upcoming Samsung Exynos
based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in
this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix
are renamed as exynos4/EXYNOS4.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2011-12-09 17:30:09 +01:00
Simon Glass
7f8c070ff9 tegra2: Don't use board pointer before it is set up
In board_init_f() the gd->bd pointer is not valid when dram_init() is called.
This only avoids dying because DRAM is at zero on Tegra2. The common ARM
routine sets up the banks in the same way anyway, so we can just remove this
code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09 17:30:09 +01:00
Simon Glass
e81cdc0350 tegra2: Remove unneeded 'dynamic ram size' message
This message is not required, since it is followed by an 'official' U-Boot
message.

U-Boot 2011.03-00048-gd7cb0d3 (May 11 2011 - 17:17:23)

TEGRA2
Board: NVIDIA Seaboard
dynamic ram_size = 1073741824
DRAM:  1 GiB

becomes:

TEGRA2
Board: NVIDIA Seaboard
DRAM:  1 GiB

This is a separate commit since it changes behavior.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09 17:30:09 +01:00
Simon Glass
e75119d278 tegra2: Remove unneeded boot code
Since we have cache support built in we can remove Tegra's existing cache
initialization code amd other related dead code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09 17:30:09 +01:00
Simon Glass
80433c9ac6 arm: Move CP15 init out of cpu_init_crit()
Some SOCs have do not start up with their 'main' CPU. The first U-Boot
code may then be executed with a CPU which does not have a CP15, or not a
useful one.

Here we split the initialization of CP15 into a separate call, which can
be performed later if required.

Once the main CPU is running, you should call cpu_init_cp15() to perform
this init as early as possible.

Existing ARMv7 boards which define CONFIG_SKIP_LOWLEVEL_INIT should not
need to change, this CP15 init is still skipped in that case. The only
impact for these boards is that the cpu_init_cp15() will be available
even if it is never used on these boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09 17:30:09 +01:00
Simon Glass
210576fc5e tegra2: Simplify tegra_start() boot path
The Tegra2 boot path is more complicated than it needs to be. Since we want
to move to building most of U-Boot with ARMv7 and only a small part with
ARMv4T (for AVP) it should be as simple as possible.

This makes tegra2_start() into a simple function which either does AVP
init or A9 init depending on which core is running it. Both cores now
following the same init path, beginning at _start, and the special Tegra2
boot path code is no longer required.

Only two files need to be built for ARMv4T, and this is handled in the
Tegra2 CPU Makefile.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09 17:30:09 +01:00
Simon Glass
e43d6ed932 tegra2: Add arch_cpu_init() to fire up Cortex-A9
We want to move away from a special Tegra2 start-up, and just use
arch_cpu_init() instead. However, if we run board_init_f() from boot
we need to build it for ARMv4T, since the Tegra's AVP start-up CPU
does not support ARMv7.

The effect of this is to do the AVP init earlier, and in
arch_cpu_init(), rather that board_early_init_f().

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09 17:30:08 +01:00
Anatolij Gustschin
164a750789 arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix GCC 4.6 warnings
Fix:
clocks-common.c: In function 'setup_dplls':
clocks-common.c:256:6: warning: variable 'sysclk_ind' set but not used
[-Wunused-but-set-variable]
clocks-common.c: In function 'setup_non_essential_dplls':
clocks-common.c:292:6: warning: variable 'sysclk_ind' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:40 +01:00
Anatolij Gustschin
b0a86a27ee arch/arm/cpu/armv7/omap-common/spl.c: Fix GCC 4.2 warnings
Fix:
spl.c: In function 'jump_to_image_no_args':
spl.c:103: warning: assignment makes pointer from integer without a cast
spl.c:105: warning: dereferencing type-punned pointer will break
strict-aliasing rules

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:40 +01:00
Simon Glass
5acc907294 mx5: Correct a warning in clock.c
This corects the warning below, obtained with my gcc 4.6 compiler.

arch/arm/cpu/armv7/mx5/libmx5.o: In function `decode_pll':
arch/arm/cpu/armv7/mx5/clock.c:94: undefined reference to `__aeabi_uldivmod'

I am not able to test this on MX5x hardware, but it does improve the
MAKEALL output for me. You may already have a similar patch, but I cannot
see it on the list.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-12-06 23:59:39 +01:00
Tom Rini
ee08a8260a OMAP3: Add SPL_BOARD_INIT hook
Add an SPL_BOARD_INIT hook and for OMAP3 have it turn on i2c.  OMAP4
doesn't need i2c enabled in SPL.  Enable SPL_BOARD_INIT on devkit8000.

Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:39 +01:00
Tom Rini
4e647e1207 OMAP3 SPL: Add identify_nand_chip function
A number of boards are populated with a PoP chip for both DDR and NAND
memory.  Other boards may simply use this as an easy way to identify
board revs.  So we provide a function that can be called early to reset
the NAND chip and return the result of NAND_CMD_READID.  All of this
code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.

Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:38 +01:00
Tom Rini
9ae0d55074 OMAP3 SPL: Rework memory initalization and devkit8000 support
This changes to making the board be responsible for providing the
memory initialization timings in SPL and converts the devkit8000
to this framework.  In SPL we try and initialize both CS0 and CS1.

Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:38 +01:00
Tom Rini
3bd8437dcc OMAP3: Change mem_ok to clear again after reading back
It's possible to need to call this function on the same banks multiple
times so we want to be sure that 'pos A' is cleared out again at the
end.

Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:38 +01:00
Tom Rini
2a04e85870 OMAP3: Add a helper function to set timings in SDRC
Since we go through the sequence to setup the SDRC timings more than
once, break this logic out into its own function and have that function
call mem_ok() to make sure the memory is usable.

Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:38 +01:00
Tom Rini
5f862b7179 OMAP3: Update SDRC dram_init to always call make_cs1_contiguous()
We update the comment in make_cs1_contiguous() to be a little bit
more clear (it's been copy/pasted from other silicons) and then
explain in dram_init() why we need to always try this.

Note that in the previous behavior we were always calling this on
boards that never had cs1 populated anyhow so making sure we do
this always is fine and will correct things like omap3evm detecting
an invalid amount of memory (384MB).

Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:37 +01:00
Tom Rini
b7eb9e7895 omap3: mem: Comment enable_gpmc_cs_config more
Expand the "enable the config" comment to explain what the bit shifts
are and define out two of the magic numbers.

Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:37 +01:00
Ilya Yanok
b9e65a797b AM35xx: add EMAC support
AM35xx has DaVinci-compatible EMAC.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
2011-12-06 23:59:36 +01:00
Aneesh V
23e9f0723e omap4: fix IO setting
The value from TRIM is not working for some 4430 silicons.
So, override with hw team recommended value. However, for
4460 TRIM value shall be used as long as the part is trimmed

This fixes boot problem on some OMAP4430 ES2.0 Panda boards
out there.

Cc: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:34 +01:00
Aneesh V
9404758e9b omap4460: add ES1.1 identification
Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:34 +01:00
Aneesh V
4324c118a0 omap4: emif: fix error in driver
There was a typo in the EMIF driver. It went un-noticed
because it affected only when automatic detection is enabled
and even then half the memory was configured and identified
properly.

Reported-by: Rockefeller <rockefeller.lin@innocomm.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:34 +01:00
Aneesh V
473673a5c8 omap: remove I2C from SPL
Due to some recent changes I2C is no longer required in SPL.
Remove the i2c_init() call to save some space

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:34 +01:00
Aneesh V
cd5847ac3a omap4460: fix TPS initialization
TPS power IC is controlled using a GPIO (gpio_wk7).
This GPIO should be maintained at logic 1 always. As
such an internal pull-up on this pin will do the job,
driving the GPIO outuput is not needed. This will avoid
the need of using GPIO library in SPL and also may
save some power.

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:34 +01:00
Aneesh V
e4fce34e7a start.S: remove omap3 specific code from start.S
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Aneesh V <aneesh@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:34 +01:00
Aneesh V
a8c686399f armv7: setup vector
The vector is not correctly setup in armv7 except for OMAP3.
Correcting this.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:33 +01:00
Aneesh V
87d3da7b01 armv7: include armv7/cpu.c in SPL build
This allows SPL to have default implementation of
save_boot_params(), useful for SoCs that do
not intend to override this default implementation

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:33 +01:00
Aneesh V
dc7100f408 armv7: disable L2 cache in cleanup_before_linux()
We were not disabling external caches before jumping
to kernel. We were flushing all caches including
external caches and disabling caches globally in
CP15 System Control register. Apparently this is not
enough.

The bootstrap loader in Linux kernel that does decompression
enables data-caches again, flush them after use and disable
them before jumping to kernel proper. However, it's not aware
of the external caches.

Since we have left external cache enabled, external cache will
get used once caches are enabled globally, but it's not flushed
because decompressor is not aware of external caches. When it
jumps to kernel with caches disabled globally, we have stale
data in the external cache and a coherency problem.

This was breaking the boot for OMAP4 with latest mainline
kernel. The solution is to disable external caches in
cleanup_before_linux(). With this fix kernel is booting again.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:33 +01:00
Alexander Holler
86623add12 OMAP3: Use sdelay from arch/arm/cpu/armv7/syslib.c instead of cloning that.
There is no need to have such a function twice.

Signed-off-by: Alexander Holler <holler@ahsoftware.de>
Acked-by: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-11-29 15:43:38 +01:00
Anatolij Gustschin
7a1b07eef9 arch/arm/cpu/armv7/s5p-common/pwm.c: fix GCC 4.6 warning
Fix:
pwm.c: In function 'pwm_config':
pwm.c:85:16: warning: variable 'timer_rate_hz' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-11-16 21:37:01 +01:00
Sricharan
78f455c055 omap4/5: Add support for booting with CH.
Configuration header(CH) is 512 byte header attached to an OMAP
boot image that will help ROM code to initialize clocks, SDRAM
etc and copy U-Boot directly into SDRAM. CH can help us in
by-passing SPL and directly boot U-boot, hence it's an alternative
for SPL. However, we intend to support both CH and SPL for OMAP4/5.

Initialization done through CH is limited and is not equivalent
to that done by SPL. So U-Boot has to distinguish between the
two cases and handle them accordingly. This patch takes care
of doing this.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Sricharan
bb772a5944 omap5: emif: Add emif/ddr configurations required for omap5 evm
Add the emif configurations required for omap5 soc.Add the
correct ddr part configurations required for omap5 evm board.
EDB8164B3PH from ELPIDA is the part used on the board.

Also changes are done to retain some part of the code
common for OMAP4/5 and keep only the remaining in the Soc
specific directories.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Sricharan
2e5ba48928 omap5: clocks: Add clocks support for omap5 platform.
Adding the correct configurations required for
dplls, clocks, for omap5 Soc.

Also changes are done to retain some part of the code common
for OMAP4/5 and move only the remaining to the Soc specific
directories.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Sricharan
508a58fa8e omap5: Add minimal support for omap5430.
This patch adds the minimal support for OMAP5. The platform and machine
specific headers and sources updated for OMAP5430.

OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.

Also moved some part of code from the basic platform support that can be made
common for OMAP4/5. Rest is kept out seperately. The same approach is followed
for clocks and emif support in the subsequent patches.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Sricharan
ce170beeb7 omap4: make omap4 code common for future reuse
Much of omap4 soc support code can be reused for omap5.
Move them to the omap-common directory to facilitate
this.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Fabio Estevam
41c881c0ca mx53: Turn off child clocks before reconfigure perclk_root
In addition to ensuring that PERCLK remains at least 2.5 times slower
than the AHB clock, certain steps need to be followed to ensure robust
operation of PERCLK when reconfiguring the PERCLK clock source.

To properly configure the PERCLK clock source, the following steps are
required:

1.In the CCGR registers, gate the clocks to all PERCLK-dependent
  modules.
2.Select the desired input clock for the PERCLK root clock (to be either
  source from the peripherals main source clock or the
  lp_apm clock source). Refer to the CMCBR register,  perclk_lp_apm_sel bit.
3.Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers
  to the desired setting.  Refer to the CBCDR register for details.
4.In the CCGR registers, enable the desired clocks for the
  PERCLK-dependent module clocks.

If these steps aren't followed, GPT timer may stop and the kernel stops
at "Calibrating delay loop".

Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-11-04 22:06:37 +01:00
Ilya Yanok
b88befa550 omap/spl: actually enable the console
Currently OMAP SPL code does all the initialization but does not set the
gd->have_console value so no output is actually performed. This patch
sets gd->have_console to 1.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-03 22:56:23 +01:00
Wolfgang Denk
cca4e4aec1 Reduce build times
U-Boot Makefiles contain a number of tests for compiler features etc.
which so far are executed again and again.  On some architectures
(especially ARM) this results in a large number of calls to gcc.

This patch makes sure to run such tests only once, thus largely
reducing the number of "execve" system calls.

Example: number of "execve" system calls for building the "P2020DS"
(Power Architecture) and "qong" (ARM) boards, measured as:
	-> strace -f -e trace=execve -o /tmp/foo ./MAKEALL <board>
	-> grep execve /tmp/foo | wc -l

	Before: After:	Reduction:
==================================
P2020DS 20555	15205	-26%
qong	31692	14490	-54%

As a result, built times are significantly reduced, typically by
30...50%.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Albert Aribaud <albert.aribaud@free.fr>
cc: Graeme Russ <graeme.russ@gmail.com>
cc: Mike Frysinger <vapier@gentoo.org>
Tested-by: Graeme Russ <graeme.russ@gmail.com>
Tested-by: Matthias Weisser <weisserm@arcor.de>
Tested-by: Sanjeev Premi <premi@ti.com>
Tested-by: Simon Glass <sjg@chromium.org>
Tested-by: Macpaul Lin <macpaul@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-11-03 20:44:58 +01:00