SRICHARAN R cdd50a8d07 OMAP5: hwinit: Add the missing break statement ... The break statement is missing in init_omap_revision function, resulting in a wrong revision identification. So fixing this. Signed-off-by: R Sricharan <r.sricharan@ti.com>		2012-05-15 08:31:24 +02:00
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am33xx	ARM:OMAP+:MMC: Add parameters to MMC init	2012-05-15 08:31:22 +02:00
exynos	ARM: EXYNOS: Add support for Exynos5 based SoCs	2012-02-12 10:11:30 +01:00
highbank	ARM: highbank: add reset support	2012-03-28 23:31:23 +02:00
imx-common	mx6: Read silicon revision from register	2012-03-27 09:41:16 +02:00
mx5	mx53: Make PLL2 to be the parent of UART clock	2012-03-27 09:41:17 +02:00
mx6	i.MX6: implement enable_caches()	2012-04-16 14:53:58 +02:00
omap-common	OMAP5: palmas: Configure nominal opp vdd values	2012-05-15 08:31:23 +02:00
omap3	sdrc.c: Fix typo in do_sdrc_init() for SPL	2012-03-29 08:19:29 +02:00
omap4	OMAP5: palmas: Configure nominal opp vdd values	2012-05-15 08:31:23 +02:00
omap5	OMAP5: hwinit: Add the missing break statement	2012-05-15 08:31:24 +02:00
s5p-common	S5P: support generic watchdog timer	2012-02-12 10:11:29 +01:00
s5pc1xx	armv7: adapt s5pc1xx to the new cache maintenance framework	2011-07-04 10:55:25 +02:00
tegra2	tegra: Enhance clock support to handle 16-bit clock divisors	2012-03-29 08:12:50 +02:00
u8500	Timer: Remove set_timer completely	2011-07-26 14:52:17 +02:00
cache_v7.c	armv7: cache: remove flush on un-aligned invalidate	2011-09-04 11:36:16 +02:00
config.mk	ARM: add u-boot.imx as target for i.MX SOCs	2012-04-16 14:53:59 +02:00
cpu.c	Add cache functions to SPL for armv7	2012-03-27 22:05:29 +02:00
Makefile	Add cache functions to SPL for armv7	2012-03-27 22:05:29 +02:00
start.S	arm: Tegra: fix undefined instruction hang immediately after reset	2011-12-21 20:36:22 +01:00
syslib.c	ARMV7: Vexpress: fix build errors	2010-12-08 23:44:21 +01:00