Commit graph

514 commits

Author SHA1 Message Date
Kever Yang
2738181eb9 rockchip: rk3399: use common TPL board file
Use common tpl.c instead of rk3399-board-tpl.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
682a99c634 rockchip: rk3399: remove TPL_BOARD_INIT
RK3399 TPL do not need a dedicate board init, print the firmware
info when debug init instead.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
87ac550862 rockchip: rk3399: use common secure_timer_init() for spl/tpl
SPL/TPL share the same secure_timer_init(), update to use
one copy source code and update to use CONFIG_ROCKCHIP_STIMER_BASE
as base address and rename to function name to rockchip_stimer_init().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
82560cb311 rockchip: rk3368: use common TPL board file
Use common tpl.c instead of rk3368-board-tpl.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
3338f544b1 rockchip: rk3288: use common TPL board file
Use Common tpl.c instead of rk3288-board-tpl.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
6ae28a30e9 rockchip: rk322x: use common TPL board file
Use Common tpl.c instead of rk322x-board-tpl.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
18f85080eb rockchip: add common tpl board file
Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
common board is a basic TPL board init which can be shared for most
of SoCs to avoid copy-pase for different SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
192445b39c rockchip: rk3368: enable stimer for rk3368
Add stimer_init() for spl/tpl so that we able to switch
to use arch timer.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
1f6b599b6d rockchip: rk3368: move sgrf init to spl as arch_cpu_init()
The SoC related init will move to SPL and keep TPL clean,
so that we can reuse the common TPL board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
0845a0ee66 rockchip: remove rk_timer
We have convert all SoC to use DM timer or ARM arch/generic
timer, we can remove this rk_timer now.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
243f48b803 rockchip: remove no use header file in board code
The timer.h is no use any more, remove it from the board files.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
1e72a757bb rockchip: rk3128: use ARM arch timer instead of rk_timer
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track to boot time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
ae5a3659f3 rockchip: rk3288: use ARM arch timer instead of rk_timer
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track to boot time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
002d897fb1 rockchip: rk3036: use ARM arch timer instead of rk_timer
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track the boot time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
19d0de3ee4 rockchip: rk3036: sdram: use udelay instead of rockchip_udelay
Use system api for udelay instead of vendor defined api,
and rockchip_udelay() will be removed.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
acea123825 rockchip: rk322x: use ARM arch timer instead of rk_timer
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track to boot time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
b39ab7f1e1 rockchip: rk3288: dts: enable spl-boot-order
We share the same default SPL boot order for all rk3288 boards,
use dts instead of hard code in board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
032906a858 rockchip: spl-boot-order: update dependency to OF_LIBFDT
The fdt interfaces are actuall depends on OF_LIBFDT instead
of OF_CONTROL, some boards may enable OF_CONTROL while disable
OF_LIBFDT.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
ccdcdbb507 rockchip: rk3288: enable TPL for evb-rk3288
Enable TPL for evb-rk3288 so that we can have a free size limited
SPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
443fe40e8b rockchip: rk3288: add default TPL_LDSCRIPT value in Kconfig
We share the same TPL_LDSCRIPT for all rk3288 board, add
default value in Kconfig.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
25c6173099 rockchip: rk3288: move configure_l2ctlr back to rk3288
The configure_l2ctlr() is used only by rk3288, do not need to
locate in sys_proto.h

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
ccab9e7ee3 rockchip: rk3288: add arch_cpu_init in spl
Add arch_cpu_init() in SPL for soc related init, and
move configure_l2ctlr() into it.
The arch_cpu_init() only need to run once, so no need
to run in TPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
d7f2d23ce4 rockchip: rk3368: default enable SPL LIBCOMMON and LIBGENERIC
We needs SPL LIBCOMMON and LIBGENERIC for all boards,
so we can enable them by default and no need to define
in each board.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
1cdb614845 rockchip: rk322x: default enable SPL LIBCOMMON and LIBGENERIC
We needs SPL LIBCOMMON and LIBGENERIC for all boards,
so we can enable them by default and no need to define
in each board.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
747e127535 rockchip: rk3328: default enable SPL LIBCOMMON and LIBGENERIC
We needs SPL LIBCOMMON and LIBGENERIC for all boards,
so we can enable them by default and no need to define
in each board.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
a13f870ad4 rockchip: rk3399: default enable SPL LIBCOMMON and LIBGENERIC
We needs SPL LIBCOMMON and LIBGENERIC for all boards,
so we can enable them by default and no need to define
in each board.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
8ef62a4aab rockchip: rk3368: use defaule value for SYS_MALLOC_F_LEN
There is no difference in rk3368 board use for SYS_MALLOC_F_LEN,
so we can use default value.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
cb32a91fbf rockchip: rk3328: use defaule value for SYS_MALLOC_F_LEN
There is no difference in rk3328 board use for SYS_MALLOC_F_LEN,
so we can use default value.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
d0ae3bc4d6 rockchip: rk3399: use default value for SYS_MALLOC_F_LEN
There is no difference in rk3399 board use for SYS_MALLOC_F_LEN,
so we can use default value.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
9489b5c7ba rockchip: rk3288: use default value for SYS_MALLOC_F_LEN
There is no difference in rk3288 board use for SYS_MALLOC_F_LEN,
so we can use default value.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
e3d83d8e54 rockchip: rk322x: use defconfig for SYS_MALLOC_F_LEN
There is no difference in rk322x board use for SYS_MALLOC_F_LEN,
so we can use default value.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
476dcb6b43 rockchip: Kconfig: move ROCKCHIP_BOOT_MODE_REG to soc Kconfig
Rockchip SoCs have different ROCKCHIP_BOOT_MODE_REG value,
move it to SoC's own Kconfig, and add address for rk3128 and
rk3328 so that all SoCs have available address.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
c83b5a2c53 rockchip: Kconfig: move rk3399 config into its Kconfig
Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
97fd39c69e rockchip: Kconfig: move rk3368 config into its Kconfig
Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
5959126771 rockchip: Kconfig: move rk3288 config into its Kconfig
Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
45c1d34157 rockchip: Kconfig: move rk322x config into its Kconfig
Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
5e283876f1 rockchip: fixup board choice in Kconfig
Kconfig for board target select is choice option, fixup for
rk3036, rk3288 and rv1108.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
c8851c9d18 rockchip: remove redundant pinctrl header including
No code is using this header file, remove it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
0e9802095d rockchip: rk3288: remove pinctrl init in spl_board_init
The pinctrl will default init the io while driver is probe
with new pinctrl driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
fcb1964a5e rockchip: rk3188: remove pinctrl init in spl_board_init
The pinctrl will default init the io while driver is probe
with new pinctrl driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
7958a85bca rockchip: rk3399: remove pinctrl init in spl_board_init
The pinctrl will default init the io while driver is probe
with new pinctrl driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
845a31ea2c rockchip: rk3399: syscon: Add pmu support
Add pmu compatible with relevant U_BOOT_DRIVER for rk3399
via syscon rk3399 driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21 00:00:17 +08:00
Andy Yan
619f002db8 rockchip: make_fit_atf.py: fix loadables property set error
Commit b238e4b00c ("rockchip: Cleanup of make_fit_atf.py.") set
firmware = "atf_1";
loadables = "uboot","atf_1","atf_2";

Actually it should be:
firmware = "atf_1";
loadables = "uboot","atf_2","atf_3";

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-05 15:57:52 +08:00
Kever Yang
665ebcadd6 rockchip: rk3288: enable TPL for tinker-board
All the config for TPL has been update, we can enable the TPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-02 11:49:49 +08:00
Kever Yang
45290847df rockchip: rk3288: add separate TPL STACK address
TPL is at SRAM while other stage is at SDRAM, so it needs
separate STACK.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-02 11:49:49 +08:00
Kever Yang
d18ca747b6 rockchip: rk3288: enable TPL configs to chip level
More boards other than vyasa needs TPL, so enable the TPL configs
at chip level instead of board level.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-02 11:49:49 +08:00
Jagan Teki
4977cf67de rockchip: rk3399: Enable TPL_BOARD_INIT
Enable TPL_BOARD_INIT, this would help us to show
TPL boot prints.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26 21:11:29 +08:00
Jagan Teki
97d98e6bbf rockchip: rk3399: tpl: Mark printascii into debug
Now, we have spl_board_init which has TPL banner prints.

So mark the 'U-Boot TPL board init' print into debug.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26 21:11:29 +08:00
Jagan Teki
c997c0fc28 rockchip: rk3399: tpl: Add spl_board_init
Add spl_board_init for TPL, that have TPL banner will help
to print tpl boot prints.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26 21:11:28 +08:00
Jagan Teki
adde32d033 rockchip: rk3399: Enable SPL_BOARD_INIT
Enable SPL_BOARD_INIT globally to rk3399, this would
help to print the SPL banner during bootup.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26 21:11:28 +08:00
Jagan Teki
5e7216462b rockchip: rk3399: spl: Mark printascii into debug
Now, we have spl_board_init with preloader_console_init that
indeed show SPL banner.

So mark the 'U-Boot SPL board init' print into debug.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26 21:11:28 +08:00
Jagan Teki
07586ee432 rockchip: rk3399: Support common spl_board_init
Support common spl_board_init by moving code from puma
board file into, common rk3399-board-spl.c.

Part of the code has sysreset-gpio, regulators_enable_boot_on
but right now only puma board is using this with relevant
config options rest remains common for all targets.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26 21:11:28 +08:00
Jagan Teki
96070460c3 rockchip: rk3399: Get bl31.elf via BL31
Right now rockchip platform need to copy bl31.elf into u-boot
source directory to make use of building u-boot.itb.

So, add environment variable BL31 like Allwinner SoC so-that the
bl31.elf would available via BL31.

If the builds are not exporting BL31 env, the make_fit_atf.py
explicitly create dummy bl31.elf in u-boot root directory to
satisfy travis builds and it will show the warning on console as

 WARNING: BL31 file bl31.elf NOT found, resulting binary is non-functional
 WARNING: Please read Building section in doc/README.rockchip

Note, that the dummy bl31 files were created during not exporting
BL31 case would be removed via clean target in Makefile.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-26 21:11:27 +08:00
Kever Yang
c009aeb8ca rockchip: Kconfig: enable SPL support for rk3328
Enable SPL support and some related option in Kconfig.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from 430b01462b with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
2019-06-26 21:11:26 +08:00
Kever Yang
661519e5c5 rockchip: rk3328: add SPL board file support
rk3328 SPL is locate at dram, so do not have strict size limit,
suppose to enable storage media controller driver, load ATF and
U-Boot, then boot into ATF.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from 4ebe3968b6 with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-26 21:11:26 +08:00
Heinrich Schuchardt
6a853dbcc0 lib: time: export usec_to_tick()
In the UEFI Stall() boottime service we need access to usec_to_tick().

Export the function.

Remove redundant implementation in arch/arm/mach-rockchip/rk_timer.c.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-06-04 22:09:26 +02:00
Christoph Muellner
b238e4b00c rockchip: Cleanup of make_fit_atf.py.
This patch cleans up make_fit_atf.py in the following way:

* Fix all issues reported by pylint
* Move copyright notice from file-to-generate to script
* Fix of-by-one bugs in loadables property
* Remove commented-out (dead) code.

Besides the bugfix no intended changes.

Tested on RK3399-Q7 with TF-A v2.1 as BL31.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-30 18:22:35 +08:00
Christoph Muellner
78a1ac33cb rockchip: rk3399: Add option to print on UART3.
The RK3399 SPL does not use a pinctrl driver to setup the UART pins.
Instead it works based on config macros, which set the base address
of the actual UART block.

Currently the RK3399 SPL support UART0 and UART2.
This patch adds UART3 in the same way as UART0.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-30 18:22:35 +08:00
Trevor Woerner
1001502545 CONFIG_SPL_SYS_[DI]CACHE_OFF: add
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.

Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-05-18 08:15:35 -04:00
Jagan Teki
2666bd42c6 arm: rockchip: rk3399: Move common configs in Kconfig
Few SPL and U-Boot proper configs are common to all rk3399 target
defconfigs, move them and select it from platform kconfig.

Moved configs:
-  SPL_ATF
-  SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
-  SPL_LOAD_FIT
-  SPL_CLK if SPL
-  SPL_PINCTRL if SPL
-  SPL_RAM if SPL
-  SPL_REGMAP if SPL
-  SPL_SYSCON if SPL
-  CLK
-  FIT
-  PINCTRL
-  RAM
-  REGMAP
-  SYSCON
-  DM_PMIC
-  DM_REGULATOR_FIXED

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
Kever Yang
6bbf5e1a94 rockchip: rk3399: add tpl support
Rockchip platform suppose to use TPL(run in SRAM) as dram init and
SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be
limited by SRAM size.
This patch add rk3399-board-tpl.c and its common configs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
3cbec0ad09 rockchip: add u-boot-tpl-v8.lds
We don't have both sram and sdram in TPL, so update from:
arch/arm/cpu/armv8/u-boot-spl.lds

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-08 17:34:12 +08:00
Kever Yang
6459e7f588 rockchip: rk3368: remove uart iomux init in SPL
The iomux should have been set in board_debug_uart_init(),
do not set in board_init_f(), remove it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
579a168466 rockchip: rk3368: support UART2/4 in board_debug_uart_init()
evb-rk3368 is using UART2 and PX5 evb is using UART4

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
c34643e0db rockchip: rk322x: add tpl support
Move original spl to tpl, and add spl to load next stage firmware,
adapt all the address and option for them.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Philipp Tomsich
dd320e122f rockchip: rk3288: include header for back_to_bootrom
To avoid a warning, we need to include the header defining
back_to_bootrom for us.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:59 +02:00
Philipp Tomsich
8c5805a210 rockchip: rk3399: include gpio.h
After applying the series for debug_uart_init(), Travis-CI reports:

arch/arm/mach-rockchip/rk3399/rk3399.c:90:2: error: implicit declaration of function 'spl_gpio_set_pull' [-Werror=implicit-function-declaration]
  spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
  ^~~~~~~~~~~~~~~~~

This is caused by a missing header-file include.  Fix it.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:59 +02:00
Kever Yang
c79bce16e5 rockchip: rk3399: add board_debug_uart_init()
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file for all rockchip SoCs later.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:59 +02:00
Kever Yang
f9e8145614 rockchip: rk3399: use grf structure to access reg
Prefer to use structure to access register if we could.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
6a03335714 rockchip: rk3368: move board_debug_uart_init() to rk3368.c
Move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file later for all rockchip SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
e83e885e53 rockchip: rk3288: add board_debug_uart_init()
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file for all rockchip SoCs later.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
070e48b30e rockchip: rk3288: use grf structure to access soc_con2
Prefer to use structure to access register if we can.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
28fe4d5b30 rockchip: rk322x: move board_debug_uart_init() to rk322x.c
Move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file later for all rockchip SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed up header-list to not break FASTBOOT:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
86d0eca451 rockchip: rk3188: add board_debug_uart_init()
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
7f3eec03d5 rockchip: rk3036: add board_debug_uart_init()
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed whitespace error:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
b0a569da08 rockchip: enable DEBUG_UART_BOARD_INIT by default
All Rockchip SoCs use DEBUG_UART_BOARD_INIT to init per board
UART IOMUX, enable it by default.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:06 +02:00
Kever Yang
b1b449bf1f rockchip: correct ARCH_SOC name
The ARCH_SOC name default as 'rockchip' and we put all the
header file in 'arch/arm/include/asm/arch-rockchip/', but
the 'rockchip' is not the SOC name, let's correct it after
we update all the source file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsiich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Kever Yang
15f09a1a83 rockchip: use 'arch-rockchip' as header file path
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common
header file path, so that we can get the correct path directly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Urja Rannikko
59ef021b99 rk3288-board: remove pinctrl call for debug uart
This failed and caused a boot failure on c201, and afaik
the pins should be setup by the new pinctrl driver.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Philipp Tomsich
a2893baa47 Revert "rockchip: Drop call to rockchip_dnl_mode_check() for now"
Due to a final resolution not coming up in time for 2019.04 and
following the consensus on the discussion, we'll keep this around
for 2019.04 after all.

This reverts commit 0d968ceb1f.
2019-03-29 09:21:13 +01:00
Philipp Tomsich
73ced87e9a rockchip: rk3399: spl: ensure that debug_uart_init is called
With the latest changes to add support for the Chromebook Bob,
initialisation through debug_uart_init() did no longer get called for
other targets.

Fix this, by moving debug_uart_init() out of the Bob-specific

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:14 +01:00
Simon Glass
9e92116bc8 rockchip: Add support for chromebook_bob
Bob is a 10-inch chromebook produced by Asus. It has two USB 3.0 type-C
ports, 4GB of SDRAM, WiFi and a 1280x800 display. It uses its USB ports
for both power and external display. It includes a Chrome OS EC
(Cortex-M3) to provide access to the keyboard and battery functions.

Support so far includes only:
- UART
- SDRAM
- MMC, SD card
- Cros EC (but not keyboard)

Not included:
- Keyboard
- Display
- Sound
- USB
- TPM

Bob is quite similar to Kevin, the Samsung Chromebook Plus, but support
for this is not provided in this series.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
c35f8e5017 rockchip: Tidy up board include-file ordering
These board files have inconsistent #include ordering. Fix them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
3523c07867 rockchip: Allow booting from SPI
The u-boot,spl-boot-device property only allows MMC at present. Add SPI as
well for boards that boot from SPI flash.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
David Wu
08c817c399 ARM: rockchip: Remove the pinctrl request at rk3288-board-spl
If we use the new pinctrl driver, the pinctrl setup will be done
by device probe. Remove the pinctrl setup at rk3288-board-spl.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
David Wu
bfb11abef2 ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188
It seems that pinctrl is not requested for rk3188 SPL, remove it so
that can save more space for SPL image size.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
David Wu
c0b163e908 ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug message.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
Marty E. Plummer
8e2e601c5f rockchip: add support for veyron-speedy (ASUS Chromebook C201)
This adds support for the ASUS C201, a RK3288-based clamshell
device. The device tree comes from linus's linux tree at
3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
are for 4GB Samsung LPDDR3, decoded from coreboot's
src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc

Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Simon Glass
0d968ceb1f rockchip: Drop call to rockchip_dnl_mode_check() for now
This function causes a 5-second delay and stops the display working on
minnie. This code should be in a driver and should only be enabled by
a device-tree property, so that it does not affect devices which do not
have this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Tom Rini
2f41ade79e linker: Modify linker scripts to be more generic
Make use of "IMAGE_MAX_SIZE" and "IMAGE_TEXT_BASE" rather than
CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE.  This lets us re-use the
same script for both SPL and TPL.  Add logic to scripts/Makefile.spl to
pass in the right value when preprocessing the script.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Adam Ford <aford173@gmail.com> #da850evm & omap3_logic_somlv
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-26 22:55:53 -05:00
Tom Rini
b32ba6f12e rockchip: Add TPL_MAX_SIZE for RK3288
Per Kever Yang, 32768 is a reasonable max size for TPL on RK3288.

Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-01-26 22:55:53 -05:00
Kever Yang
7ff025561d rockchip: rk3036: ram: update license
All the source code of sdram_rk3036.c are from Rockchip, update the
copyright to owned by Rockchip.

Because rockchip may use this copy of code both for open source
project and internal project, update the license to use both
GPL2.0+ and BSD-3 Clause.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-02 22:36:46 +01:00
Kever Yang
3119ecc4ac rockchip: sdram-common: fix wrong size for 4GB in 32bit SoC
This is workaround for issue we can't get correct size for 4GB ram
in 32bit system and available before we really need ram space
out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
The size of 4GB is '0x1 00000000', and this value will be truncated
to 0 in 32bit system, and system can not get correct ram size.
Rockchip SoCs reserve a blob of space for peripheral near 4GB,
and we are now setting SDRAM_MAX_SIZE as max available space for
ram in 4GB, so we can use this directly to workaround the issue.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-By: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2019-01-02 21:15:59 +01:00
Otavio Salvador
e11ef3d26e ARM: rockchip: Add rv1108-elgin-r1 board support
Add the initial support for Elgin R1 board, which is based on the
RV1108 SoC and has the following features currently supported in
U-Boot:

- UART
- eMMC
- USB

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-16 01:30:11 +01:00
Manivannan Sadhasivam
1bad5e1492 rockchip: rk3399: Add common Rock960 family from Vamrs
Rock960 is a family of boards based on Rockchip RK3399 SoC from Vamrs.
It consists of Rock960 (Consumer Edition) and Ficus (Enterprise Edition)
96Boards.

Below are some of the key differences between both Rock960 and Ficus
boards:

1. Different host enable GPIO for USB
2. Different power and reset GPIO for PCI-E
3. No Ethernet port on Rock960

The common board support will be utilized by both boards. The device
tree has been organized in such a way that only the properties which
differ between both boards are placed in the board specific dts and
the reset of the nodes are placed in common dtsi file.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[Added instructions for SD card boot]
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2018-12-06 16:04:49 +01:00
Kever Yang
17e5f3a426 rockchip: rk3188: use board_debug_uart_init() for UART io init
Sync with other rockchip SoCs, use board_debug_uart_init() to
init default UART iomux.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 22:00:11 +01:00
Otavio Salvador
303cbd2141 ARM: rockchip: rv1108: Add a board_usb_init for USB OTG
Like it is done for other Rockchip SoCs, introduce a board_usb_init()
function so that USB OTG can be functional on rv1108 too.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 21:56:44 +01:00
Philipp Tomsich
adbca53a3a rockchip: rk3399: spl: always report errors triggering a hard stop
The RK3399 SPL has two cases that may end in a hard-stop: if either
the pinctrl can not be initialised or if the DRAM fails to initialise.
Both have previously not triggered an error message unless DEBUG was
defined (i.e. both used debug() to print the error).

This converts both error messages to be printed using pr_err() to
ensure that some output points to the cause of the hard-stop.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 19:03:16 +01:00
Heiko Stuebner
6c69ed19f9 rockchip: rk3188: fix early uart setup
Commit 7a6d7d3e12 ("rockchip: pinctrl: rk3188: Move the iomux definitions
into pinctrl-driver") moved the iomux settings out of the grf header
to prevent conflicts with the iomux definitions of other rockchip socs.

This also breaks the early uart setup, as the iomux for uart2 are needed.
To fix that just put the tiny amount of needed iomux definitions next to
the early uart code.

Fixes: 7a6d7d3e12 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 19:03:16 +01:00
Heiko Stuebner
5b5ca4c0d4 rockchip: rk3188: add support for usb-uart functionality
Rockchip socs can route the debug uart pins through the d+ and d- pins
of one specific usbphy per soc. Add a config option and implement the
setting on the rk3188.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed up to mark grf as maybe unused:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 19:03:16 +01:00
Mian Yousaf Kaukab
7009eae890 rockchip: make_fit_atf: make python3 compatible
Make script python3 compatible. No functional changes intended.

Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04 21:15:46 +02:00
Mian Yousaf Kaukab
e4011e8daa rockchip: make_fit_atf: use elf entry point
make_fit_atf.py uses physical address of first segment as the
entry point to bl31. It is incorrect and causes following abort
when bl31_entry() is called:

U-Boot SPL board initTrying to boot from MMC1
"Synchronous Abort" handler, esr 0x02000000
elr: 0000000000000000 lr : 00000000ff8c7e8c
x 0: 00000000ff8e0000 x 1: 0000000000000000
x 2: 0000000000000000 x 3: 00000000ff8e0180
x 4: 0000000000000000 x 5: 0000000000000000
x 6: 0000000000000030 x 7: 00000000ff8e0188
x 8: 00000000000001e0 x 9: 0000000000000000
x10: 000000000007fcdc x11: 00000000002881b8
x12: 00000000000001a2 x13: 0000000000000198
x14: 000000000007fdcc x15: 00000000002881b8
x16: 00000000003c0724 x17: 00000000003c0718
x18: 000000000007fe80 x19: 00000000ff8e0000
x20: 0000000000200000 x21: 00000000ff8e0000
x22: 0000000000000000 x23: 000000000007fe30
x24: 00000000ff8d1c3c x25: 00000000ff8d5000
x26: 00000000deadbeef x27: 00000000000004a0
x28: 000000000000009c x29: 000000000007fd90

Fix it by using the entry point from the elf header.

Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04 21:15:46 +02:00
Kever Yang
aabb51da59 rockchip: add fit source file for pack itb with op-tee
We package U-Boot and OP-TEE into one itb file for SPL,
so that we can support OP-TEE in SPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04 21:15:46 +02:00
Kever Yang
f00273a3a3 rockchip: make_fit_atf: fix warning unit_address_vs_reg
Patch fix warning:
/builddir/BUILD/u-boot-2018.05-rc2/"arch/arm/mach-rockchip/make_fit_atf.py" \
arch/arm/dts/rk3399-firefly.dtb > u-boot.its
  ./tools/mkimage  -f u-boot.its -E u-boot.itb >/dev/null  && cat
/dev/null
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/uboot@1
has a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@1 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@2 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@3 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/fdt@1 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node
/configurations/config@1 has a unit name, but no reg property
make[1]: Leaving directory
'/builddir/BUILD/u-boot-2018.05-rc2/builds/firefly-rk3399'

Reported-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04 21:15:46 +02:00
Jean-Jacques Hiblot
7ec9181d6a dm: convert device_get_global_by_of_offset() to device_get_global_by_ofnode()
Also add device_find_global_by_ofnode() that also find a device based on
the OF node, but doesn't probe the device.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-08-21 16:21:37 +02:00
Michal Simek
58008cbab5 Kconfig: Sort bool, default, select and imply options
Another round of sorting Kconfig entries aplhabetically.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30 07:18:48 -04:00
Carlo Caione
315ded9730 rockchip: veyron: Set vcc33_sd regulator value
On the veyron board the vcc33_sd regulator is used as vmmc-supply for
the SD card. This regulator is powered in the MMC core during power on
but its value is never actually set.

In the veyron platform the reset value for the LDO output is 1.8V while
the standard (min and max) value for this regulator defined in the DTS
is 3.3V. When the MMC core enable the regulator without setting its
value, the output is automatically set to 1.8V instead of 3.3V.

With this patch we preemptively set the value to 3.3V.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-21 01:55:27 +02:00
Carlo Caione
389167c3c4 rk3288: Disable JTAG function from sdmmc0 IO
The GRF_SOC_CON0.grf_force_jtag bit is automatically set at boot and it
is preventing the SDMMC to work correctly. Disable the JTAG function on
the assumption that a working SD has higher priority over JTAG.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-21 01:55:27 +02:00
Carlo Caione
0d4d5fd73c rk3288: veyron: Init boot-on regulators
Use regulators_enable_boot_on() to init all the regulators with
regulator-boot-on property.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-21 01:55:27 +02:00
Heinrich Schuchardt
9125947687 rockchip: rk3399: spl: add missing \n to output
Without the patch SPL (in case of an error) creates an output like:

	U-Boot SPL board initMissing DTB

The patch adds the missing line feed. So now we get:

	U-Boot SPL board init
	Missing DTB

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-21 01:55:26 +02:00
Philipp Tomsich
e5f2ecc750 rockchip: rk3399: inject 'u-boot, spl-boot-device' for next-stage
This implements the new 'spl_perform_fixups' hook for RK3399-based
boards and injects the /chosen/u-boot,spl-boot-device with an ofpath
corresponding to the boot device used.

The intended usage is for the full U-Boot stage to evaluate this in
scripts and then adapt its boot-order when using distro-boot.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-07-21 01:55:26 +02:00
Alexander Kochetkov
706afa46c7 rockchip: rk3188: add rk_board_late_init() hook
All other rockchip boards have rk_board_late_init() hook,
so add it to rk3188 boards also.

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-21 01:55:25 +02:00
Alex Kiernan
8a65bd6372 fastboot: Rename fb_set_reboot_flag to fastboot_set_reboot_flag
Rename fb_set_reboot_flag to fastboot_set_reboot_flag so it matches
all other fastboot code in the global name space. Fix the guards around
them so that they're dependent on FASTBOOT, not just USB_FUNCTION_FASTBOOT.

Move the weak implementation of fastboot_set_reboot_flag to fb_common.c
so we can call it from non-USB fastboot code.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-05-30 11:59:21 +02:00
Lokesh Vutla
acf1500138 arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A
Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under
armv7 folder. This led to a misconception of creating separate folders
for armv7m and armv7r. There is no reason to create separate folder for
other armv7 based architectures when it can co-exist with few Kconfig
symbols.

As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later
separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and
can co exist in the same folder.

Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Suggested-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-05-07 15:53:24 -04:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Tom Rini
d024236e5a Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:48 -04:00
Kever Yang
c3c0331db1 rockchip: enable SYS_NS16550 for all SoCs by default
All rockchip SoCs can use ns16550 driver, enable it for all
and set SYS_NS16550_MEM32 for all SoCs.

Version-changes: 2
- use imply instead of select

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:07 +02:00
Kever Yang
cb7116afe8 rockchip: rk322x: update MACRO for back-to-brom
The MACRO has been update after:
ee14d29 rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL
We need to update the C code for it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:07 +02:00
Patrick Uiterwijk
ced3c10fd2 arm: rockchip: make_fit_atf: remove unneeded imports
These imports are entirely unused in the entire script.

Signed-off-by: Patrick Uiterwijk <patrick@puiterwijk.org>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:06 +02:00
Kever Yang
fd9e0fe0e3 rockchip: rk3188: use DM timer instead of rk_timer
Disable rk_timer as SYS timer and use DM timer instead,
so that we can get a better timer framework, the rk_timer
is going to be clean after we conver to use DM timer or
ARM arch/generic timer.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:06 +02:00
Jagan Teki
33554fcec9 rockchip: rk3288: Fix wrong TPL_TEXT_BASE
TPL offset 0xff704004 is unaligned address which is adding nearest
8-bytes for next instruction, So  0xff704004 is adding 0x20 for
proper alignment which is causing the next instruction data
0xefffffff is moved.

Hexdump with overlaped bytes:
-----------------------------
0000000 0000 0000 0000 0000 0000 0000 0000 0000
0000010 0000 0000 0000 0000 0000 0000 ffff eaff

So, Fix the TEXT_BASE for proper aligned address 0xff704000

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-02-24 18:47:23 +01:00
Jagan Teki
849f672bdb rockchip: rk3288: Add TPL_LDSCRIPT
Due to size limitations in SPL by adding falcon mode,
rk3288 support TPL. In order to not overlap SPL_TEXT_BASE
add TPL_TEXT_BASE with u-boot-tpl.lds that intern call
u-boot-spl.lds with proper TEXT_BASE values.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-02-24 18:47:22 +01:00
Lukasz Majewski
d695d66278 spl: eMMC/SD: Provide one __weak spl_boot_mode() function
The goal of this patch is to clean up the code related to choosing SPL
MMC boot mode.

The spl_boot_mode() now is called only in spl_mmc_load_image() function,
which is only compiled in if CONFIG_SPL_MMC_SUPPORT is enabled.

To achieve the goal, all per mach/arch implementations eligible for
unification has been replaced with one __weak implementation.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Michal Simek <michal.simek@xilinx.com> (For ZynqMP)
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-02-07 22:06:18 -05:00
Eddie Cai
451dcf5cd0 rockchip: rk3036: enable rockusb support on rk3036 based device
Rockchip Rockusb driver already merged. So we enable rockusb
support on rk3036 based device.

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28 17:12:39 +01:00
David Wu
424324d3ca rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver
Clean the iomux definitions at grf_rk322x.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
After that, define the uart2 iomux at rk322x-board file.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28 17:12:38 +01:00
Eddie Cai
c3d098e762 rockchip: rk3288: enable rockusb support on rk3288 based device
this patch enable rockusb support on rk3288 based device.

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-10 11:11:06 +01:00
Kever Yang
cbe503793a rockchip: add a common script for generate fit its
Rockchip release bl31.elf file for armv8 SoCs like rk3399, rk3328,
the elf have more than one section, we need to decode it first and
packed them into u-boot.itb with its file. This script is to generate
the its script.
Need default bl31.elf in root directory of U-Boot source and dtb
as parameter.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-12-18 17:18:02 +01:00
Kever Yang
8a8106f066 rockchip: update ROCKCHIP_SPL_RESERVE_IRAM to 0
Only rk3399 atf need ROCKCHIP_SPL_RESERVE_IRAM. This commit updates
its default setting to 0 so that other SoCs do not need to define it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-12-18 16:56:17 +01:00
Kever Yang
fd1f80aab6 rockchip: rk3036: sdram: correct setting for pll integer mode
According to rk3036 TRM, should be set to '1' for the pll
integer mode, while the '0' means the frac mode.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:27 +01:00
Kever Yang
731cafecc5 rockchip: rk3036: update clock driver for ddr
After the MASK MACRO update, we need to update the driver at the same time.
This is a fix to:
37943aa rockchip: rk3036: clean mask definition for cru reg

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:27 +01:00
Kever Yang
faa75ad9e6 rockchip: rk3036: fix pll config for correct frequency
There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy,
so we need to double to pll output and then ddr can work
in correct frequency.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:27 +01:00
Kever Yang
6074cfaa8e rockchip: rk3128: add evb-rk3128 support
evb-rk3128 is an evb from Rockchip based on rk3128 SoC:
- 2 USB2.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:27 +01:00
Kever Yang
9246d9e541 rockchip: rk3128: add clock driver
Add rk3128 clock driver and cru structure definition.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:26 +01:00
Kever Yang
daeed1dbb5 rockchip: rk3128: add soc basic support
RK3128 is a SoC from Rockchip with quad-core Cortex-A7 CPU
and mali400 GPU. Support Nand flash, eMMC, SD card, USB 2.0 host
and device, HDMI/LVDS/MIPI display.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:26 +01:00
Philipp Tomsich
f07d76c00d rockchip: fix turning off boot-mode via Kconfig
The ROCKCHIP_BOOT_MODE_REG option defaults to a hex value, so 0 will
show as 0x0 if a default is provided and changed via Kconfig.
However, it still will show as 0, if no default is given.

Consequently, the "is set to something other than 0" test in a
Makefile is cumbersome.  Instead this check can easily be performed in
the C-code.

This removes the ifeq-check from mach-rockchip/Makefile, adds a
matching #if-check to boot_mode.c and fixes resulting link issues (if
boot_mode.o was not included due to the Makefile check) by defining a
stub function (in case the functionality is not built in) for
setup_boot_mode in boot_mode.c.

Fixes: e306779 (rockchip: make boot_mode related codes reused across all platforms)
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-26 14:57:11 +01:00
Andy Yan
ecb103bf68 rockchip: check download key before bootup
Enter download mode if the download key pressed.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Converted printfs in boot_mode.c to debug/pr_err:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:24 +01:00
Andy Yan
b4d23f7643 rockchip: add support for enter to bootrom download mode
Rockchip bootrom will enter download mode if it returns from
spl/tpl with a non-zero value and couldn't find a valid image
in the backup partition.
This patch provide a method to instruct the system to back to
bootrom download mode by checking the BROM_DOWNLOAD_FLAG register.
As the bootrom download function relys on some modules such as
interrupts, so we need to back to bootrom as early as possbile
before the tpl/spl code override the interrupt configurations.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:23 +01:00
Andy Yan
e3067793c3 rockchip: make boot_mode related codes reused across all platforms
setup_boot_mode function use the same logic but different
mode register address across all the rockchip platforms,
so it's better to make this function reused across all the
platforms, and let the mode register address setting from
the config file.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:23 +01:00
Philipp Tomsich
4bbb05bcb5 rockchip: rk3188: move CONFIG_SPL_* entries from rk3188_common.h to Kconfig
There still are a few CONFIG_SPL_* options selected using defines from
rk3188_common.h instead of via Kconfig.  This migrates those over to
Kconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:23 +01:00
Philipp Tomsich
b82bd1f8d4 rockchip: back-to-bootrom: allow passing a cmd to the bootrom
The BROM supports forcing it to enter download-mode, if an appropriate
result/cmd-word is returned to it.  There already is a series to
support this in review, so this prepares the (newly C-version) of the
back-to-bootrom code to accept a cmd to passed on to the BROM.

All the existing call-sites are adjusted to match the changed function
signature.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21 23:57:22 +01:00
Philipp Tomsich
4d9253fb76 rockchip: rk3188: use boot0 hook to load up SPL in 2 steps
For the RK3188, the BROM will attempt to load up the first stage
image (SPL for the RK3188) in two steps: first 1KB to offset 0x800
in the SRAM and then the remainder to offset 0xc00 in the SRAM.
It always enters at 0x804, though.

With this changeset, the RK3188 boot removes the TPL (stub) stage and
builds a single SPL binary that utilizes the early back-to-bootrom via
the boot0-hook.

Consequently, the passing of the saved boot params via pmu->os_reg[2]
is also removed.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:22 +01:00
Philipp Tomsich
ecfd71891a rockchip: back-to-bootrom: replace assembly-implementation with C-code
The back-to-bootrom implementation for Rockchip has always relied on
the stack-pointer being valid on entry, so there was little reason to
have this as an assembly implementation.

This provides a new C-only implementation of save_boot_params and
back_to_bootrom (relying on setjmp/longjmp) and removes the older
assembly-only implementation.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21 23:57:22 +01:00
Philipp Tomsich
b377d22264 rockchip: boot0 hook: support early return for RK3188/RK3066-style BROM
Some Rockchip BROM versions (e.g. the RK3188 and RK3066) first read 1KB data
from NAND into SRAM and executes it. Then, following a return to bootrom, the
BROM loads additional code to SRAM (not overwriting the first block read) and
reenters at the same address as the first time.

To support booting either a TPL (on the RK3066) or SPL (on the RK3188) using
this model of having to count entries, this commit adds code to the boot0
hook to track the number of entries and handle them accordingly.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-11-21 23:57:22 +01:00
Philipp Tomsich
14ad6eb264 rockchip: enable boot0-hook for all Rockchip SoCs
Rockchip SoCs bootrom design is like this:
- First 2KB or 4KB internal memory is for bootrom stack and heap;
- Then the first 4-byte suppose to be a TAG like 'RK33';
- The the following memory address end with '0004' is the first
  instruction load and running by bootrom;

Let's use the boot0 hook to reserve the first 4-byte tag for all
the Rockchip SoCs.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Commit message taken from an older patch by:]
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-11-21 23:57:21 +01:00
Kever Yang
36de37f5ca rockchip: rk3328: fix rockchip_get_cru api
The API for get priv pointer is wrong, fix it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-01 11:21:32 +01:00
Masahiro Yamada
9b643e312d treewide: replace with error() with pr_err()
U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// <smpl>
@@@@
-error
+pr_err
 (...)
// </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-04 11:59:44 -04:00
Jagan Teki
2ee3021ae1 rk3288: spl: Add dram_init_banksize
Falcon mode, is updating DDR dt node configuration through
spl_fixup_fdt() so add appropriate DDR base and size through
dram_init_banksize.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:35 +02:00
Philipp Tomsich
c55addd360 rockchip: spl: rk3399: implement chip-specific board_spl_was_booted_from()
To support the new "same-as-spl" specifier in the boot-order on the
RK3399, this implements the chip-specific mapping from the information
obtainable from the BROM to a OF path name.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:34 +02:00
Philipp Tomsich
80e9f88e67 rockchip: spl: support a 'same-as-spl'-specifier in the spl-boot-order
It is often desirable to configure the spl-boot-order (i.e. the order
that SPL probes devices to find the FIT image containing a full U-Boot)
such that it contains 'the same device the SPL stage was booted from'
early on.  To support this, we introduce the 'same-as-spl' specifier
for the spl-boot-order property.

This commit adds:
 - documentation for the new board_spl_was_booted_from() function that
   individual SoCs/boards should provide, if they can determine where
   the SPL was booted from
 - implements the new board_spl_was_booted_from() stub function
 - adds support for handling the 'same-as-spl' specifier and calling
   into the per-SoC/per-board support code.

This also updates the documentation for the 'u-boot,spl-boot-order'
property.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:34 +02:00
Philipp Tomsich
dbad01cab5 rockchip: spl: add documentation for spl_node_to_boot_device()
In the expectation that the spl-boot-order code will eventually
gain use outside of mach-rockchip: let's add documentation on the
spl_node_to_boot_device() function, which is likely to become a
publicly exported function.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:34 +02:00
Philipp Tomsich
fb7406469c rockchip: rk3399: make spl_board_init board-specific
The later-stage spl_board_init (as opposed to board_init_f) should set
up board-specific details: these differ between the EVB-RK3399 and the
RK3399-Q7 (Puma).

This moves spl_board_init back into the individual boards and removes
the unneeded functionality from Puma.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:34 +02:00
Kever Yang
4a18729726 rockchip: rk322x: update the sysreg number for boot mode
The boot mode for rk322x is stored in sysreg 0, update it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:34 +02:00
Jagan Teki
532cb7f5ad rk3288: vyasa: Add TPL support
Since the size of SPL can't be exceeded 0x8000 bytes in RK3288,
it is not possible add new SPL features like Falcon mode or etc.

So add TPL stage so-that adding new features to SPL is possible.
- TPL: DRAM init, clocks
- SPL: MMC, falcon, etc

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:33 +02:00
Jagan Teki
a982d5156d armv7: rk3288: Move configure_l2ctlr to common
configure_l2ctlr will be shared between SPL and TPL so
move them into asm/arch/sys_proto.h

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:33 +02:00
Jagan Teki
d9a7dcf5b8 armv7: Move L2CTLR read/write to common
L2CTLR read/write functions are common to armv7 so, move
them in to include/asm/armv7.h and use them where ever it need.

Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Backed out the change to arch/arm/mach-tegra/cache.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:33 +02:00
Philipp Tomsich
cbe18f10e6 rockchip: rk3399: spl: convert to using BOOT_DEVICE_BOOTROM
Instead of directly calling into the back-to-bootrom code, the RK3399
common SPL implementation now uses BOOT_DEVICE_BOOTROM to trigger a
transfer back into the bootrom.

With this factored out, the spl_board_init function can not be
customised for each RK3399 board.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:32 +02:00
Kever Yang
f0768491db rockchip: rk3328: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Kever Yang
c9eb7bca4b rockchip: rk3288: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Kever Yang
5b67d7010b rockchip: rk3188: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Kever Yang
b5934cf67c rockchip: rk3399: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Kever Yang
6e5bd8d6f3 rockchip: ram: rk3399: update reg map for of-platdata
After Simon's patch, the dtoc can work with 64bit address,
so we need to fix reg number for it.
Depend on Simon's patch set:
https://patchwork.ozlabs.org/cover/807266/

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:38 +02:00
Jagan Teki
d55af074e5 rk3288: Add Vyasa initial board support
This patch adds support for Vyasa RK3288 initial board
from Amarula Solutions.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:36 +02:00
Philipp Tomsich
ba1657338b rockchip: rk3399: spl: remove hard-coded addresses for GRF and SGRF
On the RK3399, we will have either OF_PLATDATA or full OF_CONTROL
enabled: this allows the use of syscon to retrieve the addresses of
GRF and SGRF (except for the early debug UART setup, which runs so
early that the device-model is not initialised).

This removes the hard-coded addresses and goes through syscon to
retrieve the base-addresses of GRF and SGRF. After that, we use
the structure definitions to locate the respective registers.

In addition to this, the inclusion of header files is also cleaned up:
- all headers are included at the beginning (there was a spurious
  inclusion of the grf header from within a function)
- all #include statements for unused headers are removed
- the remaining #include statements are sorted (while keeping common.h
  included in front)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:36 +02:00
David Wu
4c94aacd62 rockchip: rk322x: Disable integrated macphy for saving power consuming
Unfortunately, the integrated macphy default is enabled, which will
increase power consuming, if we do not use this PHY. So let's disable
it at first, which will save power consuming. If we really use it, then
enable it in driver level.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:33 +02:00
Kever Yang
c964a0dcae rockchip: rk322x: enable fastboot to set boot mode tag
To support fastboot "fastboot reboot-bootloader" cmd.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:32 +02:00
Kever Yang
e1f6881367 rockchip: rk3328: fix syscon id table
syscon id table need a dummy member as NULL ending, or else system
will panic while try to match a compatible in this table as a list.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-08 11:44:51 +02:00
Wadim Egorov
40d4f79b81 rockchip: rk3288: Add reset reason detection
Sometimes it's helpful to know the reset reason caused in the SoC.
Add reset reason detection for the RK3288 SoC.
This will set an environment variable which represents the reset reason.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05 11:04:35 +02:00
Kever Yang
44c5ba557b rockchip: rk322x: update dram bank size
The DRAM start address is not 0, so need to update the last bank size
as:
DRAM start addr + DRAM_SIZE - last bank start addr

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-18 16:55:25 +02:00
Philipp Tomsich
a299a4879e rockchip: rk3399: spl: remove unused header inclusion
fdtdec.h is included, but not used in rk3399-board-spl.c: remove the
'#include'-statement.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 16:55:15 +02:00
Simon Glass
382bee57f1 env: Rename setenv() to env_set()
We are now using an env_ prefix for environment functions. Rename setenv()
for consistency. Also add function comments in common.h.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:22:18 -04:00
Kever Yang
18d38d3a94 rockchip: rk322x: set the DDR region as non-secure in SPL
Disable the ddr secure region setting in SPL and the ddr memory
becomes non-secure, every one can access it. the trust firmware
like OPTEE should have the correct setting for it after SPL if
there is one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:15:08 +02:00
Philipp Tomsich
e8f9ad94bf rockchip: rk3368: spl: move SPL_LDSCRIPT to Kconfig
With the new way of doing things (i.e. the hierarchical selection of
SPL_LDSCRIPT via Kconfig) in place, this moves the SPL_LDSCRIPT setting
for the RK3368 from defconfig back into Kconfig.

With this done, there should be no lingering cases of SPL_LDSCRIPT
outside of Kconfig files.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:15:08 +02:00
Philipp Tomsich
96b9082c64 rockchip: rk3188: rock: adjust for SPL/TPL split
With the changes to split SPL/TPL for the RK3368, I apparently missed
some needed adjustments to the RK3188 Kconfig and rock_defconfig.

This fixes build-issues for the rock board after applying the RK3368
enablement (and SPL/TPL) set that resulted from TPL_SERIAL_SUPPORT,
TPL_ROCKCHIP_BACK_TO_BROM and TPL_TINY_MEMSET being separate symbols
now.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:37 +02:00
Philipp Tomsich
3159a6fc39 rockchip: rk3368: remove setup of secure timer from TPL/SPL
When using DM timers w/ the timer0 block within the RK3368, we no
longer depend on the ARMv8 generic timer counting.  This allows us to
drop the secure timer initialisation from the TPL and SPL stages.

The secure timer will later be set up by ATF, which starts the ARMv8
generic timer.  Thus, there will be a dependency from Linux to the ATF
through the ARMv8 generic timer... this seems reasonable, as Linux
will require the ATF (and PSCI) to start up the secondary cores anyway
(in other words: we don't add any new dependencies).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:36 +02:00
Philipp Tomsich
5aa49af311 moveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE
We can finally drop TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE off the
whitelist (this time it's really happening!) and migrate the setting
(only used on the RK3368-uQ7 so far) into Kconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:35 +02:00
Philipp Tomsich
4cf4378ed0 rockchip: rk3368: mark TPL as not inheriting its stack, text-base and size from SPL
The RK3368 needs to have a different base-address and stack-pointer
for its TPL stage.  Now that we want to do this via Kconfig, we need
to tick the appropriate 'TPL_NEEDS_...' boxes.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:35 +02:00
Philipp Tomsich
d9d1242b82 rockchip: Kconfig: preset TPL_LDSCRIPT via Kconfig for the RK3368
Set TPL_LDSCRIPT in Kconfig, so we don't have to pollute our
header file.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
4d02d20605 rockchip: board: lion-rk3368: add support for the RK3368-uQ7
The RK3368-uQ7 (codenamed 'Lion') is a micro-Qseven (40mm x 70mm,
MXM-230 edge connector compatible with the Qseven specification)
form-factor system-on-module based on the octo-core Rockchip RK3368.
It is designed, supported and manufactured by Theobroma Systems.

It provides the following features:
 - 8x Cortex-A53 (in 2 clusters of 4 cores each)
 - (on-module) up to 4GB of DDR3 memory
 - (on-module) SPI-NOR flash
 - (on-module) eMMC
 - Gigabit Ethernet (with an on-module KSZ9031 PHY)
 - USB
 - HDMI
 - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
 - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
5071457e44 rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368
With SPL and TPL support for the RK3368 in place, mark SPL and TPL as
supported from Kconfig for the RK3368.  As this is primarily tested on
the RK3368-uQ7, we'll leave it to board's individual defconfig to
enable.

Also enable DEBUG_UART_BOARD_INIT for the RK3368, so we get output
during the early boot-up, as we turn on TPL and SPL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
fbbd38001f rockchip: rk3368: spl: add SPL support
Adds SPL support for the RK3368 (assuming that our TPL stage has
initialised DRAM and set up the memory firewall).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
9b0bc59366 rockchip: spl: make spl-boot-order code reusable (split from rk3399)
In order to reuse the support for the u-boot,spl-boot-order property
from the rk3399, we split it into a reusable module that can be
included by the SPL code for any of our boards.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
a55e497156 rockchip: rk3368: spl: add TPL support
This adds the TPL support for the RK3368, including the u-boot-tpl.lds.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:33 +02:00
Philipp Tomsich
403e9cbcd5 rockchip: rk3368: add DRAM controller driver with DRAM initialisation
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).

At this stage, only the following feature-set is supported:
 - DDR3
 - 32-bit configuration (i.e. fully populated)
 - dual-rank (i.e. no auto-detection of ranks)
 - DDR3-1600K speed-bin

This driver expects to run from a TPL stage that will later return to
the RK3368 BROM.  It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).

Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).

The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block.  This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:33 +02:00
Philipp Tomsich
832567d5aa rockchip: Makefile: streamline SPL/TPL configuration
Handling TPL and SPL in the Makefile for mach-rockchip was based on
nested if checks and/or if-else-if paths.  This can be simplified and
made more readable by using $(SPL_TPL_) and by introducing
intermediate variables for the aggregation of SPL and TPL features.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:33 +02:00
Philipp Tomsich
81bd0ad07c rockchip: rk3368: syscon: SGRF support for OF_PLATDATA
In TPL we will need to configure security in the SGRF of the RK3368.
This change adds support for the SGRF as a syscon device, so we can
retrieve its address range through the syscon API in TPL (and can
avoid having to hard-code the address).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
66a63fec81 rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATA
The RK3368 has both a limited TPL size (just 0x7000 bytes) and the
added challenge of booting in AArch64, which increases the code size
for TPL (particularily when using the LP64 programming model).  For
this reason we expect the RK3368 to always use OF_PLATDATA for its
TPL stage.

This change adds support for the MSCH, PMUGRF and GRF register regions
in syscon, which are necessary for initialising the RK3368's DRAM
controller.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
9a8f009f24 rockchip: rk3368: improve Kconfig text for the RK3368
The RK3368 option in Kconfig referred to the RK3328 (copy-and-paste)
and had a few typos and unnecessarily used UTF-8 characters.  While
fixing this, I also reformatted and further clarified the text
(e.g. made the grouping into a a big and little cluster of 4 cores
each explicit).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
9e27c816a8 rockchip: Makefile: allow selective inclusion of sdram_common.o from TPL/SPL/U-Boot
The utility functions in sdram_common.c will be useful both for some
SPL implementations (and if unused, the linked will discard these
anyway) and for the full U-Boot stage.

This changes selects sdram_common.o through the $(SPL_TPL_) macro to
allow better control of its inclusion through the CONFIG_ROM,
CONFIG_SPL_RAM or CONFIG_TPL_RAM options.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
19b68fb280 rockchip: back-to-bootrom: simplify the #ifdef-check for LIBCOMMON in TPL/SPL
With the finer-grained control over LIBCOMMON_SUPPORT for TPL/SPL (i.e.
with the newly introduced distinction between TPL_LIBCOMMON_SUPPORT and
SPL_LIBCOMMON_SUPPORT), we can simplify the #ifdef-check to simply use
CONFIG_IS_ENABELD.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up to use 'puts' and LIBCOMMON:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:19 +02:00
Philipp Tomsich
ee14d29db0 rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL
The back-to-bootrom option is rather unfortunately named
  CONFIG_ROCKCHIP_SPL_BACK_TO_BOOTROM
instead of
  CONFIG_SPL_ROCKCHIP_BACK_TO_BOOTROM

To make is selectable through CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BOOTROM),
we need to rename it.  At the same time, we introduce a TPL_ variant of
the option to give us finer-grained control over when it should be used.

This change is motivated by our RK3368 boot process, which returns to
the boot ROM only from the TPL stage, but not from the SPL stage.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[added fix-up for evb-rk3229_defconfig and phycore-rk3288_defconfig:]
[fixed inverted CONFIG_IS_ENABLED test for rk3288:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

include/configs/rock.h: undef
2017-08-13 17:12:19 +02:00
Philipp Tomsich
36979c7e56 rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64
The back-to-bootrom support for Rockchip is equivalent to an
(assembly) implementation of setjmp/longjmp (i.e. it saves the
stack-pointer, link-register and callee-saved registers). Up until
now, this had only been implemented for AArch32 (i.e. ARMv7 or older),
which puts the new ARMv8 devices (which boot in AArch64 mode) at a
slight disadvantage.

To allow use of the 'back-to-bootrom' feature on new devices (e.g. the
RK3368), this commit adds an implementation for AArch64.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:19 +02:00
Andy Yan
77c17f4354 rockchip: use puts instead of printf when back to bootrom
printf will increase the code size more than 1kb, but platform
like rk3036 has no enough space for it.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
d26bfa73ed rockchip: enable SPL_LIBGENERIC for rk3036 based boards
function board_init_f_init_reserve will call memset, which
is implemented in lib, and enabled by CONFIG_SPL_LIBGENERIC_SUPPORT
in spl stage.
To reduce the code size, also enable SPL_TINY_MEMSET.
As rk3036 will return to bootrom immediately after dram
initialization, there is no need to run DM, so disable
SPL_DM_SERIAL.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Philipp Tomsich
c0508e427f rockchip: rk3399: enable SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT via Kconfig
SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT were previously
enabled through rk3399_common.h.  This change implies these options
through Kconfig.

These need to always be active for the RK3399, as follows:
 - SPL_SERIAL_SUPPORT is needed to pass the SPL build
 - SPL_DRIVERS_MISC_SUPPORT is needed to pass the SPL build

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
cb91173a7f rockchip: timer: make register sizes explicit
We are about to reuse the rockchip timer (header file) for 64bit ARMv8
chips, so it seems a good time to make the register sizes explicit by
changing from 'unsigned int' to 'u32'.

Reorders the header-includes in rk_timer.c to ensure that 'u32' is
definded before it is used by 'asm/arch/timer.h'.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:00 +02:00
Wadim Egorov
bafcf2db41 rockchip: Add basic support for phyCORE-RK3288 SoM based carrier board
The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC.
The module can be connected to different carrier boards.
It can be also equipped with different RAM, SPI flash and eMMC variants.
The Rapid Development Kit option is using the following setup:

  - 1 GB DDR3 RAM (2 Banks)
  - 1x 4 KB EEPROM
  - DP83867 Gigabit Ethernet PHY
  - 16 MB SPI Flash
  - 4 GB eMMC Flash

Add basic support for the PCM-947 carrier board, a RK3288 based development
board made by PHYTEC. This board works in a combination with
the phyCORE-RK3288 System on Module.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Kever Yang
64a524b08a rockchip: rk3036: sync os_reg2 define with other soc
Rockchip using the same bit definition for dram info and write
to os_reg, the col and bw info is not correct and let's fix it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:48 +02:00
Kever Yang
b24a8ec15c rockchip: add evb_rk3229 board
evb_rk3229 is a RK3229 based board, with:
- 8GB eMMC;
- 1GB DDR SDRAM;
- 2 USB2.0 HOST port;
- 1 MAC port;
- 1 HDMI port;
- IR;
- WiFi;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
168eef7ada rockchip: rk322x: add basic soc support
Enable soc support for SPL and U-boot skeleton.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
975e4abad2 rockchip: correct the bank0 ram size
The bank0 ram size should be the DRAM size minus reserved size,
the DRAM size may be 1GB, 2GB, 4GB, we can not hard code it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Added DECLARE_GLOBAL_DATA_PTR for RK3328, RK3368 and RK3399:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00