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rockchip: correct the bank0 ram size
The bank0 ram size should be the DRAM size minus reserved size, the DRAM size may be 1GB, 2GB, 4GB, we can not hard code it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Added DECLARE_GLOBAL_DATA_PTR for RK3328, RK3368 and RK3399: Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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c541a7a12a
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975e4abad2
9 changed files with 39 additions and 52 deletions
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@ -9,6 +9,8 @@
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct mm_region rk3328_mem_map[] = {
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{
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.virt = 0x0UL,
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@ -31,6 +33,17 @@ static struct mm_region rk3328_mem_map[] = {
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struct mm_region *mem_map = rk3328_mem_map;
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int dram_init_banksize(void)
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{
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size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
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/* Reserve 0x200000 for ATF bl31 */
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gd->bd->bi_dram[0].start = 0x200000;
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gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
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return 0;
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}
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int arch_cpu_init(void)
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{
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/* We do some SoC one time setting here. */
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@ -13,6 +13,8 @@
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#include <asm/arch/grf_rk3368.h>
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#include <syscon.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define IMEM_BASE 0xFF8C0000
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/* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */
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@ -50,6 +52,17 @@ static struct mm_region rk3368_mem_map[] = {
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struct mm_region *mem_map = rk3368_mem_map;
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int dram_init_banksize(void)
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{
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size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
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/* Reserve 0x200000 for ATF bl31 */
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gd->bd->bi_dram[0].start = 0x200000;
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gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
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return 0;
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}
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#ifdef CONFIG_ARCH_EARLY_INIT_R
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static int mcu_init(void)
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{
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@ -9,6 +9,8 @@
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GRF_EMMCCORE_CON11 0xff77f02c
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static struct mm_region rk3399_mem_map[] = {
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@ -33,6 +35,17 @@ static struct mm_region rk3399_mem_map[] = {
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struct mm_region *mem_map = rk3399_mem_map;
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int dram_init_banksize(void)
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{
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size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
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/* Reserve 0x200000 for ATF bl31 */
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gd->bd->bi_dram[0].start = 0x200000;
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gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
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return 0;
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}
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int arch_cpu_init(void)
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{
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/* We do some SoC one time setting here. */
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@ -12,11 +12,3 @@ int board_init(void)
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{
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = 0;
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gd->bd->bi_dram[0].size = 0x80000000;
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return 0;
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}
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@ -33,12 +33,3 @@ int board_init(void)
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{
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return 0;
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}
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int dram_init_banksize(void)
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{
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/* Reserve 0x200000 for ATF bl31 */
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gd->bd->bi_dram[0].start = 0x200000;
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gd->bd->bi_dram[0].size = 0x3fe00000;
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return 0;
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}
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@ -16,15 +16,6 @@ int board_init(void)
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return 0;
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}
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int dram_init_banksize(void)
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{
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/* Reserve 0x200000 for ATF bl31 */
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gd->bd->bi_dram[0].start = 0x200000;
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gd->bd->bi_dram[0].size = 0x7e000000;
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return 0;
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}
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int board_usb_init(int index, enum usb_init_type init)
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{
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return 0;
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@ -67,12 +67,3 @@ int board_init(void)
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out:
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return 0;
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}
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int dram_init_banksize(void)
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{
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/* Reserve 0x200000 for ATF bl31 */
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gd->bd->bi_dram[0].start = 0x200000;
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gd->bd->bi_dram[0].size = 0x7e000000;
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return 0;
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}
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@ -20,11 +20,3 @@ int board_init(void)
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{
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = 0x200000;
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gd->bd->bi_dram[0].size = 0x7fe00000;
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return 0;
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}
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@ -180,12 +180,3 @@ void get_board_serial(struct tag_serialnr *serialnr)
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serialnr->low = (u32)(serial & 0xffffffff);
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}
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#endif
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int dram_init_banksize(void)
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{
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/* Reserve 0x200000 for ATF bl31 */
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gd->bd->bi_dram[0].start = 0x200000;
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gd->bd->bi_dram[0].size = 0x7e000000;
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return 0;
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}
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