Commit graph

291 commits

Author SHA1 Message Date
Andrew Klossner
dc4b0b38d4 Fix printf errors.
The compiler will help find mismatches between printf formats and
arguments if you let it.  This patch adds the necessary attributes to
declarations in include/common.h, then begins to correct the resulting
compiler warnings.  Some of these were bugs, e.g., "$d" instead of
"%d" and incorrect arguments.  Others were just annoying, like
int-long mismatches on a system where both are 32 bits.  It's worth
fixing the annoying errors to catch the real ones.

Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com>
2008-07-09 23:55:46 +02:00
Wolfgang Denk
9692cab76f Merge branch 'master' of git://www.denx.de/git/u-boot-net 2008-07-09 23:22:54 +02:00
Ben Warren
dd35479a50 Add mechanisms for CPU and board-specific Ethernet initialization
This patch is the first step in cleaning up net/eth.c, by moving Ethernet
initialization to CPU or board-specific code.  Initial implementation is
only on the Freescale TSEC controller, but others will be added soon.

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-07-06 00:20:59 -07:00
Wolfgang Denk
e093a24762 Coding Style Cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-06-28 23:34:37 +02:00
Anatolij Gustschin
96026d42fa Fix 4xx build issue
Building for 4xx doesn't work since commit 4dbdb768:

In file included from 4xx_pcie.c:28:
include/asm/processor.h:971: error: expected ')' before 'ver'
make[1]: *** [4xx_pcie.o] Error 1

This patch fixes the problem.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-19 22:48:45 +02:00
Kumar Gala
859a86a25c 85xx/86xx: Move to dynamic mgmt of LAWs
With the new LAW interface (set_next_law) we can move to letting the
system allocate which LAWs are used for what purpose.  This makes life
a bit easier going forward with the new DDR code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-11 01:52:23 -05:00
Kumar Gala
f060054dad FSL LAW: Keep track of LAW allocations
Make it so we keep track of which LAWs have allocated and provide
a function (set_next_law) which can allocate a LAW for us if one is
free.

In the future we will move to doing more "dynamic" LAW allocation
since the majority of users dont really care about what LAW number
they are at.

Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-06-11 01:50:53 -05:00
Sergei Poselenov
740280e68c Added the upmconfig() function for 85xx.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-06-11 00:29:29 -05:00
Wolfgang Grandegger
6beecfbb54 MPC85xx: Beautify boot output of L2 cache configuration
The boot output is now aligned poperly with other boot output
lines, e.g.:

  FLASH: 128 MB
  L2:    512 KB enabled

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
2008-06-10 18:22:26 -05:00
Kumar Gala
730b2fcf6f 85xx: Add setting of cache props in the device tree.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-10 18:22:25 -05:00
Kumar Gala
4dbdb7681e 85xx: expose cpu identification
The current cpu identification code is used just to return the name
of the processor at boot.  There are some other locations that the name
is useful (device tree setup).  Expose the functionality to other bits
of code.

Also, drop the 'E' suffix and add it on by looking at the SVR version
when we print this out.  This is mainly to allow the most flexible use
of the name.  The device tree code tends to not care about the 'E' suffix.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-10 18:22:25 -05:00
Kumar Gala
ee1e35bede 85xx: Only use PORPLLSR[DDR_Ratio] on platforms that define it
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-09 13:31:20 -05:00
Becky Bruce
3b9519fc50 MPC85xx: Change traps.c to not reference non-addressable memory
Currently, END_OF_RAM is used by the trap code to determine if
we should attempt to access the stack pointer or not. However,
on systems with a lot of RAM, only a subset of the RAM is
guaranteed to be mapped in and accessible.  Change END_OF_RAM
to use get_effective_memsize() instead of using the raw ram
size out of the bd.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-09 13:31:20 -05:00
Wolfgang Denk
0ad4770f8e Merge branch 'socrates' of /home/wd/git/u-boot/projects 2008-05-21 01:13:52 +02:00
Wolfgang Denk
53677ef18e Big white-space cleanup.
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-21 00:14:08 +02:00
Sergei Poselenov
793670c3c0 Fixed reset for socrates
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-05-20 23:27:50 +02:00
Kumar Gala
70a0f81412 85xx: Add -mno-spe to e500/85xx builds
Newer gcc's might be configured to enable autovectorization by default.
If we happen to build with one of those compilers we will get SPE
instructions in random code.

-mno-spe disables the compiler for automatically generating SPE
instructions without our knowledge.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-29 20:08:43 +02:00
Kumar Gala
45239cf415 85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docs
All the 85xx and 86xx UM describe the register as timing_cfg_3
not as ext_refrec.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-29 11:44:29 -05:00
Kumar Gala
cf6cc01427 85xx: Additional fixes and cleanup of MP code
* adjust __spin_table alignment to match ePAPR v0.94 spec
* loop over all cpus when determing who is up.  This fixes an issue if
  the "boot cpu" isn't core0.  The "boot cpu" will already be in the
  cpu_up_mask so there is no harm
* Added some protection in the code to ensure proper behavior.  These
  changes are explicitly needed but don't hurt:
  - Added eieio to ensure the "hot word" of the table is written after
    all other table updates have occurred.
  - Added isync to ensure we don't prefetch loading of table entries
    until we a released

These issues we raised by Dave Liu.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-29 09:42:19 -05:00
Kumar Gala
022f121635 85xx: Round up frequency calculations to get reasonable output
eg. because of rounding error we can get 799Mhz instead of 800Mhz.

Introduced DIV_ROUND_UP and roundup taken from linux kernel.

Signed-off-by: Dejan Minic <minic@freescale.com>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-04-24 15:42:35 +02:00
Kumar Gala
0878af169b 85xx: Fix size of cpu-release-addr property
The cpu-release-addr is defined as always being a 64-bit quanity regardless
if we are running on a 32-bit or 64-bit machine.
2008-04-18 17:44:50 -05:00
Timur Tabi
88353a9851 Fix calculation of I2C clock for some 85xx chips
Some 85xx chips use CCB as the base clock for the I2C.  Some use CCB/2, and
some use CCB/3.  There is no pattern that can be used to determine which
chips use which frequency, so the only way to determine is to look up the
actual SOC designation and use the right value for that SOC.

Update immap_85xx.h to include the GUTS PORDEVSR2 register.

Signed-off-by: Timur Tabi <timur@freescale.com>
2008-04-18 17:43:09 -05:00
Kumar Gala
97b3ecb575 85xx: Fix detection of MP cpu spin up
We were looking at the wrong memory offset to determine of a secondary
cpu had been spun up or not.  Also added a warning message if the
all the secondary cpus we expect don't spin up.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-11 17:32:56 -05:00
Kumar Gala
f3e04bdc3f 85xx: Use SVR_SOC_VER instead of SVR_VER
The recent change introduced by 'Update SVR numbers to expand support'
now requires that we use SVR_SOC_VER instead of SVR_VER if we want
to compare against a particular processor id.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-11 17:32:51 -05:00
Kumar Gala
dd6c910aad 85xx: Add cpu_mp_lmb_reserve helper to reserve boot page
Provide a board_lmb_reserve helper function to ensure we reserve
the page of memory we are using for the boot page translation code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
Kumar Gala
79679d8002 85xx: Update multicore boot mechanism to ePAPR v0.81 spec
The following changes are needed to be inline with ePAPR v0.81:

* r4, r5 and now always set to 0 on boot release
* r7 is used to pass the size of the initial map area (IMA)
* EPAPR_MAGIC value changed for book-e processors
* changes in the spin table layout
* spin table supports a 64-bit physical release address

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
Kumar Gala
a5af4b358a 85xx: Fix merge duplication
ft_fixup_cpu() got duplicated in some merge snafu.  Remove the duplicate.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
James Yang
a3e77fa535 85xx: Speed up get_ddr_freq() and get_bus_freq()
get_ddr_freq() and get_bus_freq() used get_sys_info() each time they were
called.  However, get_sys_info() recalculates extraneous information when
called each time.  Have get_ddr_freq() and get_bus_freq() return memoized
values from global_data instead.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
James Yang
e9ea679918 85xx: Show DDR memory data rate in addition to the memory clock frequency.
Show the DDR memory data rate in addition to the memory clock
frequency.  For DDR/DDR2 memories the memory data rate is 2x the
memory clock.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
James Yang
591933ca6e 85xx: get_tbclk() speed up and rounding fix
Speed up get_tbclk() by referencing pre-computed bus clock
frequency value from global data instead of sys_info_t.  Fix
rounding of result to nearest; previously it was rounding
upwards.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
Andy Fleming
1ced121600 Update SVR numbers to expand support
FSL has taken to using SVR[16:23] as an SOC sub-version field.  This
is used to distinguish certain variants within an SOC family.  To
account for this, we add the SVR_SOC_VER() macro, and update the SVR_*
constants to reflect the larger value.  We also add SVR numbers for all
of the current variants.  Finally, to make things neater, rather than
use an enormous switch statement to print out the CPU type, we create
and array of SVR/name pairs (using a macro), and print out the CPU name
that matches the SVR SOC version.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-03-26 11:43:04 -05:00
Kumar Gala
7aff0c051a 85xx: Added support for multicore boot mechanism
Added the cpu command that provides a generic mechanism to get status,
reset, and release secondary cores in multicore processors.

Added support for using the ePAPR defined spin-table mechanism on 85xx.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-03-26 11:43:03 -05:00
Kumar Gala
ec2b74ffd3 85xx: Added support for multicore boot mechanism
Added the cpu command that provides a generic mechanism to get status,
reset, and release secondary cores in multicore processors.

Added support for using the ePAPR defined spin-table mechanism on 85xx.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:03 -05:00
Kumar Gala
f69766e4b5 85xx: Add the concept of CFG_CCSRBAR_PHYS
When we go to 36-bit physical addresses we need to keep the concept of
the physical CCSRBAR address seperate from the virtual one.

For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:03 -05:00
Kumar Gala
2b22fa4bae 85xx: Don't icbi when unlocking the cache
There is no reason to icbi when invalidating the temporary stack in
the d-cache.  Its impossible on e500 to have the i-cache contain
any addresses in the temp stack and it can be problematic in generating
transactions on the bus to non-valid addresses.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-02-27 16:30:47 -06:00
Andy Fleming
534ea6b6f8 Fix source for ECM error IVPR
The source vector for the ECM was being set to 2,
but that's what the source vector for DDR was being
set to.  Change it to 1.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-02-27 16:28:57 -06:00
Andy Fleming
21fae8b2b4 Invalidate INIT_RAM TLB mappings
Commit 0db37dc...  (and some others) changed the INIT_RAM TLB
mappings to be unguarded.  This collided with an existing "bug"
where the mappings for the INIT_RAM were being kept around.
This meant that speculative loads to those addresses were
succeeding in the TLB, and going out to the bus, where they
were causing an exception (there's nothing at that address). The
Flash code was coincidentally causing such a speculative load.
Rather than go back to mapping the INIT RAM as guarded, we fix
it so that the entries for the INIT_RAM are invalidated.  Thus
the speculative loads will fail in the TLB, and have no effect.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-02-27 16:28:48 -06:00
Timur Tabi
943afa229c 85xx, 86xx: Determine I2C clock frequencies and store in global_data
Update global_data to define i2c1_clk and i2c2_clk to 85xx and 86xx.

Update the get_clocks() function in 85xx and 86xx to determine the I2C
clock frequency and store it in gd->i2c1_clk and gd->i2c2_clk.

Signed-off-by: Timur Tabi <timur@freescale.com>
2008-02-14 23:32:40 +01:00
Wolfgang Denk
e7670f6c1e PPC: Use r2 instead of r29 as global data pointer
R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc
will refuse to use load/store multiple insns; instead, it issues a
list of simple load/store instructions upon function entry and exit,
resulting in bigger code size, which in turn makes the build for a
few boards fail.

Use r2 instead.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-02-14 22:43:22 +01:00
Rafal Jaworowski
f57d7d364c ppc: Refactor cache routines, so there is only one common set.
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
2008-02-14 22:00:41 +01:00
Kumar Gala
69018ce2e0 QE: Move FDT support into a common file
Move the flat device tree setup for QE related devices into
a common file shared between 83xx & 85xx platforms that have QE's.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-02-12 00:36:21 +01:00
Wolfgang Denk
865f0f9754 Coding Style Cleanup; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-01-23 14:31:17 +01:00
Kumar Gala
7dc358bb0d 85xx: Get ride of old TLB setup code
Now that all boards have been converted, remove old config code and the
config option for the new style.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 02:19:18 -06:00
Kumar Gala
8716318057 85xx: Reworked initial processor init
Reworked the initial processor initialzation sequence:
* introduced cpu_early_init_f that is run in address space 1 (AS=1)
* Moved TLB/LAW and CCSR init into cpu_early_init_f()
* Reworked initial asm code to do most of the core init before TLBs

The main reasons for these changes are to allow handling of 36-bit phys
addresses in the future and some of the issues that will exist when we
do that.

There are a few caveats on what can be initialized via the LAW and TLB
static tables:
* TLB entry 14/15 can't be initialized via the TLB table
* any LAW that covers the implicit boot window (4G-8M to 4G) must map to
  the code that is currently executing.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 02:04:53 -06:00
Kumar Gala
44a23cfd63 85xx: Introduce new tlb API
Add a set of functions to manipulate TLB entries:
 * set_tlb() - write a tlb entry
 * invalidate_tlb() - invalidate a tlb array
 * disable_tlb() - disable a variable size tlb entry
 * init_tlbs() - setup initial tlbs based on static table

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 02:04:07 -06:00
Kumar Gala
54a5070115 85xx: Remove old style of LAW init
All boards are now using the new fsl_law code so we can drop the old version.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-16 23:21:56 -06:00
Kumar Gala
83d40dfd79 85xx: Move LAW init code into C
Move the initialization of the LAWs into C code and provide an API
to allow modification of LAWs after init.

Board code is responsible to provide a law_table and num_law_entries.

We should be able to use the same code on 86xx as well.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-16 23:21:55 -06:00
Kim Phillips
17a41e4492 Add QE brg freq and correct qe bus freq fdt update code
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-01-09 16:56:54 -06:00
Timur Tabi
b8ec238503 85xx: add ability to upload QE firmware
Define the layout of a binary blob that contains a QE firmware and instructions
on how to upload it.  Add function qe_upload_firmware() to parse the blob and
perform the actual upload.  Add command-line command "qe fw" to take a firmware
blob in memory and upload it.  Update ft_cpu_setup() on 85xx to create the
'firmware' device tree node if U-Boot has uploaded a firmware.  Fully define
'struct rsp' in immap_qe.h to include the actual RISC Special Registers.

Signed-off-by: Timur Tabi <timur@freescale.com>
2008-01-09 16:28:12 -06:00
Kumar Gala
b009f3eca9 85xx: Remove cache config from configs.h
Either use the standard defines in asm/cache.h or grab the information
at runtime from the L1CFG SPR.

Also, minor cleanup in cache.h to make the code a bit more readable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-09 16:25:04 -06:00
Kumar Gala
2146cf5682 Reworked FSL Book-E TLB macros to be more readable
The old macros made it difficult to know what WIMGE and perm bits
were set for a TLB entry.  Actually use the bit masks for these items
since they are only a single bit.

Also moved the macros into mmu.h out of e500.h since they aren't specific
to e500.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-09 16:25:03 -06:00
Kumar Gala
d435793229 Handle Asynchronous DDR clock on 85xx
The MPC8572 introduces the concept of an asynchronous DDR clock with
regards to the platform clock.

Introduce get_ddr_freq() to report the DDR freq regardless of sync/async
mode.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:20 -06:00
Kumar Gala
04db400892 Stop using immap_t on 85xx
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_*_ADDR as the base of the registers
instead of getting it via &immap.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:20 -06:00
Kumar Gala
2714223f8e Remove CONFIG_OF_FLAT_TREE related code from mpc85xx since we now use libfdt
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:20 -06:00
Kumar Gala
aafeefbdb8 Stop using immap_t for cpm offset on 85xx
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers
instead of getting it via &immap->im_cpm.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:19 -06:00
Kumar Gala
f59b55a5b8 Stop using immap_t for guts offset on 85xx
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers
instead of getting it via &immap->im_gur.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:19 -06:00
Kumar Gala
f852ce72f1 Add libfdt based ft_cpu_setup for mpc85xx
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:19 -06:00
Wolfgang Denk
992742a5b0 Cleanup coding style; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-11-03 23:09:27 +01:00
urwithsughosh@gmail.com
df90968b48 Setting MSR[DE] in do_reset
Hello,
   This patch ensures the soft reset of the board for the 85xx boards
   by setting the MSR[DE] in the do_reset function.

Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
2007-10-19 13:13:44 -05:00
urwithsughosh@gmail.com
1e701e7013 MSR overwrite fix
Hello,
  This patch fixes the MSR overwrite in the start.S when moving out of
  the last 4K page.

Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
2007-10-19 13:13:27 -05:00
Kumar Gala
e1ce3cb617 Remove magic numbers from cache related operations for mpc85xx
The mpc85xx start code uses some magic numbers that we actually
have #defines for in <config.h> so use those instead.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-19 11:25:01 -05:00
Ed Swarthout
1487adbdcf 85xx io out functions need sync after write.
This fixes the mc146818 rtc_read/write functions for 85xx.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2007-09-26 16:50:02 -05:00
Haiying Wang
7a1ac419fa Enable L2 cache for MPC8568MDS board
The L2 cache size is 512KB for 8568, print out the correct informaiton.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2007-08-29 00:11:44 -05:00
Randy Vinson
7f3f2bd2dc 85xxCDS: Add make targets for legacy systems.
The PCI ID select values on the Arcadia main board differ depending
on the version of the hardware. The standard configuration supports
Rev 3.1. The legacy target supports Rev 2.x.

Signed-off-by Randy Vinson <rvinson@mvista.com>
2007-08-14 01:51:39 -05:00
Andy Fleming
da9d4610d7 Add support for UEC to 8568
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-08-14 01:47:44 -05:00
Haiying Wang
d111d6382c Empirically set cpo and clk_adjust for mpc85xx DDR2 support
This patch is against u-boot-mpc85xx.git of www.denx.com

Setting cpo to 0x9 for frequencies higher than 333MHz is verified on
both MPC8548CDS board and MPC8568MDS board, especially for supporting
533MHz DDR2.

Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for
DDR2 on all current board versions especially ver 1.92 or later to bring
up.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2007-08-14 01:45:51 -05:00
Kumar Gala
3db0bef59e Use an absolute address when jumping out of 4k boot page
On e500 when we leave the 4k boot page we should use an absolute address since
we don't know where the board code may want us to be really running at.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-08-14 01:45:09 -05:00
Andy Fleming
39980c610c MPC85xx BA bits not set for 3-bit bank address DIMM
The current implementation does not set the number of bank address bits
(BA) in the processor. The default assumes 2 logical bank bits. This
works fine for a DIMM that uses devices with 4 internal banks (SPD
byte17 = 0x4) but needs to be set appropriately for a DIMM that uses
devices with 8 internal banks (SPD byte17 = 0x8).

Signed-off-by: Greg Davis <DavisG@embeddedplanet.com>
2007-08-14 01:44:55 -05:00
Andy Fleming
6c543597bb Fix minor 85xx warnings
Some patches had inserted warnings into the build:
* mpc8560ads declared data without using it
* cpu_init declared ecm and immap without using it in all CONFIGs
* MPC8548CDS.h had its default filenames changed so that they contained
  "\m" in the paths.  Made the defaults not Windows-specific (or
  anything-specific)

Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-08-14 01:39:14 -05:00
Andy Fleming
61a21e980a 85xx start.S cleanup and exception support
From: Ed Swarthout <Ed.Swarthout@freescale.com>

Support external interrupts from platform to eliminate system hangs.
Define CONFIG_INTERRUPTS board configure option to enable.
Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.

Remove extra cpu initialization redundant with hardware initialization.
Whitespace cleanup.

Define and use _START_OFFSET consistent with other processors using
ppc_asm.tmpl

Move additional code from .text to boot page to make room for
exception vectors at start of image.

Handle Machine Check, External and Critical exceptions.

Fix e500 machine check error determination in traps.c

TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2007-08-14 01:34:21 -05:00
Ed Swarthout
40c7f9b0de 85xx allow debugger to configure ddr.
Only check for mpc8548 rev 1 when compiled for 8548.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2007-08-14 01:22:01 -05:00
Ed Swarthout
29372ff38c mpc85xx L2 cache reporting and SRAM relocation option.
Allow debugger to override flash cs0/cs1 settings to enable alternate
boot regions

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2007-08-14 01:21:55 -05:00
Jon Loeliger
068b60a0eb cpu/ rtc/ include/: Remove lingering references to CFG_CMD_* symbols.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-10 10:27:39 -05:00
Jon Loeliger
4431283c7e cpu/m*: Remove obsolete references to CONFIG_COMMANDS
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-09 19:06:00 -05:00
Jon Loeliger
56b304ac20 Fix #if typo in CONFIG_CMD_* changes.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-05 03:41:23 +02:00
Jon Loeliger
f48070fe5f cpu/mpc*/ : Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*).
This is a compatibility step that allows both the older form
and the new form to co-exist for a while until the older can
be removed entirely.

All transformations are of the form:
Before:
    #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT)
After:
    #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT)

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-04 00:23:18 +02:00
Wolfgang Denk
98c440bee6 Merge with /home/wd/git/u-boot/custodian/u-boot-testing 2007-07-03 15:07:56 +02:00
Rafal Jaworowski
02032e8f14 [ppc] Fix build breakage for all non-4xx PowerPC variants.
- adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros
- minor 4xx cleanup
2007-06-22 14:58:04 +02:00
Kim Phillips
255a3577c8 Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx
For all practical u-boot purposes, TSECs don't differ throughout the
mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-05-17 00:07:21 +02:00
Wolfgang Denk
2f15278c2e Coding stylke cleanup; update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-05-05 18:23:11 +02:00
Andy Fleming
ffa621a0d1 Cleaned up some 85xx PCI bugs
* Cleaned up the CDS PCI Config Tables and added NULL entries to
  the end
* Fixed PCIe LAWBAR assignemt to use the cpu-relative address
* Fixed 85xx PCI code to assign powar region sizes based on the
  config values (rather than hard-coding them)
* Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address

Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-05-02 15:50:13 -05:00
Andy Fleming
6743105988 Add support for the 8568 MDS board
This included some changes to common files:
* Add 8568 processor SVR to various places
* Add support for setting the qe bus-frequency value in the dts
* Add the 8568MDS target to the Makefile

Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-05-02 15:50:02 -05:00
Andy Fleming
66ed6cca3f Reworked 85xx speed detection code
Changed the code to read the registers and calculate the clock
rates, rather than using a "switch" statement.

Idea from Andrew Klossner <andrew@cesa.opbu.xerox.com>

Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-04-23 19:58:28 -05:00
Andy Fleming
0d8c3a2096 Support 1G size on 8548
e500v2 and newer cores support 1G page sizes.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-04-23 19:58:28 -05:00
Andy Fleming
1f9a318cea Only set ddrioovcr for 8548 rev1.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-04-23 19:58:28 -05:00
Andy Fleming
9343dbf85b Tweak DDR ECC error counter
Enable single-bit error counter when memory was cleared by ddr controller.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-04-23 19:58:28 -05:00
Timur Tabi
85e7c7a45e 85xx: write MAC address to mac-address and local-mac-address
Some device trees have a mac-address property, some have local-mac-address,
and some have both.  To support all of these device trees, ftp_cpu_setup()
should write the MAC address to mac-address and local-mac-address, if they
exist.

Signed-off-by: Timur Tabi <timur@freescale.com>
2007-04-23 19:58:28 -05:00
Andy Fleming
03b81b48ee Some 85xx cpu cleanups
* Cleaned up the TSR[WIS] clearing
* Cleaned up DMA initialization

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2007-04-23 19:58:28 -05:00
Andy Fleming
151d5d992e Add cpu support for the 8544
Recognize new SVR values, and add a few register definitions

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2007-04-23 19:58:28 -05:00
Zang Roy-r61911
96629cbabd u-boot: Fix e500 v2 core reset bug
The following patch fixes the e500 v2 core reset bug.
For e500 v2 core, a new reset control register is added to reset the
processor.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2007-04-23 19:58:27 -05:00
Zang Roy-r61911
63247a5acd u-boot: v2: Remove the fixed TLB and LAW entrynubmer
Remove the fixed TLB and LAW entry nubmer. Use actually TLB and LAW
entry number to control the loop.  This can reduce the potential risk
for the 85xx processor increasing its TLB adn LAW entry number.

Signed-off-by: Swarthout Edward <swarthout@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2007-04-23 19:58:27 -05:00
Wolfgang Denk
47a6989c10 Code cleanup 2006-10-24 15:32:57 +02:00
Jon Loeliger
2047672684 Converted all 85xx boards to use a common FSL I2C driver.
Introduced COFIG_FSL_I2C to select the common FSL I2C driver.
And removed hard i2c path from a few u-boot.lds scipts too.
Minor whitespace cleanups along the way.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2006-10-20 15:50:15 -05:00
Jon Loeliger
13a7fcdf37 * Fix a bunch of compiler warnings for gcc 4.0
Signed-off-by: Matthew McClintock <msm@freescale.com>
2006-10-19 11:33:52 -05:00
Jon Loeliger
daaba9859b Merge branch 'master' of http://www.denx.de/git/u-boot 2006-10-10 17:21:42 -05:00
Jon Loeliger
1fd5699a4a Coding style changes to remove local varible blocks
and reformat a bit nicer.
2006-10-10 17:19:03 -05:00
Wolfgang Denk
2b208f5308 Move "ar" flags to config.mk to allow for silent "make -s"
Based on patch by Mike Frysinger, 20 Jun 2006
2006-10-09 01:02:05 +02:00
Jon Loeliger
afa98843e4 Merge branch 'master' of http://www.denx.de/git/u-boot
Conflicts:

	board/stxxtc/Makefile
2006-09-19 08:51:24 -05:00
Marian Balakowicz
f93286397e Add support for a saving build objects in a separate directory.
Modifications are based on the linux kernel approach and
support two use cases:

  1) Add O= to the make command line
  'make O=/tmp/build all'

  2) Set environement variable BUILD_DIR to point to the desired location
  'export BUILD_DIR=/tmp/build'
  'make'

The second approach can also be used with a MAKEALL script
'export BUILD_DIR=/tmp/build'
'./MAKEALL'

Command line 'O=' setting overrides BUILD_DIR environent variable.

When none of the above methods is used the local build is performed and
the object files are placed in the source directory.
2006-09-01 19:49:50 +02:00
Matthew McClintock
34c3c0e01d * Switched default PCI speed for 8540 ADS back to 33MHz
* Added comments and a printf to warn that PCI-X won't
  work at 33MHz
  Patch by Andy Fleming 17-Mar-2006

Signed-off-by: Andy Fleming <afleming@freescale.com>
2006-08-09 13:51:05 -05:00
Matthew McClintock
97074ed965 * Added support for initializing second PCI bus on 85xx Patch by Andy Fleming 17-Mar-2006
Signed-off-by: Andy Fleming <afleming@freescale.com>
2006-08-09 13:50:44 -05:00
Matthew McClintock
0e16387db1 * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards Patch by Jon Loeliger 17-Jan-2006
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2006-08-09 13:50:30 -05:00
Wolfgang Denk
d87080b721 GCC-4.x fixes: clean up global data pointer initialization for all boards. 2006-03-31 18:32:53 +02:00
Wolfgang Denk
b38dbd4622 Fix bug in [id]cache_status commands for MPC85xx processors;
should look at LSB of L1CSRn registers to determine if L1 cache is
enabled, not the MSB.
Patch by Murray Jensen, 19 Jul 2005
2006-03-13 00:46:05 +01:00
Wolfgang Denk
a889bd27ef Fix DPRAM offset/size for MPC8541/8555.
Simplify TQM85xx Makefile handling.
2005-12-06 15:02:31 +01:00
Stefan Roese
527b5a511c Fix MPC85xx PCI support (pci_register_hose() before pci config access)
Patch by Stefan Roese, 07 Nov 2005
2005-11-07 13:43:06 +01:00
Marian Balakowicz
63ff004c4f Add support for multiple PHYs. 2005-10-28 22:30:33 +02:00
Wolfgang Denk
77ddac9480 Cleanup for GCC-4.x 2005-10-13 16:45:02 +02:00
Wolfgang Denk
99b0d2851a Added support for KwikByte KB920x boards (based on AT91RM9200)
Patch by Matt ?? <kb9200_dev@kwikbyte.com>, 27 Apr 2005
2005-10-05 00:19:34 +02:00
Wolfgang Denk
7d314992a8 E500 update: repoint IVPR to RAM when code is relocated
Patch by Kylo Ginsberg, 13 Apr 2005
2005-10-05 00:00:54 +02:00
Wolfgang Denk
cbf9c11728 Merge with /home/wd/git/u-boot/master 2005-08-05 11:22:28 +02:00
Wolfgang Denk
3e0bc4473a Fix typos in cpu/85xx/start.S which caused DataTLB exception to be
routed to the Watchdog handler
Patch by Eugene Surovegin, 18 Jun 2005
2005-08-04 01:24:19 +02:00
Jon Loeliger
de1d0a6995 Fix style issues primarily in 85xx and 83xx boards.
- C++ comments
    - Trailing white space
    - Indentation not by TAB
    - Excessive amount of empty lines
    - Trailing empty lines
2005-08-01 13:20:47 -05:00
Lunsheng Wang
b0e3294923 * Patch by Ron Alder, 11 July 2005
Add Xianghua Xiao and Lunsheng Wang's support for the
    GDA MPC8540 EVAL board.
2005-07-29 10:20:29 -05:00
Jon Loeliger
63be111e72 * Patch by Jon Loeliger, 2005-07-25
Move the TSEC driver out of cpu/mpc85xx as it will be shared
  by the upcoming mpc83xx family as well.
2005-07-25 15:38:06 -05:00
Jon Loeliger
d9b94f28a4 * Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board.
  Added DDR II support based on SPD values for MPC85xx boards.
  This roll-up patch also includes bugfies for the previously
  published patches:
    DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
2005-07-25 14:05:07 -05:00
Jon Loeliger
d65cfe89ec * Patch by Jon Loeliger 2005-02-08
Determine L2 Cache size dynamically on 85XX boards.
2005-07-25 10:58:39 -05:00
Jon Loeliger
9c4c5ae3e1 * Patch by Jon Loeliger, Kumar Gala 2005-02-08
- Convert the CPM2 based functionality to use new CONFIG_CPM2
    option rather than a myriad of CONFIG_MPC8560-like variants.
    Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560.
    Eliminates the CONFIG_MPC8560 option entirely.  Distributes the
    new CONFIG_CPM2 option to each 8260 board.
2005-07-23 10:37:35 -05:00
wdenk
343117bf12 Fix timer handling on MPC85xx systems 2005-05-13 22:49:36 +00:00
wdenk
a63109281a Fix bug in the SDRAM initialization code for canmb, IceCube and
PM520 boards.

Fix PHY address for canmb board.
2005-04-21 21:10:22 +00:00
wdenk
2a8af18738 * Fixes for TQM8560 board:
- fix clock rates
  - remove debug messages
  - fix flash sector protection

* Patch by Steven Scholz, 07 Apr 2005:
  Fix warning in cpu/arm920t/at91rm9200/i2c.c
2005-04-13 10:02:42 +00:00
wdenk
3c2b3d454d * Patch by Ladislav Michl, 05 Apr 2005:
Add support for VoiceBlue board.

* Patch by Ladislav Michl, 05 Apr 2005:
  Fix netboot_common() prototypes.

* Cleanup.
2005-04-05 23:32:21 +00:00
wdenk
3dd7f0f0ca * Add FEC support for TQM8540 board.
Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC

* Patch by Martin Krause, 04 Apr 2005:
  Update default configuration for CMC_PU2 board.
2005-04-04 23:43:44 +00:00
wdenk
384cc68744 Patches by Josef Wagner, 29 Oct 2004:
- Add support for MicroSys CPU87 board
- Add support for MicroSys PM854 board
2005-04-03 22:35:21 +00:00
wdenk
8f0b7cbe80 Patches by Martin Krause, 22 Mar 2005:
- use TQM5200_auto as MAKEALL target for TQM5200 systems
- add support for SM501 graphics controller
- add support for graphic console on TQM5200
- add support for TQM5200 Rev 200
- cleanup, fix typo in include/configs/TQM5200.h
2005-03-27 23:41:39 +00:00
wdenk
6c9e789e9e Update code for TQM8540 board (and 85xx in general):
- Change the name of the Ethernet driver: MOTO ENET -> ENET
- Reformat boot messages
- Enable redundant environment
- Replace the -O2 optimization flag with -mno-string
2005-03-15 22:56:53 +00:00
wdenk
9d46ea4a55 * Patch by David Brownell, 10 Mar 2005:
Restore copyright statements in OHCI drivers.

* Add support for TQM8540 board
2005-03-14 23:56:42 +00:00
wdenk
5c952cf024 Patches by Scott McNutt, 24 Aug 2004:
- Add support for Altera Nios-II processors.
- Add support for Psyent PCI-5441 board.
- Add support for Psyent PK1C20 board.
2004-10-10 21:27:30 +00:00
wdenk
cf33678e51 * Patch by Jon Loeliger, 24 Aug 2004:
- Fix PCI window on MPC85xx; remove unneeded PCI initialization
    from board_early_init_f()
  - Provide SW workaround for PCI initialization on 85xx CDS
  - Convert MPC85xxADS to use common CFI flash driver

* Cleanup: avoid compiler warnings

* Add CMC PU2 board to MAKEALL script
2004-10-10 20:23:57 +00:00
wdenk
c65fdc74aa * Patch by Jon Loeliger, 15 Jul 2004:
Fix MPC85xx I2C driver
2004-09-28 21:26:26 +00:00
wdenk
9aea95307f Patch by Jon Loeliger, 16 Jul 2004:
- support larger DDR memories up to 2G on the PC8540/8560ADS and
  STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
  and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads
2004-08-01 23:02:45 +00:00
wdenk
281e00a3be * Code cleanup
* Patch by Sascha Hauer, 28 Jun:
  - add generic support for Motorola i.MX architecture
  - add support for mx1ads, mx1fs2 and scb9328 boards

* Patches by Marc Leeman, 23 Jul 2004:
  - Add define for the PCI/Memory Buffer Configuration Register
  - corrected comments in cpu/mpc824x/cpu_init.c

* Add support for multiple serial interfaces
  (for example to allow modem dial-in / dial-out)
2004-08-01 22:48:16 +00:00
wdenk
8b07a1103d * Patch by Fred Klatt, 25 Jun 2004:
Add support for WindRiver's SBC8560 board

* Patch by Nicolas Lacressonniere, 24 Jun 2004
  Small Bugs fixes for "at91rm9200dk" board:
  - Timing modifications for SPI DataFlash access
  - Fix NAND flash detection bug

* Patch by Nicolas Lacressonniere, 24 Jun 2004:
  Add Support for Flash AT49BV6416 for AT91RM9200DK board
2004-07-10 21:45:47 +00:00
wdenk
0ac6f8b749 Patch by Jon Loeliger, 17 June 2004:
Completion of the 8540ADS/8560ADS updates:
Fix some PCI and Rapid I/O memory maps,
Initialize both TSEC 1 and 2,
Initialize SDRAM
Update MAINTAINER for 85xx boards and README.mpc85xxads
2004-07-09 23:27:13 +00:00
wdenk
97d80fc391 Patches Part 1 by Jon Loeliger, 11 May 2004:
Dynamically handle REV1 and REV2 MPC85xx parts.
  (Jon Loeliger, 10-May-2004).
New consistent memory map and Local Access Window across MPC85xx line.
New CCSRBAR at 0xE000_0000 now.
Add RAPID I/O memory map.
New memory map in README.MPC85xxads
  (Kumar Gala, 10-May-2004)
Better board and CPU identification on MPC85xx boards at boot.
  (Jon Loeliger, 10-May-2004)
SDRAM clock control fixes on MPC8540ADS & MPC8560 boards.
Some configuration options for MPC8540ADS & MPC8560ADS cleaned up.
  (Jim Robertson, 10-May-2004)
Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver.
Supports multiple PHYs.
  (Andy Fleming, 10-May-2004)
Some README.MPC85xxads updates.
  (Kumar Gala, 10-May-2004)
Copyright updates for "Freescale"
  (Andy Fleming, 10-May-2004)
2004-06-09 00:34:46 +00:00
wdenk
7abf0c5886 * Patch by Dan Malek, 07 Apr 2004:
- Add support for RPC/STx GP3, Motorola 8560 board
  - Update 85xx TSEC driver so it searches MII for first available PHY
    and uses that one.
  - Add functions to support console MII commands.

* Patch by Tolunay Orkun, 07 Apr 2004:
  Move  initialization of bi_iic_fast[]
  from board_init_f() to board_init_r()

* Patch by Yasushi Shoji, 07 Apr 2004:
  Cleanup microblaze port

* Patch by Sangmoon Kim, 07 Apr 2004:
  Add auto SDRAM module detection for Debris board
2004-04-18 21:45:42 +00:00
wdenk
63e73c9a8e * Patches by Reinhard Meyer, 14 Feb 2004:
- update board/emk tree; use common flash driver
  - Corrected tested bits in machine check exception in cpu/mpc5xxx/traps.c
    [adapted for other PPC CPUs -- wd]
  - Added support for the M48T08 on the EVAL5200 board in rtc/mk48t59.c

* Patch by Jon Diekema, 13 Feb 2004:
  Call show_boot_progress() whenever POST "FAILED" is printed.

* Patch by Nishant Kamat, 13 Feb 2004:
  Add support for TI OMAP1610 H2 Board
  Fixes for cpu/arm926ejs/interrupt.c
       (based on Richard Woodruff's patch for arm925, 16 Oct 03)
  Fix for a timer bug in OMAP1610 Innovator
  Add support for CS0 (ROM)/CS3 (Flash) boot in OMAP1610 Innovator and H2

* Patches by Stephan Linz, 12 Feb 2004:
  - add support for NIOS timer with variable period preload counter value
  - prepare POST framework support for NIOS targets

* Patch by Denis Peter, 11 Feb 2004:
  add POST support for the MIP405 board
2004-02-23 22:22:28 +00:00
wdenk
3f85ce2785 * CVS add missing files
* Cleanup compiler warnings

* Fix problem with side effects in macros in include/usb.h

* Patch by David Benson, 13 Nov 2003:
  bug 841358 - fix TFTP download size limit

* Fixing bug 850768:
  improper flush_cache() in load_serial()

* Fixing bug 834943:
  MPC8540 - missing volatile declarations

* Patch by Stephen Williams, 09 Feb 2004:
  Add support for Xilinx SystemACE chip:
  - New files common/cmd_ace.c and include/systemace.h
  - Hook systemace support into cmd_fat and the partition manager

* Patch by Travis Sawyer, 09 Feb 2004:
  Add bi_opbfreq & bi_iic_fast to 440GX bd_info as needed for Linux
2004-02-23 16:11:30 +00:00
wdenk
5bb226e821 * Use "-fPIC" instead of "-mrelocatable" to prevent problems with
recent tools

* Add checksum verification to 'imls' command

* Add bd_info fields needed for 4xx Linux I2C driver

* Patch by Martin Krause, 4 Nov. 2003:
  Fix error in cmd_vfd.c (TRAB board: "vfd /1" shows now only one Bitmap)

* Print used network interface when CONFIG_NET_MULTI is set
2003-11-17 21:14:37 +00:00
wdenk
a57a496f4d * Patch by Xiao Xianghua, 23 Oct 2003:
small patch for mpc85xx

* Fix small problem in MPC5200 I2C driver

* Fix FCC3 support on ATC board
2003-10-26 22:52:58 +00:00
wdenk
42d1f0394b * Patches by Xianghua Xiao, 15 Oct 2003:
- Added Motorola CPU 8540/8560 support (cpu/85xx)
  - Added Motorola MPC8540ADS board support (board/mpc8540ads)
  - Added Motorola MPC8560ADS board support (board/mpc8560ads)

* Minor code cleanup
2003-10-15 23:53:47 +00:00