mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 21:54:01 +00:00
* Code cleanup
* Patch by Sascha Hauer, 28 Jun: - add generic support for Motorola i.MX architecture - add support for mx1ads, mx1fs2 and scb9328 boards * Patches by Marc Leeman, 23 Jul 2004: - Add define for the PCI/Memory Buffer Configuration Register - corrected comments in cpu/mpc824x/cpu_init.c * Add support for multiple serial interfaces (for example to allow modem dial-in / dial-out)
This commit is contained in:
parent
cfca5e604d
commit
281e00a3be
71 changed files with 5493 additions and 2493 deletions
13
CHANGELOG
13
CHANGELOG
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@ -2,12 +2,23 @@
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Changes since U-Boot 1.1.1:
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======================================================================
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* Patch by Sascha Hauer, 28 Jun:
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- add generic support for Motorola i.MX architecture
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- add support for mx1ads, mx1fs2 and scb9328 boards
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* Patches by Marc Leeman, 23 Jul 2004:
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- Add define for the PCI/Memory Buffer Configuration Register
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- corrected comments in cpu/mpc824x/cpu_init.c
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* Add support for multiple serial interfaces
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(for example to allow modem dial-in / dial-out)
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* Patch by Stefan Roese, 15 Jul 2004:
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cpu/ppc4xx/sdram.c rewritten now using get_ram_size()
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* Fix NSCU config; add ethernet wakeup code.
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* Add link for preloader for Motorola Coldfire to RAEDME.m68k
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* Add link for preloader for Motorola Coldfire to README.m68k
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* Patch by Michael Bendzick, 12 Jul 2004:
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fix output formatting in drivers/cfi_flash.c
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9
MAKEALL
9
MAKEALL
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@ -139,11 +139,10 @@ LIST_ARM7="B2 ep7312 evb4510 impa7 modnet50"
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#########################################################################
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LIST_ARM9=" \
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at91rm9200dk integratorcp integratorap \
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lpd7a400 mx1ads omap1510inn \
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omap1610h2 omap1610inn omap730p2 \
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smdk2400 smdk2410 trab \
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VCMA9 versatile \
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at91rm9200dk integratorcp integratorap lpd7a400 \
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mx1ads mx1fs2 omap1510inn omap1610h2 \
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omap1610inn omap730p2 scb9328 smdk2400 \
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smdk2410 trab VCMA9 versatile \
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"
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#########################################################################
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17
Makefile
17
Makefile
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@ -757,6 +757,7 @@ PLU405_config: unconfig
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PMC405_config: unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd
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PPChameleonEVB_config \
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PPChameleonEVB_BA_25_config \
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PPChameleonEVB_ME_25_config \
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PPChameleonEVB_HI_25_config \
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@ -1154,6 +1155,12 @@ lpd7a400_config \
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lpd7a404_config: unconfig
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@./mkconfig $(@:_config=) arm lh7a40x lpd7a40x
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mx1ads_config : unconfig
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@./mkconfig $(@:_config=) arm arm920t mx1ads
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mx1fs2_config : unconfig
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@./mkconfig $(@:_config=) arm arm920t mx1fs2
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omap1510inn_config : unconfig
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@./mkconfig $(@:_config=) arm arm925t omap1510inn
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@ -1192,6 +1199,9 @@ omap730p2_cs3boot_config : unconfig
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fi;
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@./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2
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scb9328_config : unconfig
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@./mkconfig $(@:_config=) arm arm920t scb9328
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smdk2400_config : unconfig
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@./mkconfig $(@:_config=) arm arm920t smdk2400
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@ -1239,13 +1249,6 @@ versatile_config : unconfig
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B2_config : unconfig
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@./mkconfig $(@:_config=) arm s3c44b0 B2 dave
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#########################################################################
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## MC9328 (Dragonball) Systems
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#########################################################################
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mx1ads_config : unconfig
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@./mkconfig $(@:_config=) arm mc9328 mx1ads
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#########################################################################
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## ARM720T Systems
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#########################################################################
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@ -40,6 +40,7 @@ V* Verification: dzu@denx.de
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#include <command.h>
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#include <malloc.h>
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#include <post.h>
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#include <serial.h>
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#include <linux/types.h>
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#include <linux/string.h> /* for strdup */
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@ -468,6 +469,13 @@ int board_postclk_init (void)
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return (0);
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}
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struct serial_device * default_serial_console (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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return gd->do_mdm_init ? &serial_scc_device : &serial_smc_device;
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}
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static void kbd_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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@ -23,9 +23,9 @@
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mc9328.h>
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/*#include <mc9328.h>*/
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#include <asm/arch-arm920t/imx-regs.h>
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/* ------------------------------------------------------------------------- */
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@ -67,7 +67,6 @@ static inline void delay (unsigned long loops) {
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* Miscellaneous platform dependent initialisations
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*/
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void SetAsynchMode(void) {
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__asm__ (
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"mrc p15,0,r0,c1,c0,0 \n"
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@ -85,42 +84,34 @@ int board_init (void) {
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volatile unsigned int tmp;
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mc9328sid = MX1_SIDR;
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mc9328sid = SIDR;
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MX1_GPCR = 0x000003AB; /* I/O pad driving strength */
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GPCR = 0x000003AB; /* I/O pad driving strength */
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/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
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/* MX1_CS1L = 0x11110601; */
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MX1_MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
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/* MX1_MPCTL0 = 0x003f1437; */ /* setting for 192 MHz MCU PLL CLK */
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MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
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/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
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* BCLK divider to 2 (i.e. BCLK to 48 MHz)
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*/
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MX1_CSCR = 0xAF000403;
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CSCR = 0xAF000403;
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MX1_CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
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MX1_CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
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CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
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CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
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/* setup cs4 for cs8900 ethernet */
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MX1_CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
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MX1_CS4L = 0x00001501;
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CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
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CS4L = 0x00001501;
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MX1_GIUS_A &= 0xFF3FFFFF;
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MX1_GPR_A &= 0xFF3FFFFF;
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GIUS(0) &= 0xFF3FFFFF;
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GPR(0) &= 0xFF3FFFFF;
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tmp = *(unsigned int *)(0x1500000C);
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tmp = *(unsigned int *)(0x1500000C);
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/* setup timer 1 as system timer */
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MX1_TPRER1 = 0x1f; /* divide by 32 */
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MX1_TCTL1 = 0x19; /* clock in from 32k Osc. */
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SetAsynchMode();
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gd->bd->bi_arch_number = 160; /* Arch number of MX1ADS Board */
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@ -131,19 +122,19 @@ int board_init (void) {
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dcache_enable();
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/* set PERCLKs */
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MX1_PCDR = 0x00000055; /* set PERCLKS */
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PCDR = 0x00000055; /* set PERCLKS */
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/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
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* PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
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* all sources selected as normal interrupt
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*/
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MX1_INTTYPEH = 0;
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MX1_INTTYPEL = 0;
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/* MX1_INTTYPEH = 0;
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MX1_INTTYPEL = 0;
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*/
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return 0;
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}
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int board_late_init(void) {
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setenv("stdout", "serial");
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@ -163,13 +154,10 @@ int board_late_init(void) {
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default :
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printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
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break;
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}
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return 0;
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}
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int dram_init (void) {
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DECLARE_GLOBAL_DATA_PTR;
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@ -24,7 +24,8 @@
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*/
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#include <common.h>
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#include <mc9328.h>
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/*#include <mc9328.h>*/
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#include <asm/arch/imx-regs.h>
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typedef unsigned long * p_u32;
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@ -33,27 +34,26 @@ typedef unsigned long * p_u32;
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/* Following Setting is for CSD1 */
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#define SFCTL 0x00221004
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#define reg_SFCTL __REG(SFCTL)
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#define SFCTL 0x00221004
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#define reg_SFCTL __REG(SFCTL)
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#define SYNCFLASH_A10 (0x00100000)
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#define SYNCFLASH_A10 (0x00100000)
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#define CMD_NORMAL (0x81020300) /* Normal Mode */
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#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
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#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
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#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
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#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
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#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
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#define CMD_NORMAL (0x81020300) /* Normal Mode */
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#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
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#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
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#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
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#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
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#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
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#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
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#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
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/* LCR Command */
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#define LCR_READSTATUS (0x0001C000) /* 0x70 */
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#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
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#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
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#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
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#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
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#define LCR_READSTATUS (0x0001C000) /* 0x70 */
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#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
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#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
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#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
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#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
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/* Get Status register */
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u32 SF_SR(void) {
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@ -82,7 +82,6 @@ u8 SF_Ready(void) {
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if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
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printf ("SyncFlash Error code %08x\n",tmp);
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};
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if (tmp == 0x00800080) /* Test Bit 7 of SR */
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@ -98,7 +97,6 @@ void SF_PrechargeAll(void) {
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reg_SFCTL = CMD_PREC; /* Set Precharge Command */
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tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
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}
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/* set SyncFlash to normal mode */
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@ -128,7 +126,6 @@ void SF_Erase(u32 RowAddress) {
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while(!SF_Ready());
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}
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void SF_NvmodeErase(void) {
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SF_PrechargeAll();
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@ -149,10 +146,8 @@ void SF_NvmodeWrite(void) {
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reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
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__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
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}
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/****************************************************************************************/
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ulong flash_init(void) {
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@ -195,7 +190,6 @@ ulong flash_init(void) {
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return FLASH_BANK_SIZE;
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}
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void flash_print_info (flash_info_t *info) {
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int i;
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@ -209,7 +203,6 @@ void flash_print_info (flash_info_t *info) {
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
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printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
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@ -236,7 +229,6 @@ void flash_print_info (flash_info_t *info) {
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printf ("\n");
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}
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/*-----------------------------------------------------------------------*/
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int flash_erase (flash_info_t *info, int s_first, int s_last) {
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@ -23,7 +23,6 @@
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* MA 02111-1307 USA
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*/
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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@ -34,7 +33,7 @@ SECTIONS
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. = ALIGN(4);
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.text :
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{
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cpu/mc9328/start.o (.text)
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cpu/arm920t/start.o (.text)
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*(.text)
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}
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|
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@ -1,5 +1,5 @@
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#
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# (C) Copyright 2000, 2001, 2002
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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@ -23,21 +23,25 @@
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include $(TOPDIR)/config.mk
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LIB = lib$(CPU).a
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LIB = lib$(BOARD).a
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START = start.o
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OBJS = serial.o interrupts.o cpu.o
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OBJS := mx1fs2.o flash.o
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SOBJS := memsetup.o
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all: .depend $(START) $(LIB)
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $^
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$(LIB): $(OBJS)
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$(AR) crv $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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|
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sinclude .depend
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-include .depend
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#########################################################################
|
10
board/mx1fs2/config.mk
Normal file
10
board/mx1fs2/config.mk
Normal file
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@ -0,0 +1,10 @@
|
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#
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||||
# This config file is used for compilation of IMX sources
|
||||
#
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||||
# You might change location of U-Boot in memory by setting right TEXT_BASE.
|
||||
# This allows for example having one copy located at the end of ram and stored
|
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# in flash device and later on while developing use other location to test
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# the code in RAM device only.
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#
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||||
|
||||
TEXT_BASE = 0x08f00000
|
914
board/mx1fs2/flash.c
Normal file
914
board/mx1fs2/flash.c
Normal file
|
@ -0,0 +1,914 @@
|
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/*
|
||||
* (C) 2000-2004 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* (C) 2003 August Hoeraendl, Logotronic GmbH
|
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*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#undef CONFIG_FLASH_16BIT
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||||
|
||||
#include <common.h>
|
||||
|
||||
#if defined CFG_JFFS_CUSTOM_PART
|
||||
#include <jffs2/jffs2.h>
|
||||
#endif
|
||||
|
||||
#define FLASH_BANK_SIZE MX1FS2_FLASH_BANK_SIZE
|
||||
#define MAIN_SECT_SIZE MX1FS2_FLASH_SECT_SIZE
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/*
|
||||
* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
|
||||
* has nothing to do with the flash chip being 8-bit or 16-bit.
|
||||
*/
|
||||
#ifdef CONFIG_FLASH_16BIT
|
||||
typedef unsigned short FLASH_PORT_WIDTH;
|
||||
typedef volatile unsigned short FLASH_PORT_WIDTHV;
|
||||
|
||||
#define FLASH_ID_MASK 0xFFFF
|
||||
#else
|
||||
typedef unsigned long FLASH_PORT_WIDTH;
|
||||
typedef volatile unsigned long FLASH_PORT_WIDTHV;
|
||||
|
||||
#define FLASH_ID_MASK 0xFFFFFFFF
|
||||
#endif
|
||||
|
||||
#define FPW FLASH_PORT_WIDTH
|
||||
#define FPWV FLASH_PORT_WIDTHV
|
||||
|
||||
#define ORMASK(size) ((-size) & OR_AM_MSK)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
#if 0
|
||||
static ulong flash_get_size(FPWV * addr, flash_info_t * info);
|
||||
static void flash_get_offsets(ulong base, flash_info_t * info);
|
||||
#endif
|
||||
static void flash_reset(flash_info_t * info);
|
||||
static int write_word_intel(flash_info_t * info, FPWV * dest, FPW data);
|
||||
static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
|
||||
#define write_word(in, de, da) write_word_amd(in, de, da)
|
||||
#ifdef CFG_FLASH_PROTECTION
|
||||
static void flash_sync_real_protect(flash_info_t * info);
|
||||
#endif
|
||||
|
||||
#if defined CFG_JFFS_CUSTOM_PART
|
||||
|
||||
/**
|
||||
* jffs2_part_info - get information about a JFFS2 partition
|
||||
*
|
||||
* @part_num: number of the partition you want to get info about
|
||||
* @return: struct part_info* in case of success, 0 if failure
|
||||
*/
|
||||
|
||||
static struct part_info part;
|
||||
static int current_part = -1;
|
||||
|
||||
struct part_info *
|
||||
jffs2_part_info(int part_num)
|
||||
{
|
||||
void *jffs2_priv_saved = part.jffs2_priv;
|
||||
|
||||
printf("jffs2_part_info: part_num=%i\n", part_num);
|
||||
|
||||
if (current_part == part_num)
|
||||
return ∂
|
||||
|
||||
/* rootfs */
|
||||
if (part_num == 0) {
|
||||
memset(&part, 0, sizeof (part));
|
||||
|
||||
part.offset = (char *) MX1FS2_JFFS2_PART0_START;
|
||||
part.size = MX1FS2_JFFS2_PART0_SIZE;
|
||||
|
||||
/* Mark the struct as ready */
|
||||
current_part = part_num;
|
||||
|
||||
printf("part.offset = 0x%08x\n", (unsigned int) part.offset);
|
||||
printf("part.size = 0x%08x\n", (unsigned int) part.size);
|
||||
}
|
||||
|
||||
/* userfs */
|
||||
if (part_num == 1) {
|
||||
memset(&part, 0, sizeof (part));
|
||||
|
||||
part.offset = (char *) MX1FS2_JFFS2_PART1_START;
|
||||
part.size = MX1FS2_JFFS2_PART1_SIZE;
|
||||
|
||||
/* Mark the struct as ready */
|
||||
current_part = part_num;
|
||||
|
||||
printf("part.offset = 0x%08x\n", (unsigned int) part.offset);
|
||||
printf("part.size = 0x%08x\n", (unsigned int) part.size);
|
||||
}
|
||||
|
||||
if (current_part == part_num) {
|
||||
part.usr_priv = ¤t_part;
|
||||
part.jffs2_priv = jffs2_priv_saved;
|
||||
return ∂
|
||||
}
|
||||
|
||||
printf("jffs2_part_info: end of partition table\n");
|
||||
return 0;
|
||||
}
|
||||
#endif /* CFG_JFFS_CUSTOM_PART */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* flash_init()
|
||||
*
|
||||
* sets up flash_info and returns size of FLASH (bytes)
|
||||
*/
|
||||
ulong
|
||||
flash_init(void)
|
||||
{
|
||||
int i, j;
|
||||
ulong size = 0;
|
||||
|
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
|
||||
ulong flashbase = 0;
|
||||
flash_info[i].flash_id =
|
||||
(FLASH_MAN_AMD & FLASH_VENDMASK) |
|
||||
(FLASH_AM640U & FLASH_TYPEMASK);
|
||||
flash_info[i].size = FLASH_BANK_SIZE;
|
||||
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
|
||||
memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
|
||||
switch (i) {
|
||||
case 0:
|
||||
flashbase = MX1FS2_FLASH_BASE;
|
||||
break;
|
||||
default:
|
||||
panic("configured too many flash banks!\n");
|
||||
break;
|
||||
}
|
||||
for (j = 0; j < flash_info[i].sector_count; j++) {
|
||||
flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE;
|
||||
}
|
||||
size += flash_info[i].size;
|
||||
}
|
||||
|
||||
/* Protect monitor and environment sectors */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_FLASH_BASE,
|
||||
CFG_FLASH_BASE + _bss_start - _armboot_start,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR,
|
||||
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void
|
||||
flash_reset(flash_info_t * info)
|
||||
{
|
||||
FPWV *base = (FPWV *) (info->start[0]);
|
||||
|
||||
/* Put FLASH back in read mode */
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
|
||||
*base = (FPW) 0x00FF00FF; /* Intel Read Mode */
|
||||
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
|
||||
*base = (FPW) 0x00F000F0; /* AMD Read Mode */
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
#if 0
|
||||
static void
|
||||
flash_get_offsets(ulong base, flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* set up sector start address table */
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
|
||||
&& (info->flash_id & FLASH_BTYPE)) {
|
||||
int bootsect_size; /* number of bytes/boot sector */
|
||||
int sect_size; /* number of bytes/regular sector */
|
||||
|
||||
bootsect_size = 0x00002000 * (sizeof (FPW) / 2);
|
||||
sect_size = 0x00010000 * (sizeof (FPW) / 2);
|
||||
|
||||
/* set sector offsets for bottom boot block type */
|
||||
for (i = 0; i < 8; ++i) {
|
||||
info->start[i] = base + (i * bootsect_size);
|
||||
}
|
||||
for (i = 8; i < info->sector_count; i++) {
|
||||
info->start[i] = base + ((i - 7) * sect_size);
|
||||
}
|
||||
} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
|
||||
&& (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
|
||||
|
||||
int sect_size; /* number of bytes/sector */
|
||||
|
||||
sect_size = 0x00010000 * (sizeof (FPW) / 2);
|
||||
|
||||
/* set up sector start address table (uniform sector type) */
|
||||
for (i = 0; i < info->sector_count; i++)
|
||||
info->start[i] = base + (i * sect_size);
|
||||
}
|
||||
}
|
||||
#endif /* 0 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
void
|
||||
flash_print_info(flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
uchar *boottype;
|
||||
uchar *bootletter;
|
||||
uchar *fmt;
|
||||
uchar botbootletter[] = "B";
|
||||
uchar topbootletter[] = "T";
|
||||
uchar botboottype[] = "bottom boot sector";
|
||||
uchar topboottype[] = "top boot sector";
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD:
|
||||
printf("AMD ");
|
||||
break;
|
||||
case FLASH_MAN_BM:
|
||||
printf("BRIGHT MICRO ");
|
||||
break;
|
||||
case FLASH_MAN_FUJ:
|
||||
printf("FUJITSU ");
|
||||
break;
|
||||
case FLASH_MAN_SST:
|
||||
printf("SST ");
|
||||
break;
|
||||
case FLASH_MAN_STM:
|
||||
printf("STM ");
|
||||
break;
|
||||
case FLASH_MAN_INTEL:
|
||||
printf("INTEL ");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
/* check for top or bottom boot, if it applies */
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
boottype = botboottype;
|
||||
bootletter = botbootletter;
|
||||
} else {
|
||||
boottype = topboottype;
|
||||
bootletter = topbootletter;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_AM640U:
|
||||
fmt = "29LV641D (64 Mbit, uniform sectors)\n";
|
||||
break;
|
||||
case FLASH_28F800C3B:
|
||||
case FLASH_28F800C3T:
|
||||
fmt = "28F800C3%s (8 Mbit, %s)\n";
|
||||
break;
|
||||
case FLASH_INTEL800B:
|
||||
case FLASH_INTEL800T:
|
||||
fmt = "28F800B3%s (8 Mbit, %s)\n";
|
||||
break;
|
||||
case FLASH_28F160C3B:
|
||||
case FLASH_28F160C3T:
|
||||
fmt = "28F160C3%s (16 Mbit, %s)\n";
|
||||
break;
|
||||
case FLASH_INTEL160B:
|
||||
case FLASH_INTEL160T:
|
||||
fmt = "28F160B3%s (16 Mbit, %s)\n";
|
||||
break;
|
||||
case FLASH_28F320C3B:
|
||||
case FLASH_28F320C3T:
|
||||
fmt = "28F320C3%s (32 Mbit, %s)\n";
|
||||
break;
|
||||
case FLASH_INTEL320B:
|
||||
case FLASH_INTEL320T:
|
||||
fmt = "28F320B3%s (32 Mbit, %s)\n";
|
||||
break;
|
||||
case FLASH_28F640C3B:
|
||||
case FLASH_28F640C3T:
|
||||
fmt = "28F640C3%s (64 Mbit, %s)\n";
|
||||
break;
|
||||
case FLASH_INTEL640B:
|
||||
case FLASH_INTEL640T:
|
||||
fmt = "28F640B3%s (64 Mbit, %s)\n";
|
||||
break;
|
||||
default:
|
||||
fmt = "Unknown Chip Type\n";
|
||||
break;
|
||||
}
|
||||
|
||||
printf(fmt, bootletter, boottype);
|
||||
|
||||
printf(" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf(" Sector Start Addresses:");
|
||||
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
if ((i % 5) == 0) {
|
||||
printf("\n ");
|
||||
}
|
||||
|
||||
printf(" %08lX%s", info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
|
||||
#if 0
|
||||
ulong
|
||||
flash_get_size(FPWV * addr, flash_info_t * info)
|
||||
{
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
|
||||
/* Write auto select command sequence and test FLASH answer */
|
||||
addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */
|
||||
addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */
|
||||
addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */
|
||||
|
||||
/* The manufacturer codes are only 1 byte, so just use 1 byte.
|
||||
* This works for any bus width and any FLASH device width.
|
||||
*/
|
||||
switch (addr[0] & 0xff) {
|
||||
|
||||
case (uchar) AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
|
||||
case (uchar) INTEL_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_INTEL;
|
||||
break;
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
|
||||
if (info->flash_id != FLASH_UNKNOWN)
|
||||
switch (addr[1]) {
|
||||
|
||||
case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
|
||||
info->flash_id += FLASH_AM640U;
|
||||
info->sector_count = 128;
|
||||
info->size = 0x00800000 * (sizeof (FPW) / 2);
|
||||
break; /* => 8 or 16 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F800C3B:
|
||||
info->flash_id += FLASH_28F800C3B;
|
||||
info->sector_count = 23;
|
||||
info->size = 0x00100000 * (sizeof (FPW) / 2);
|
||||
break; /* => 1 or 2 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F800B3B:
|
||||
info->flash_id += FLASH_INTEL800B;
|
||||
info->sector_count = 23;
|
||||
info->size = 0x00100000 * (sizeof (FPW) / 2);
|
||||
break; /* => 1 or 2 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F160C3B:
|
||||
info->flash_id += FLASH_28F160C3B;
|
||||
info->sector_count = 39;
|
||||
info->size = 0x00200000 * (sizeof (FPW) / 2);
|
||||
break; /* => 2 or 4 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F160B3B:
|
||||
info->flash_id += FLASH_INTEL160B;
|
||||
info->sector_count = 39;
|
||||
info->size = 0x00200000 * (sizeof (FPW) / 2);
|
||||
break; /* => 2 or 4 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F320C3B:
|
||||
info->flash_id += FLASH_28F320C3B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000 * (sizeof (FPW) / 2);
|
||||
break; /* => 4 or 8 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F320B3B:
|
||||
info->flash_id += FLASH_INTEL320B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000 * (sizeof (FPW) / 2);
|
||||
break; /* => 4 or 8 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F640C3B:
|
||||
info->flash_id += FLASH_28F640C3B;
|
||||
info->sector_count = 135;
|
||||
info->size = 0x00800000 * (sizeof (FPW) / 2);
|
||||
break; /* => 8 or 16 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F640B3B:
|
||||
info->flash_id += FLASH_INTEL640B;
|
||||
info->sector_count = 135;
|
||||
info->size = 0x00800000 * (sizeof (FPW) / 2);
|
||||
break; /* => 8 or 16 MB */
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* => no or unknown flash */
|
||||
}
|
||||
|
||||
flash_get_offsets((ulong) addr, info);
|
||||
|
||||
/* Put FLASH back in read mode */
|
||||
flash_reset(info);
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
#endif /* 0 */
|
||||
|
||||
#ifdef CFG_FLASH_PROTECTION
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
static void
|
||||
flash_sync_real_protect(flash_info_t * info)
|
||||
{
|
||||
FPWV *addr = (FPWV *) (info->start[0]);
|
||||
FPWV *sect;
|
||||
int i;
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_28F800C3B:
|
||||
case FLASH_28F800C3T:
|
||||
case FLASH_28F160C3B:
|
||||
case FLASH_28F160C3T:
|
||||
case FLASH_28F320C3B:
|
||||
case FLASH_28F320C3T:
|
||||
case FLASH_28F640C3B:
|
||||
case FLASH_28F640C3T:
|
||||
/* check for protected sectors */
|
||||
*addr = (FPW) 0x00900090;
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02.
|
||||
* D0 = 1 for each device if protected.
|
||||
* If at least one device is protected the sector is marked
|
||||
* protected, but mixed protected and unprotected devices
|
||||
* within a sector should never happen.
|
||||
*/
|
||||
sect = (FPWV *) (info->start[i]);
|
||||
info->protect[i] =
|
||||
(sect[2] & (FPW) (0x00010001)) ? 1 : 0;
|
||||
}
|
||||
|
||||
/* Put FLASH back in read mode */
|
||||
flash_reset(info);
|
||||
break;
|
||||
|
||||
case FLASH_AM640U:
|
||||
default:
|
||||
/* no hardware protect that we support */
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int
|
||||
flash_erase(flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
FPWV *addr;
|
||||
int flag, prot, sect;
|
||||
int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
|
||||
ulong start, now, last;
|
||||
int rcode = 0;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf("- missing\n");
|
||||
} else {
|
||||
printf("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_INTEL800B:
|
||||
case FLASH_INTEL160B:
|
||||
case FLASH_INTEL320B:
|
||||
case FLASH_INTEL640B:
|
||||
case FLASH_28F800C3B:
|
||||
case FLASH_28F160C3B:
|
||||
case FLASH_28F320C3B:
|
||||
case FLASH_28F640C3B:
|
||||
case FLASH_AM640U:
|
||||
break;
|
||||
case FLASH_UNKNOWN:
|
||||
default:
|
||||
printf("Can't erase unknown flash type %08lx - aborted\n",
|
||||
info->flash_id);
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
start = get_timer(0);
|
||||
last = start;
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
|
||||
|
||||
if (info->protect[sect] != 0) /* protected, skip it */
|
||||
continue;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr = (FPWV *) (info->start[sect]);
|
||||
if (intel) {
|
||||
*addr = (FPW) 0x00500050; /* clear status register */
|
||||
*addr = (FPW) 0x00200020; /* erase setup */
|
||||
*addr = (FPW) 0x00D000D0; /* erase confirm */
|
||||
} else {
|
||||
/* must be AMD style if not Intel */
|
||||
FPWV *base; /* first address in bank */
|
||||
|
||||
base = (FPWV *) (info->start[0]);
|
||||
base[0x0555] = (FPW) 0x00AA00AA; /* unlock */
|
||||
base[0x02AA] = (FPW) 0x00550055; /* unlock */
|
||||
base[0x0555] = (FPW) 0x00800080; /* erase mode */
|
||||
base[0x0555] = (FPW) 0x00AA00AA; /* unlock */
|
||||
base[0x02AA] = (FPW) 0x00550055; /* unlock */
|
||||
*addr = (FPW) 0x00300030; /* erase sector */
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 50us for AMD, 80us for Intel.
|
||||
* Let's wait 1 ms.
|
||||
*/
|
||||
udelay(1000);
|
||||
|
||||
while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
||||
if ((now = get_timer(0)) - start > CFG_FLASH_ERASE_TOUT) {
|
||||
printf("Timeout\n");
|
||||
|
||||
if (intel) {
|
||||
/* suspend erase */
|
||||
*addr = (FPW) 0x00B000B0;
|
||||
}
|
||||
|
||||
flash_reset(info); /* reset to read mode */
|
||||
rcode = 1; /* failed */
|
||||
break;
|
||||
}
|
||||
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
flash_reset(info); /* reset to read mode */
|
||||
}
|
||||
|
||||
printf(" done\n");
|
||||
return rcode;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
int
|
||||
bad_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
|
||||
int bytes; /* number of bytes to program in current word */
|
||||
int left; /* number of bytes left to program */
|
||||
int i, res;
|
||||
|
||||
for (left = cnt, res = 0;
|
||||
left > 0 && res == 0;
|
||||
addr += sizeof (data), left -= sizeof (data) - bytes) {
|
||||
|
||||
bytes = addr & (sizeof (data) - 1);
|
||||
addr &= ~(sizeof (data) - 1);
|
||||
|
||||
/* combine source and destination data so can program
|
||||
* an entire word of 16 or 32 bits
|
||||
*/
|
||||
for (i = 0; i < sizeof (data); i++) {
|
||||
data <<= 8;
|
||||
if (i < bytes || i - bytes >= left)
|
||||
data += *((uchar *) addr + i);
|
||||
else
|
||||
data += *src++;
|
||||
}
|
||||
|
||||
/* write one word to the flash */
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD:
|
||||
res = write_word_amd(info, (FPWV *) addr, data);
|
||||
break;
|
||||
case FLASH_MAN_INTEL:
|
||||
res = write_word_intel(info, (FPWV *) addr, data);
|
||||
break;
|
||||
default:
|
||||
/* unknown flash type, error! */
|
||||
printf("missing or unknown FLASH type\n");
|
||||
res = 1; /* not really a timeout, but gives error */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (res);
|
||||
}
|
||||
|
||||
/**
|
||||
* write_buf: - Copy memory to flash.
|
||||
*
|
||||
* @param info:
|
||||
* @param src: source of copy transaction
|
||||
* @param addr: where to copy to
|
||||
* @param cnt: number of bytes to copy
|
||||
*
|
||||
* @return error code
|
||||
*/
|
||||
|
||||
int
|
||||
write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp;
|
||||
FPW data;
|
||||
int l;
|
||||
int i, rc;
|
||||
|
||||
wp = (addr & ~1); /* get lower word aligned address */
|
||||
|
||||
/* handle unaligned start bytes */
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < l; ++i, ++cp) {
|
||||
data = (data >> 8) | (*(uchar *) cp << 8);
|
||||
}
|
||||
for (; i < 2 && cnt > 0; ++i) {
|
||||
data = (data >> 8) | (*src++ << 8);
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt == 0 && i < 2; ++i, ++cp) {
|
||||
data = (data >> 8) | (*(uchar *) cp << 8);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, (FPWV *)wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 2;
|
||||
}
|
||||
|
||||
/* handle word aligned part */
|
||||
while (cnt >= 2) {
|
||||
/* data = *((vushort*)src); */
|
||||
data = *((FPW *) src);
|
||||
if ((rc = write_word(info, (FPWV *)wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += sizeof (FPW);
|
||||
wp += sizeof (FPW);
|
||||
cnt -= sizeof (FPW);
|
||||
}
|
||||
|
||||
if (cnt == 0)
|
||||
return ERR_OK;
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
|
||||
data = (data >> 8) | (*src++ << 8);
|
||||
--cnt;
|
||||
}
|
||||
for (; i < 2; ++i, ++cp) {
|
||||
data = (data >> 8) | (*(uchar *) cp << 8);
|
||||
}
|
||||
|
||||
return write_word(info, (FPWV *)wp, data);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash for AMD FLASH
|
||||
* A word is 16 or 32 bits, whichever the bus width of the flash bank
|
||||
* (not an individual chip) is.
|
||||
*
|
||||
* returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int
|
||||
write_word_amd(flash_info_t * info, FPWV * dest, FPW data)
|
||||
{
|
||||
ulong start;
|
||||
int flag;
|
||||
int res = 0; /* result, assume success */
|
||||
FPWV *base; /* first address in flash bank */
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*dest & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
base = (FPWV *) (info->start[0]);
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
base[0x0555] = (FPW) 0x00AA00AA; /* unlock */
|
||||
base[0x02AA] = (FPW) 0x00550055; /* unlock */
|
||||
base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */
|
||||
|
||||
*dest = data; /* start programming the data */
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
start = get_timer(0);
|
||||
|
||||
/* data polling for D7 */
|
||||
while (res == 0
|
||||
&& (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
|
||||
if (get_timer(0) - start > CFG_FLASH_WRITE_TOUT) {
|
||||
*dest = (FPW) 0x00F000F0; /* reset bank */
|
||||
printf("SHA timeout\n");
|
||||
res = 1;
|
||||
}
|
||||
}
|
||||
|
||||
return (res);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash for Intel FLASH
|
||||
* A word is 16 or 32 bits, whichever the bus width of the flash bank
|
||||
* (not an individual chip) is.
|
||||
*
|
||||
* returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int
|
||||
write_word_intel(flash_info_t * info, FPWV * dest, FPW data)
|
||||
{
|
||||
ulong start;
|
||||
int flag;
|
||||
int res = 0; /* result, assume success */
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*dest & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
*dest = (FPW) 0x00500050; /* clear status register */
|
||||
*dest = (FPW) 0x00FF00FF; /* make sure in read mode */
|
||||
*dest = (FPW) 0x00400040; /* program setup */
|
||||
|
||||
*dest = data; /* start programming the data */
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
start = get_timer(0);
|
||||
|
||||
while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
||||
*dest = (FPW) 0x00B000B0; /* Suspend program */
|
||||
res = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (res == 0 && (*dest & (FPW) 0x00100010))
|
||||
res = 1; /* write failed, time out error is close enough */
|
||||
|
||||
*dest = (FPW) 0x00500050; /* clear status register */
|
||||
*dest = (FPW) 0x00FF00FF; /* make sure in read mode */
|
||||
|
||||
return (res);
|
||||
}
|
||||
|
||||
#ifdef CFG_FLASH_PROTECTION
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
int
|
||||
flash_real_protect(flash_info_t * info, long sector, int prot)
|
||||
{
|
||||
int rcode = 0; /* assume success */
|
||||
FPWV *addr; /* address of sector */
|
||||
FPW value;
|
||||
|
||||
addr = (FPWV *) (info->start[sector]);
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_28F800C3B:
|
||||
case FLASH_28F800C3T:
|
||||
case FLASH_28F160C3B:
|
||||
case FLASH_28F160C3T:
|
||||
case FLASH_28F320C3B:
|
||||
case FLASH_28F320C3T:
|
||||
case FLASH_28F640C3B:
|
||||
case FLASH_28F640C3T:
|
||||
flash_reset(info); /* make sure in read mode */
|
||||
*addr = (FPW) 0x00600060L; /* lock command setup */
|
||||
if (prot)
|
||||
*addr = (FPW) 0x00010001L; /* lock sector */
|
||||
else
|
||||
*addr = (FPW) 0x00D000D0L; /* unlock sector */
|
||||
flash_reset(info); /* reset to read mode */
|
||||
|
||||
/* now see if it really is locked/unlocked as requested */
|
||||
*addr = (FPW) 0x00900090;
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02.
|
||||
* D0 = 1 for each device if protected.
|
||||
* If at least one device is protected the sector is marked
|
||||
* protected, but return failure. Mixed protected and
|
||||
* unprotected devices within a sector should never happen.
|
||||
*/
|
||||
value = addr[2] & (FPW) 0x00010001;
|
||||
if (value == 0)
|
||||
info->protect[sector] = 0;
|
||||
else if (value == (FPW) 0x00010001)
|
||||
info->protect[sector] = 1;
|
||||
else {
|
||||
/* error, mixed protected and unprotected */
|
||||
rcode = 1;
|
||||
info->protect[sector] = 1;
|
||||
}
|
||||
if (info->protect[sector] != prot)
|
||||
rcode = 1; /* failed to protect/unprotect as requested */
|
||||
|
||||
/* reload all protection bits from hardware for now */
|
||||
flash_sync_real_protect(info);
|
||||
break;
|
||||
|
||||
case FLASH_AM640U:
|
||||
default:
|
||||
/* no hardware protect that we support */
|
||||
info->protect[sector] = prot;
|
||||
break;
|
||||
}
|
||||
|
||||
return rcode;
|
||||
}
|
||||
#endif
|
99
board/mx1fs2/intel.h
Normal file
99
board/mx1fs2/intel.h
Normal file
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* Copyright (C) 2002 ETC s.r.o.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the ETC s.r.o. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Written by Marcel Telka <marcel@telka.sk>, 2002.
|
||||
*
|
||||
* Documentation:
|
||||
* [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
|
||||
* 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
|
||||
* [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
|
||||
* 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
|
||||
*
|
||||
* This file is taken from OpenWinCE project hosted by SourceForge.net
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef FLASH_INTEL_H
|
||||
#define FLASH_INTEL_H
|
||||
|
||||
#include <common.h>
|
||||
|
||||
/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
|
||||
|
||||
#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
|
||||
|
||||
/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
|
||||
|
||||
#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */
|
||||
|
||||
/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
|
||||
|
||||
#define CFI_CHIP_INTEL_28F320J3A 0x0016
|
||||
#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
|
||||
#define CFI_CHIP_INTEL_28F640J3A 0x0017
|
||||
#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
|
||||
#define CFI_CHIP_INTEL_28F128J3A 0x0018
|
||||
#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
|
||||
|
||||
/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
|
||||
|
||||
#define CFI_CHIP_INTEL_28F640K3 0x8801
|
||||
#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
|
||||
#define CFI_CHIP_INTEL_28F128K3 0x8802
|
||||
#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
|
||||
#define CFI_CHIP_INTEL_28F256K3 0x8803
|
||||
#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
|
||||
#define CFI_CHIP_INTEL_28F640K18 0x8805
|
||||
#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
|
||||
#define CFI_CHIP_INTEL_28F128K18 0x8806
|
||||
#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
|
||||
#define CFI_CHIP_INTEL_28F256K18 0x8807
|
||||
#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
|
||||
|
||||
#endif /* FLASH_INTEL_H */
|
188
board/mx1fs2/memsetup.S
Normal file
188
board/mx1fs2/memsetup.S
Normal file
|
@ -0,0 +1,188 @@
|
|||
/*
|
||||
* Copyright (C) 2004 Sascha Hauer, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
|
||||
* 02111-1307, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
.globl memsetup
|
||||
memsetup:
|
||||
|
||||
mov r10, lr
|
||||
|
||||
/* Change PERCLK1DIV to 14 ie 14+1 */
|
||||
ldr r0, =PCDR
|
||||
ldr r1, =CFG_PCDR_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* set MCU PLL Control Register 0 */
|
||||
|
||||
ldr r0, =MPCTL0
|
||||
ldr r1, =CFG_MPCTL0_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* set MCU PLL Control Register 1 */
|
||||
|
||||
ldr r0, =MPCTL1
|
||||
ldr r1, =CFG_MPCTL1_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* set mpll restart bit */
|
||||
ldr r0, =CSCR
|
||||
ldr r1, [r0]
|
||||
orr r1,r1,#(1<<21)
|
||||
str r1, [r0]
|
||||
|
||||
mov r2,#0x10
|
||||
1:
|
||||
mov r3,#0x2000
|
||||
2:
|
||||
subs r3,r3,#1
|
||||
bne 2b
|
||||
|
||||
subs r2,r2,#1
|
||||
bne 1b
|
||||
|
||||
/* set System PLL Control Register 0 */
|
||||
|
||||
ldr r0, =SPCTL0
|
||||
ldr r1, =CFG_SPCTL0_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* set System PLL Control Register 1 */
|
||||
|
||||
ldr r0, =SPCTL1
|
||||
ldr r1, =CFG_SPCTL1_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* set spll restart bit */
|
||||
ldr r0, =CSCR
|
||||
ldr r1, [r0]
|
||||
orr r1,r1,#(1<<22)
|
||||
str r1, [r0]
|
||||
|
||||
mov r2,#0x10
|
||||
1:
|
||||
mov r3,#0x2000
|
||||
2:
|
||||
subs r3,r3,#1
|
||||
bne 2b
|
||||
|
||||
subs r2,r2,#1
|
||||
bne 1b
|
||||
|
||||
ldr r0, =CSCR
|
||||
ldr r1, =CFG_CSCR_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPCR
|
||||
ldr r1, =CFG_GPCR_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/*
|
||||
* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
|
||||
* this.....
|
||||
*
|
||||
* It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
|
||||
* register 1, this stops it using the output of the PLL and thus runs at the
|
||||
* slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
|
||||
* use the value set in the CM_OSC registers...regardless of what you set it
|
||||
* too! Thus, although i thought i was running at 140MHz, i'm actually running
|
||||
* at 40!..
|
||||
*
|
||||
* Slapping this into my bootloader does the trick...
|
||||
*
|
||||
* MRC p15,0,r0,c1,c0,0 ; read core configuration register
|
||||
* ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
|
||||
* MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
|
||||
* register
|
||||
*
|
||||
*/
|
||||
MRC p15,0,r0,c1,c0,0
|
||||
/* ORR r0,r0,#0xC0000000 async mode */
|
||||
/* ORR r0,r0,#0x40000000 sync mode */
|
||||
ORR r0,r0,#0xC0000000
|
||||
MCR p15,0,r0,c1,c0,0
|
||||
|
||||
ldr r0, =GIUS(0)
|
||||
ldr r1, =CFG_GIUS_A_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =FMCR
|
||||
ldr r1, =CFG_FMCR_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS0U
|
||||
ldr r1, =CFG_CS0U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS0L
|
||||
ldr r1, =CFG_CS0L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS1U
|
||||
ldr r1, =CFG_CS1U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS1L
|
||||
ldr r1, =CFG_CS1L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS4U
|
||||
ldr r1, =CFG_CS4U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS4L
|
||||
ldr r1, =CFG_CS4L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS5U
|
||||
ldr r1, =CFG_CS5U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS5L
|
||||
ldr r1, =CFG_CS5L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* SDRAM Setup */
|
||||
|
||||
ldr r1,=0x00221000 /* adr of SDCTRL0 */
|
||||
ldr r0,=0x92120200
|
||||
str r0,[r1,#0] /* put in precharge command mode */
|
||||
ldr r2,=0x08200000 /* adr for precharge cmd */
|
||||
ldr r0,[r2,#0] /* precharge */
|
||||
ldr r0,=0xA2120200
|
||||
ldr r2,=0x08000000 /* start of SDRAM */
|
||||
str r0,[r1,#0] /* put in auto-refresh mode */
|
||||
ldr r0,[r2,#0] /* auto-refresh */
|
||||
ldr r0,[r2,#0] /* auto-refresh */
|
||||
ldr r0,[r2,#0] /* auto-refresh */
|
||||
ldr r0,[r2,#0] /* auto-refresh */
|
||||
ldr r0,[r2,#0] /* auto-refresh */
|
||||
ldr r0,[r2,#0] /* auto-refresh */
|
||||
ldr r0,[r2,#0] /* auto-refresh */
|
||||
ldr r0,=0xB2120200
|
||||
ldr r2,=0x08111800
|
||||
str r0,[r1,#0] /* setup for mode register of SDRAM */
|
||||
ldr r0,[r2,#0] /* program mode register */
|
||||
ldr r0,=0x82124267
|
||||
str r0,[r1,#0] /* back to normal operation */
|
||||
|
||||
mov pc,r10
|
125
board/mx1fs2/mx1fs2.c
Normal file
125
board/mx1fs2/mx1fs2.c
Normal file
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* Copyright (C) 2004 Sascha Hauer, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
|
||||
|
||||
extern void imx_gpio_mode(int gpio_mode);
|
||||
|
||||
static void logo_init(void)
|
||||
{
|
||||
imx_gpio_mode(PD15_PF_LD0);
|
||||
imx_gpio_mode(PD16_PF_LD1);
|
||||
imx_gpio_mode(PD17_PF_LD2);
|
||||
imx_gpio_mode(PD18_PF_LD3);
|
||||
imx_gpio_mode(PD19_PF_LD4);
|
||||
imx_gpio_mode(PD20_PF_LD5);
|
||||
imx_gpio_mode(PD21_PF_LD6);
|
||||
imx_gpio_mode(PD22_PF_LD7);
|
||||
imx_gpio_mode(PD23_PF_LD8);
|
||||
imx_gpio_mode(PD24_PF_LD9);
|
||||
imx_gpio_mode(PD25_PF_LD10);
|
||||
imx_gpio_mode(PD26_PF_LD11);
|
||||
imx_gpio_mode(PD27_PF_LD12);
|
||||
imx_gpio_mode(PD28_PF_LD13);
|
||||
imx_gpio_mode(PD29_PF_LD14);
|
||||
imx_gpio_mode(PD30_PF_LD15);
|
||||
imx_gpio_mode(PD14_PF_FLM_VSYNC);
|
||||
imx_gpio_mode(PD13_PF_LP_HSYNC);
|
||||
imx_gpio_mode(PD6_PF_LSCLK);
|
||||
imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_GPIO);
|
||||
imx_gpio_mode(PD11_PF_CONTRAST);
|
||||
imx_gpio_mode(PD10_PF_SPL_SPR);
|
||||
|
||||
LCDC_RMCR = 0x00000000;
|
||||
LCDC_PCR = PCR_COLOR | PCR_PBSIZ_8 | PCR_BPIX_16 | PCR_PCD(5);
|
||||
LCDC_HCR = HCR_H_WIDTH(2);
|
||||
LCDC_VCR = VCR_V_WIDTH(2);
|
||||
|
||||
LCDC_PWMR = 0x00000380; /* contrast to 0x80 middle (is best !!!) */
|
||||
LCDC_SSA = 0x10040000; /* image in flash */
|
||||
|
||||
LCDC_SIZE = SIZE_XMAX(320) | SIZE_YMAX(240); /* screen size */
|
||||
|
||||
LCDC_VPW = 0x000000A0; /* Virtual Page Width Register */
|
||||
LCDC_POS = 0x00000000; /* panning offset 0 (0 pixel offset) */
|
||||
|
||||
/* disable Cursor */
|
||||
LCDC_CPOS = 0x00000000;
|
||||
|
||||
/* fixed burst length */
|
||||
LCDC_DMACR = DMACR_BURST | DMACR_HM(8) | DMACR_TM(2);
|
||||
|
||||
/* enable LCD */
|
||||
DR(3) |= 0x00001000;
|
||||
LCDC_RMCR = RMCR_LCDC_EN;
|
||||
|
||||
}
|
||||
|
||||
int
|
||||
board_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gd->bd->bi_arch_number = 470;
|
||||
gd->bd->bi_boot_params = 0x08000100;
|
||||
serial_init();
|
||||
logo_init();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
dram_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if ( CONFIG_NR_DRAM_BANKS > 0 )
|
||||
gd->bd->bi_dram[0].start = MX1FS2_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = MX1FS2_SDRAM_1_SIZE;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* show_boot_progress: - indicate state of the boot process
|
||||
*
|
||||
* @param status: Status number - see README for details.
|
||||
*
|
||||
*/
|
||||
|
||||
void
|
||||
show_boot_progress(int status)
|
||||
{
|
||||
/* We use this as a hook to disable serial ports just before booting
|
||||
* This way we suppress the "uncompressing linux..." message
|
||||
*/
|
||||
#ifdef CONFIG_SILENT_CONSOLE
|
||||
if( status == 8) {
|
||||
if( getenv("silent") != NULL ) {
|
||||
*(volatile unsigned long *)0x206080 &= ~1;
|
||||
*(volatile unsigned long *)0x207080 &= ~1;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return;
|
||||
}
|
56
board/mx1fs2/u-boot.lds
Normal file
56
board/mx1fs2/u-boot.lds
Normal file
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm920t/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
|
@ -326,7 +326,6 @@ int phone_getc(void)
|
|||
int drv_phone_init(void)
|
||||
{
|
||||
device_t console_dev;
|
||||
char *penv;
|
||||
|
||||
console_init();
|
||||
|
||||
|
|
|
@ -256,11 +256,13 @@ long int initdram (int board_type)
|
|||
long dram_size = 0;
|
||||
extern long spd_sdram (void);
|
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||
#if 0
|
||||
#if !defined(CONFIG_RAM_AS_FLASH)
|
||||
volatile ccsr_lbc_t *lbc= &immap->im_lbc;
|
||||
sys_info_t sysinfo;
|
||||
uint temp_lbcdll = 0;
|
||||
#endif
|
||||
#endif /* 0 */
|
||||
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
|
||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
||||
#endif
|
||||
|
@ -279,7 +281,7 @@ long int initdram (int board_type)
|
|||
dram_size = fixed_sdram ();
|
||||
#endif
|
||||
|
||||
#if XXX
|
||||
#if 0
|
||||
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
|
||||
get_sys_info(&sysinfo);
|
||||
/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
|
@ -21,7 +21,27 @@
|
|||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
|
||||
-mshort-load-bytes -msoft-float
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := scb9328.o flash.o
|
||||
SOBJS := memsetup.o
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(AR) crv $@ $^
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend
|
||||
|
||||
#########################################################################
|
10
board/scb9328/config.mk
Normal file
10
board/scb9328/config.mk
Normal file
|
@ -0,0 +1,10 @@
|
|||
#
|
||||
# This config file is used for compilation of scb93328 sources
|
||||
#
|
||||
# You might change location of U-Boot in memory by setting right TEXT_BASE.
|
||||
# This allows for example having one copy located at the end of ram and stored
|
||||
# in flash device and later on while developing use other location to test
|
||||
# the code in RAM device only.
|
||||
#
|
||||
|
||||
TEXT_BASE = 0x08f00000
|
321
board/scb9328/flash.c
Normal file
321
board/scb9328/flash.c
Normal file
|
@ -0,0 +1,321 @@
|
|||
/*
|
||||
* Copyright (C) 2003 ETC s.r.o.
|
||||
*
|
||||
* This code was inspired by Marius Groeger and Kyle Harris code
|
||||
* available in other board ports for U-Boot
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* Written by Peter Figuli <peposh@etc.sk>, 2003.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "intel.h"
|
||||
|
||||
|
||||
/*
|
||||
* This code should handle CFI FLASH memory device. This code is very
|
||||
* minimalistic approach without many essential error handling code as well.
|
||||
* Because U-Boot actually is missing smart handling of FLASH device,
|
||||
* we just set flash_id to anything else to FLASH_UNKNOW, so common code
|
||||
* can call us without any restrictions.
|
||||
* TODO: Add CFI Query, to be able to determine FLASH device.
|
||||
* TODO: Add error handling code
|
||||
* NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
|
||||
* hopefully may work with other configurations.
|
||||
*/
|
||||
|
||||
#if ( SCB9328_FLASH_BUS_WIDTH == 1 )
|
||||
# define FLASH_BUS vu_char
|
||||
# if ( SCB9328_FLASH_INTERLEAVE == 1 )
|
||||
# define FLASH_CMD( x ) x
|
||||
# else
|
||||
# error "With 8bit bus only one chip is allowed"
|
||||
# endif
|
||||
|
||||
|
||||
#elif ( SCB9328_FLASH_BUS_WIDTH == 2 )
|
||||
# define FLASH_BUS vu_short
|
||||
# if ( SCB9328_FLASH_INTERLEAVE == 1 )
|
||||
# define FLASH_CMD( x ) x
|
||||
# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
|
||||
# define FLASH_CMD( x ) (( x << 8 )| x )
|
||||
# else
|
||||
# error "With 16bit bus only 1 or 2 chip(s) are allowed"
|
||||
# endif
|
||||
|
||||
|
||||
#elif ( SCB9328_FLASH_BUS_WIDTH == 4 )
|
||||
# define FLASH_BUS vu_long
|
||||
# if ( SCB9328_FLASH_INTERLEAVE == 1 )
|
||||
# define FLASH_CMD( x ) x
|
||||
# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
|
||||
# define FLASH_CMD( x ) (( x << 16 )| x )
|
||||
# elif ( SCB9328_FLASH_INTERLEAVE == 4 )
|
||||
# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
|
||||
# else
|
||||
# error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
|
||||
# endif
|
||||
|
||||
#else
|
||||
# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
|
||||
#endif
|
||||
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
|
||||
|
||||
static FLASH_BUS flash_status_reg (void)
|
||||
{
|
||||
|
||||
FLASH_BUS *addr = (FLASH_BUS *) 0;
|
||||
|
||||
*addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
|
||||
|
||||
return *addr;
|
||||
}
|
||||
|
||||
static int flash_ready (ulong timeout)
|
||||
{
|
||||
int ok = 1;
|
||||
|
||||
reset_timer_masked ();
|
||||
while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
|
||||
FLASH_CMD (CFI_INTEL_SR_READY)) {
|
||||
if (get_timer_masked () > timeout && timeout != 0) {
|
||||
ok = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return ok;
|
||||
}
|
||||
|
||||
#if ( CFG_MAX_FLASH_BANKS != 1 )
|
||||
# error "SCB9328 platform has only one flash bank!"
|
||||
#endif
|
||||
|
||||
|
||||
ulong flash_init (void)
|
||||
{
|
||||
int i;
|
||||
unsigned long address = SCB9328_FLASH_BASE;
|
||||
|
||||
flash_info[0].size = SCB9328_FLASH_BANK_SIZE;
|
||||
flash_info[0].sector_count = CFG_MAX_FLASH_SECT;
|
||||
flash_info[0].flash_id = INTEL_MANUFACT;
|
||||
memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT);
|
||||
|
||||
for (i = 0; i < CFG_MAX_FLASH_SECT; i++) {
|
||||
flash_info[0].start[i] = address;
|
||||
#ifdef SCB9328_FLASH_UNLOCK
|
||||
/* Some devices are hw locked after start. */
|
||||
*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
|
||||
*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
|
||||
flash_ready (0);
|
||||
*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
|
||||
#endif
|
||||
address += SCB9328_FLASH_SECT_SIZE;
|
||||
}
|
||||
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CFG_FLASH_BASE,
|
||||
CFG_FLASH_BASE + monitor_flash_len - 1,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR,
|
||||
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
|
||||
|
||||
return SCB9328_FLASH_BANK_SIZE;
|
||||
}
|
||||
|
||||
void flash_print_info (flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
printf (" Intel vendor\n");
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
if (!(i % 5)) {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
printf (" %08lX%s", info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
int flag, non_protected = 0, sector;
|
||||
int rc = ERR_OK;
|
||||
|
||||
FLASH_BUS *address;
|
||||
|
||||
for (sector = s_first; sector <= s_last; sector++) {
|
||||
if (!info->protect[sector]) {
|
||||
non_protected++;
|
||||
}
|
||||
}
|
||||
|
||||
if (!non_protected) {
|
||||
return ERR_PROTECTED;
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
flag = disable_interrupts ();
|
||||
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
|
||||
if (info->protect[sector]) {
|
||||
printf ("Protected sector %2d skipping...\n", sector);
|
||||
continue;
|
||||
} else {
|
||||
printf ("Erasing sector %2d ... ", sector);
|
||||
}
|
||||
|
||||
address = (FLASH_BUS *) (info->start[sector]);
|
||||
|
||||
*address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
|
||||
*address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
|
||||
if (flash_ready (CFG_FLASH_ERASE_TOUT)) {
|
||||
*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
|
||||
printf ("ok.\n");
|
||||
} else {
|
||||
*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
|
||||
rc = ERR_TIMOUT;
|
||||
printf ("timeout! Aborting...\n");
|
||||
break;
|
||||
}
|
||||
*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
|
||||
}
|
||||
if (ctrlc ())
|
||||
printf ("User Interrupt!\n");
|
||||
|
||||
/* allow flash to settle - wait 10 ms */
|
||||
udelay_masked (10000);
|
||||
if (flag) {
|
||||
enable_interrupts ();
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
|
||||
{
|
||||
FLASH_BUS *address = (FLASH_BUS *) dest;
|
||||
int rc = ERR_OK;
|
||||
int flag;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*address & data) != data) {
|
||||
return ERR_NOT_ERASED;
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
|
||||
flag = disable_interrupts ();
|
||||
|
||||
*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
|
||||
*address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
|
||||
*address = data;
|
||||
|
||||
if (!flash_ready (CFG_FLASH_WRITE_TOUT)) {
|
||||
*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
|
||||
rc = ERR_TIMOUT;
|
||||
printf ("timeout! Aborting...\n");
|
||||
}
|
||||
|
||||
*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
|
||||
if (flag) {
|
||||
enable_interrupts ();
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong read_addr, write_addr;
|
||||
FLASH_BUS data;
|
||||
int i, result = ERR_OK;
|
||||
|
||||
|
||||
read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
|
||||
write_addr = read_addr;
|
||||
if (read_addr != addr) {
|
||||
data = 0;
|
||||
for (i = 0; i < sizeof (FLASH_BUS); i++) {
|
||||
if (read_addr < addr || cnt == 0) {
|
||||
data |= *((uchar *) read_addr) << i * 8;
|
||||
} else {
|
||||
data |= (*src++) << i * 8;
|
||||
cnt--;
|
||||
}
|
||||
read_addr++;
|
||||
}
|
||||
if ((result = write_data (info, write_addr, data)) != ERR_OK) {
|
||||
return result;
|
||||
}
|
||||
write_addr += sizeof (FLASH_BUS);
|
||||
}
|
||||
for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
|
||||
if ((result = write_data (info, write_addr,
|
||||
*((FLASH_BUS *) src))) != ERR_OK) {
|
||||
return result;
|
||||
}
|
||||
write_addr += sizeof (FLASH_BUS);
|
||||
src += sizeof (FLASH_BUS);
|
||||
}
|
||||
if (cnt > 0) {
|
||||
read_addr = write_addr;
|
||||
data = 0;
|
||||
for (i = 0; i < sizeof (FLASH_BUS); i++) {
|
||||
if (cnt > 0) {
|
||||
data |= (*src++) << i * 8;
|
||||
cnt--;
|
||||
} else {
|
||||
data |= *((uchar *) read_addr) << i * 8;
|
||||
}
|
||||
read_addr++;
|
||||
}
|
||||
if ((result = write_data (info, write_addr, data)) != 0) {
|
||||
return result;
|
||||
}
|
||||
}
|
||||
return ERR_OK;
|
||||
}
|
99
board/scb9328/intel.h
Normal file
99
board/scb9328/intel.h
Normal file
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* Copyright (C) 2002 ETC s.r.o.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the ETC s.r.o. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Written by Marcel Telka <marcel@telka.sk>, 2002.
|
||||
*
|
||||
* Documentation:
|
||||
* [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
|
||||
* 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
|
||||
* [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
|
||||
* 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
|
||||
*
|
||||
* This file is taken from OpenWinCE project hosted by SourceForge.net
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef FLASH_INTEL_H
|
||||
#define FLASH_INTEL_H
|
||||
|
||||
#include <common.h>
|
||||
|
||||
/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
|
||||
|
||||
#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
|
||||
|
||||
/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
|
||||
|
||||
#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */
|
||||
|
||||
/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
|
||||
|
||||
#define CFI_CHIP_INTEL_28F320J3A 0x0016
|
||||
#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
|
||||
#define CFI_CHIP_INTEL_28F640J3A 0x0017
|
||||
#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
|
||||
#define CFI_CHIP_INTEL_28F128J3A 0x0018
|
||||
#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
|
||||
|
||||
/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
|
||||
|
||||
#define CFI_CHIP_INTEL_28F640K3 0x8801
|
||||
#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
|
||||
#define CFI_CHIP_INTEL_28F128K3 0x8802
|
||||
#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
|
||||
#define CFI_CHIP_INTEL_28F256K3 0x8803
|
||||
#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
|
||||
#define CFI_CHIP_INTEL_28F640K18 0x8805
|
||||
#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
|
||||
#define CFI_CHIP_INTEL_28F128K18 0x8806
|
||||
#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
|
||||
#define CFI_CHIP_INTEL_28F256K18 0x8807
|
||||
#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
|
||||
|
||||
#endif /* FLASH_INTEL_H */
|
203
board/scb9328/memsetup.S
Normal file
203
board/scb9328/memsetup.S
Normal file
|
@ -0,0 +1,203 @@
|
|||
/*
|
||||
* Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
|
||||
* 02111-1307, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
.globl memsetup
|
||||
memsetup:
|
||||
|
||||
mov r10, lr
|
||||
|
||||
/* Change PERCLK1DIV to 14 ie 14+1 */
|
||||
ldr r0, =PCDR
|
||||
ldr r1, =CFG_PCDR_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* set MCU PLL Control Register 0 */
|
||||
|
||||
ldr r0, =MPCTL0
|
||||
ldr r1, =CFG_MPCTL0_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* set mpll restart bit */
|
||||
ldr r0, =CSCR
|
||||
ldr r1, [r0]
|
||||
orr r1,r1,#(1<<21)
|
||||
str r1, [r0]
|
||||
|
||||
mov r2,#0x10
|
||||
1:
|
||||
mov r3,#0x2000
|
||||
2:
|
||||
subs r3,r3,#1
|
||||
bne 2b
|
||||
|
||||
subs r2,r2,#1
|
||||
bne 1b
|
||||
|
||||
/* set System PLL Control Register 0 */
|
||||
|
||||
ldr r0, =SPCTL0
|
||||
ldr r1, =CFG_SPCTL0_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* set spll restart bit */
|
||||
ldr r0, =CSCR
|
||||
ldr r1, [r0]
|
||||
orr r1,r1,#(1<<22)
|
||||
str r1, [r0]
|
||||
|
||||
mov r2,#0x10
|
||||
1:
|
||||
mov r3,#0x2000
|
||||
2:
|
||||
subs r3,r3,#1
|
||||
bne 2b
|
||||
|
||||
subs r2,r2,#1
|
||||
bne 1b
|
||||
|
||||
ldr r0, =CSCR
|
||||
ldr r1, =CFG_CSCR_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
|
||||
*this.....
|
||||
*
|
||||
* It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
|
||||
* register 1, this stops it using the output of the PLL and thus runs at the
|
||||
* slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
|
||||
* use the value set in the CM_OSC registers...regardless of what you set it
|
||||
* too! Thus, although i thought i was running at 140MHz, i'm actually running
|
||||
* at 40!..
|
||||
|
||||
* Slapping this into my bootloader does the trick...
|
||||
|
||||
* MRC p15,0,r0,c1,c0,0 ; read core configuration register
|
||||
* ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
|
||||
* MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
|
||||
* register
|
||||
*/
|
||||
MRC p15,0,r0,c1,c0,0
|
||||
ORR r0,r0,#0xC0000000
|
||||
MCR p15,0,r0,c1,c0,0
|
||||
|
||||
ldr r0, =GPR(0)
|
||||
ldr r1, =CFG_GPR_A_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GIUS(0)
|
||||
ldr r1, =CFG_GIUS_A_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
|
||||
|
||||
ldr r0, =FMCR
|
||||
ldr r1, =CFG_FMCR_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS0U
|
||||
ldr r1, =CFG_CS0U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS0L
|
||||
ldr r1, =CFG_CS0L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS1U
|
||||
ldr r1, =CFG_CS1U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS1L
|
||||
ldr r1, =CFG_CS1L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS2U
|
||||
ldr r1, =CFG_CS2U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS2L
|
||||
ldr r1, =CFG_CS2L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS3U
|
||||
ldr r1, =CFG_CS3U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS3L
|
||||
ldr r1, =CFG_CS3L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS4U
|
||||
ldr r1, =CFG_CS4U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS4L
|
||||
ldr r1, =CFG_CS4L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS5U
|
||||
ldr r1, =CFG_CS5U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =CS5L
|
||||
ldr r1, =CFG_CS5L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* SDRAM Setup */
|
||||
|
||||
ldr r0, =SDCTL0
|
||||
ldr r1, =PRECHARGE_CMD
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =0x08200000
|
||||
ldr r1, =0x0 /* Issue Precharge all Command */
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =SDCTL0
|
||||
ldr r1, =AUTOREFRESH_CMD
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =0x08000000
|
||||
ldr r1, =0x0 /* Issue AutoRefresh Command */
|
||||
str r1, [r0]
|
||||
str r1, [r0]
|
||||
str r1, [r0]
|
||||
str r1, [r0]
|
||||
str r1, [r0]
|
||||
str r1, [r0]
|
||||
str r1, [r0]
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =SDCTL0
|
||||
ldr r1, =0xb10a8300
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =0x08223000 /* CAS Latency 2 */
|
||||
ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =SDCTL0
|
||||
ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
|
||||
str r1, [r0]
|
||||
|
||||
mov pc,r10
|
73
board/scb9328/scb9328.c
Normal file
73
board/scb9328/scb9328.c
Normal file
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_SHOW_BOOT_PROGRESS
|
||||
# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
|
||||
#else
|
||||
# define SHOW_BOOT_PROGRESS(arg)
|
||||
#endif
|
||||
|
||||
int board_init( void ){
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gd->bd->bi_arch_number = 508;
|
||||
gd->bd->bi_boot_params = 0x08000100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init( void ){
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if ( CONFIG_NR_DRAM_BANKS > 0 )
|
||||
gd->bd->bi_dram[0].start = SCB9328_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE;
|
||||
#endif
|
||||
#if ( CONFIG_NR_DRAM_BANKS > 1 )
|
||||
gd->bd->bi_dram[1].start = SCB9328_SDRAM_2;
|
||||
gd->bd->bi_dram[1].size = SCB9328_SDRAM_2_SIZE;
|
||||
#endif
|
||||
#if ( CONFIG_NR_DRAM_BANKS > 2 )
|
||||
gd->bd->bi_dram[2].start = SCB9328_SDRAM_3;
|
||||
gd->bd->bi_dram[2].size = SCB9328_SDRAM_3_SIZE;
|
||||
#endif
|
||||
#if ( CONFIG_NR_DRAM_BANKS > 3 )
|
||||
gd->bd->bi_dram[3].start = SCB9328_SDRAM_4;
|
||||
gd->bd->bi_dram[3].size = SCB9328_SDRAM_4_SIZE;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* show_boot_progress: - indicate state of the boot process
|
||||
*
|
||||
* @param status: Status number - see README for details.
|
||||
*
|
||||
* The CSB226 does only have 3 LEDs, so we switch them on at the most
|
||||
* important states (1, 5, 15).
|
||||
*/
|
||||
|
||||
void show_boot_progress (int status)
|
||||
{
|
||||
return;
|
||||
}
|
56
board/scb9328/u-boot.lds
Normal file
56
board/scb9328/u-boot.lds
Normal file
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm920t/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
|
@ -265,7 +265,7 @@ static const S1D_REGS init_regs [] =
|
|||
void video_get_info_str (int line_number, char *info)
|
||||
{
|
||||
if (line_number == 1) {
|
||||
#if CONFIG_MGT5100
|
||||
#ifdef CONFIG_MGT5100
|
||||
strcpy (info, " Total5100");
|
||||
#elif CONFIG_TOTAL5200_REV==1
|
||||
strcpy (info, " Total5200");
|
||||
|
|
|
@ -45,7 +45,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o \
|
|||
env_nand.o env_dataflash.o env_flash.o env_eeprom.o env_nvram.o env_nowhere.o exports.o \
|
||||
flash.o fpga.o \
|
||||
hush.o kgdb.o lists.o lynxkdi.o memsize.o miiphybb.o miiphyutil.o \
|
||||
s_record.o soft_i2c.o soft_spi.o spartan2.o \
|
||||
s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o \
|
||||
usb.o usb_kbd.o usb_storage.o \
|
||||
virtex2.o xilinx.o circbuf.o
|
||||
|
||||
|
|
|
@ -123,14 +123,15 @@ static int bmp_info(ulong addr)
|
|||
*/
|
||||
static int bmp_display(ulong addr, int x, int y)
|
||||
{
|
||||
#ifdef CONFIG_LCD
|
||||
extern int lcd_display_bitmap (ulong, int, int);
|
||||
#if defined(CONFIG_LCD)
|
||||
extern int lcd_display_bitmap (ulong, int, int);
|
||||
|
||||
return (lcd_display_bitmap (addr, x, y));
|
||||
#endif
|
||||
#ifdef CONFIG_VIDEO
|
||||
#elif defined(CONFIG_VIDEO)
|
||||
extern int video_display_bitmap (ulong, int, int);
|
||||
return (video_display_bitmap (addr, x, y));
|
||||
#else
|
||||
# error bmp_display() requires CONFIG_LCD or CONFIG_VIDEO
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
@ -43,6 +43,7 @@
|
|||
#include <command.h>
|
||||
#include <environment.h>
|
||||
#include <watchdog.h>
|
||||
#include <serial.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <asm/byteorder.h>
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NET)
|
||||
|
@ -216,6 +217,11 @@ int _do_setenv (int flag, int argc, char *argv[])
|
|||
/* Try assigning specified device */
|
||||
if (console_assign (console, argv[2]) < 0)
|
||||
return 1;
|
||||
|
||||
#ifdef CONFIG_SERIAL_MULTI
|
||||
if (serial_assign (argv[2]) < 0)
|
||||
return 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
#include <stdarg.h>
|
||||
#include <malloc.h>
|
||||
#include <devices.h>
|
||||
#include <serial.h>
|
||||
#ifdef CONFIG_LOGBUFFER
|
||||
#include <logbuff.h>
|
||||
#endif
|
||||
|
@ -194,6 +195,9 @@ int devices_init (void)
|
|||
drv_logbuff_init ();
|
||||
#endif
|
||||
drv_system_init ();
|
||||
#ifdef CONFIG_SERIAL_MULTI
|
||||
serial_devices_init ();
|
||||
#endif
|
||||
#ifdef CONFIG_USB_TTY
|
||||
drv_usbtty_init ();
|
||||
#endif
|
||||
|
|
196
common/serial.c
Normal file
196
common/serial.c
Normal file
|
@ -0,0 +1,196 @@
|
|||
/*
|
||||
* (C) Copyright 2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <serial.h>
|
||||
#include <devices.h>
|
||||
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
|
||||
static struct serial_device *serial_devices = NULL;
|
||||
static struct serial_device *serial_current = NULL;
|
||||
|
||||
#ifndef CONFIG_LWMON
|
||||
struct serial_device * default_serial_console (void)
|
||||
{
|
||||
#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
|
||||
return &serial_smc_device;
|
||||
#elif defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
|
||||
|| defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
|
||||
return &serial_scc_device;
|
||||
#else
|
||||
#error No default console
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
static int serial_register(struct serial_device* dev)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
dev->init += gd->reloc_off;
|
||||
dev->setbrg += gd->reloc_off;
|
||||
dev->getc += gd->reloc_off;
|
||||
dev->tstc += gd->reloc_off;
|
||||
dev->putc += gd->reloc_off;
|
||||
dev->puts += gd->reloc_off;
|
||||
|
||||
dev->next = serial_devices;
|
||||
serial_devices = dev;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void serial_initialize(void)
|
||||
{
|
||||
#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
|
||||
serial_register(&serial_smc_device);
|
||||
#endif
|
||||
#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
|
||||
|| defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
|
||||
serial_register(&serial_scc_device);
|
||||
#endif
|
||||
|
||||
serial_assign(default_serial_console()->name);
|
||||
}
|
||||
|
||||
void serial_devices_init(void)
|
||||
{
|
||||
device_t dev;
|
||||
struct serial_device *s = serial_devices;
|
||||
|
||||
while (s)
|
||||
{
|
||||
memset (&dev, 0, sizeof (dev));
|
||||
|
||||
strcpy (dev.name, s->name);
|
||||
dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
|
||||
|
||||
dev.start = s->init;
|
||||
dev.putc = s->putc;
|
||||
dev.puts = s->puts;
|
||||
dev.getc = s->getc;
|
||||
dev.tstc = s->tstc;
|
||||
|
||||
device_register (&dev);
|
||||
|
||||
s = s->next;
|
||||
}
|
||||
}
|
||||
|
||||
int serial_assign(char * name)
|
||||
{
|
||||
struct serial_device *s;
|
||||
|
||||
for (s = serial_devices; s; s = s->next)
|
||||
{
|
||||
if (strcmp(s->name, name) == 0)
|
||||
{
|
||||
serial_current = s;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void serial_reinit_all(void)
|
||||
{
|
||||
struct serial_device *s;
|
||||
|
||||
for (s = serial_devices; s; s = s->next)
|
||||
{
|
||||
s->init();
|
||||
}
|
||||
}
|
||||
|
||||
int serial_init(void)
|
||||
{
|
||||
if (!serial_current)
|
||||
{
|
||||
struct serial_device *dev = default_serial_console();
|
||||
return dev->init();
|
||||
}
|
||||
|
||||
return serial_current->init();
|
||||
}
|
||||
|
||||
void serial_setbrg(void)
|
||||
{
|
||||
if (!serial_current)
|
||||
{
|
||||
struct serial_device *dev = default_serial_console();
|
||||
dev->setbrg();
|
||||
return;
|
||||
}
|
||||
|
||||
serial_current->setbrg();
|
||||
}
|
||||
|
||||
int serial_getc(void)
|
||||
{
|
||||
if (!serial_current)
|
||||
{
|
||||
struct serial_device *dev = default_serial_console();
|
||||
return dev->getc();
|
||||
}
|
||||
|
||||
return serial_current->getc();
|
||||
}
|
||||
|
||||
int serial_tstc(void)
|
||||
{
|
||||
if (!serial_current)
|
||||
{
|
||||
struct serial_device *dev = default_serial_console();
|
||||
return dev->tstc();
|
||||
}
|
||||
|
||||
return serial_current->tstc();
|
||||
}
|
||||
|
||||
void serial_putc(const char c)
|
||||
{
|
||||
if (!serial_current)
|
||||
{
|
||||
struct serial_device *dev = default_serial_console();
|
||||
dev->putc(c);
|
||||
return;
|
||||
}
|
||||
|
||||
serial_current->putc(c);
|
||||
}
|
||||
|
||||
void serial_puts(const char *s)
|
||||
{
|
||||
if (!serial_current)
|
||||
{
|
||||
struct serial_device *dev = default_serial_console();
|
||||
dev->puts(s);
|
||||
return;
|
||||
}
|
||||
|
||||
serial_current->puts(s);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SERIAL_MULTI */
|
|
@ -41,8 +41,6 @@ int cpu_init (void)
|
|||
* setup up stacks if necessary
|
||||
*/
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
|
||||
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
|
||||
#endif
|
||||
|
|
|
@ -26,7 +26,11 @@ include $(TOPDIR)/config.mk
|
|||
LIB = lib$(CPU).a
|
||||
|
||||
START = start.o
|
||||
OBJS = serial.o interrupts.o cpu.o speed.o usb_ohci.o
|
||||
OBJS = cpu.o \
|
||||
imx_generic.o imx_interrupts.o imx_speed.o \
|
||||
interrupts.o \
|
||||
s3c24x0_interrupts.o s3c24x0_serial.o s3c24x0_speed.o \
|
||||
usb_ohci.o
|
||||
|
||||
all: .depend $(START) $(LIB)
|
||||
|
||||
|
|
90
cpu/arm920t/imx_generic.c
Normal file
90
cpu/arm920t/imx_generic.c
Normal file
|
@ -0,0 +1,90 @@
|
|||
/*
|
||||
* arch/arm/mach-imx/generic.c
|
||||
*
|
||||
* author: Sascha Hauer
|
||||
* Created: april 20th, 2004
|
||||
* Copyright: Synertronixx GmbH
|
||||
*
|
||||
* Common code for i.MX machines
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_IMX
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
void imx_gpio_mode(int gpio_mode)
|
||||
{
|
||||
unsigned int pin = gpio_mode & GPIO_PIN_MASK;
|
||||
unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5;
|
||||
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10;
|
||||
unsigned int tmp;
|
||||
|
||||
/* Pullup enable */
|
||||
if(gpio_mode & GPIO_PUEN)
|
||||
PUEN(port) |= (1<<pin);
|
||||
else
|
||||
PUEN(port) &= ~(1<<pin);
|
||||
|
||||
/* Data direction */
|
||||
if(gpio_mode & GPIO_OUT)
|
||||
DDIR(port) |= 1<<pin;
|
||||
else
|
||||
DDIR(port) &= ~(1<<pin);
|
||||
|
||||
/* Primary / alternate function */
|
||||
if(gpio_mode & GPIO_AF)
|
||||
GPR(port) |= (1<<pin);
|
||||
else
|
||||
GPR(port) &= ~(1<<pin);
|
||||
|
||||
/* use as gpio? */
|
||||
if( ocr == 3 )
|
||||
GIUS(port) |= (1<<pin);
|
||||
else
|
||||
GIUS(port) &= ~(1<<pin);
|
||||
|
||||
/* Output / input configuration */
|
||||
/* FIXME: I'm not very sure about OCR and ICONF, someone
|
||||
* should have a look over it
|
||||
*/
|
||||
if(pin<16) {
|
||||
tmp = OCR1(port);
|
||||
tmp &= ~( 3<<(pin*2));
|
||||
tmp |= (ocr << (pin*2));
|
||||
OCR1(port) = tmp;
|
||||
|
||||
if( gpio_mode & GPIO_AOUT )
|
||||
ICONFA1(port) &= ~( 3<<(pin*2));
|
||||
if( gpio_mode & GPIO_BOUT )
|
||||
ICONFB1(port) &= ~( 3<<(pin*2));
|
||||
} else {
|
||||
tmp = OCR2(port);
|
||||
tmp &= ~( 3<<((pin-16)*2));
|
||||
tmp |= (ocr << ((pin-16)*2));
|
||||
OCR2(port) = tmp;
|
||||
|
||||
if( gpio_mode & GPIO_AOUT )
|
||||
ICONFA2(port) &= ~( 3<<((pin-16)*2));
|
||||
if( gpio_mode & GPIO_BOUT )
|
||||
ICONFB2(port) &= ~( 3<<((pin-16)*2));
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_IMX */
|
117
cpu/arm920t/imx_interrupts.c
Normal file
117
cpu/arm920t/imx_interrupts.c
Normal file
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Alex Zuepke <azu@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#if defined (CONFIG_IMX)
|
||||
|
||||
#include <arm920t.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
int interrupt_init (void)
|
||||
{
|
||||
int i;
|
||||
/* setup GP Timer 1 */
|
||||
TCTL1 = TCTL_SWR;
|
||||
for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
|
||||
TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
|
||||
TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
|
||||
|
||||
reset_timer_masked();
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* timer without interrupts
|
||||
*/
|
||||
|
||||
void reset_timer (void)
|
||||
{
|
||||
reset_timer_masked ();
|
||||
}
|
||||
|
||||
ulong get_timer (ulong base)
|
||||
{
|
||||
return get_timer_masked ();
|
||||
}
|
||||
|
||||
void set_timer (ulong t)
|
||||
{
|
||||
/* nop */
|
||||
}
|
||||
|
||||
void reset_timer_masked (void)
|
||||
{
|
||||
TCTL1 &= ~TCTL_TEN;
|
||||
TCTL1 |= TCTL_TEN; /* Enable timer */
|
||||
}
|
||||
|
||||
ulong get_timer_masked (void)
|
||||
{
|
||||
return TCN1;
|
||||
}
|
||||
|
||||
void udelay_masked (unsigned long usec)
|
||||
{
|
||||
ulong start = get_timer_masked();
|
||||
|
||||
while (get_timer_masked () - start < usec )
|
||||
/*NOP*/;
|
||||
}
|
||||
|
||||
void udelay (unsigned long usec)
|
||||
{
|
||||
udelay_masked(usec);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long).
|
||||
* On ARM it just returns the timer value.
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
return get_timer(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On ARM it returns the number of timer ticks per second.
|
||||
*/
|
||||
ulong get_tbclk (void)
|
||||
{
|
||||
ulong tbclk;
|
||||
|
||||
tbclk = CFG_HZ;
|
||||
|
||||
return tbclk;
|
||||
}
|
||||
|
||||
#endif /* defined (CONFIG_IMX) */
|
102
cpu/arm920t/imx_speed.c
Normal file
102
cpu/arm920t/imx_speed.c
Normal file
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
*
|
||||
* (c) 2004 Sascha Hauer <sascha@saschahauer.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#if defined (CONFIG_IMX)
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* NOTE: This describes the proper use of this file.
|
||||
*
|
||||
* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
|
||||
* SH FIXME: 16780000 in our case
|
||||
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
|
||||
* the specified bus in HZ.
|
||||
*/
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
ulong get_systemPLLCLK(void)
|
||||
{
|
||||
/* FIXME: We assume System_SEL = 0 here */
|
||||
u32 spctl0 = SPCTL0;
|
||||
u32 mfi = (spctl0 >> 10) & 0xf;
|
||||
u32 mfn = spctl0 & 0x3f;
|
||||
u32 mfd = (spctl0 >> 16) & 0x3f;
|
||||
u32 pd = (spctl0 >> 26) & 0xf;
|
||||
|
||||
mfi = mfi<=5 ? 5 : mfi;
|
||||
|
||||
return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
|
||||
}
|
||||
|
||||
ulong get_mcuPLLCLK(void)
|
||||
{
|
||||
/* FIXME: We assume System_SEL = 0 here */
|
||||
u32 mpctl0 = MPCTL0;
|
||||
u32 mfi = (mpctl0 >> 10) & 0xf;
|
||||
u32 mfn = mpctl0 & 0x3f;
|
||||
u32 mfd = (mpctl0 >> 16) & 0x3f;
|
||||
u32 pd = (mpctl0 >> 26) & 0xf;
|
||||
|
||||
mfi = mfi<=5 ? 5 : mfi;
|
||||
|
||||
return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
|
||||
}
|
||||
|
||||
ulong get_FCLK(void)
|
||||
{
|
||||
return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK();
|
||||
}
|
||||
|
||||
/* return HCLK frequency */
|
||||
ulong get_HCLK(void)
|
||||
{
|
||||
u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
|
||||
printf("bclkdiv: %d\n", bclkdiv);
|
||||
return get_systemPLLCLK() / bclkdiv;
|
||||
}
|
||||
|
||||
/* return BCLK frequency */
|
||||
ulong get_BCLK(void)
|
||||
{
|
||||
return get_HCLK();
|
||||
}
|
||||
|
||||
ulong get_PERCLK1(void)
|
||||
{
|
||||
return get_systemPLLCLK() / (((PCDR) & 0xf)+1);
|
||||
}
|
||||
|
||||
ulong get_PERCLK2(void)
|
||||
{
|
||||
return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1);
|
||||
}
|
||||
|
||||
ulong get_PERCLK3(void)
|
||||
{
|
||||
return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1);
|
||||
}
|
||||
|
||||
#endif /* defined (CONFIG_IMX) */
|
|
@ -30,25 +30,11 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <arm920t.h>
|
||||
#if defined(CONFIG_S3C2400)
|
||||
#include <s3c2400.h>
|
||||
#elif defined(CONFIG_S3C2410)
|
||||
#include <s3c2410.h>
|
||||
#endif
|
||||
|
||||
#include <arm920t.h>
|
||||
#include <asm/proc-armv/ptrace.h>
|
||||
|
||||
extern void reset_cpu(ulong addr);
|
||||
int timer_load_val = 0;
|
||||
|
||||
/* macro to read the 16 bit timer */
|
||||
static inline ulong READ_TIMER(void)
|
||||
{
|
||||
S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
|
||||
|
||||
return (timers->TCNTO4 & 0xffff);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* enable IRQ interrupts */
|
||||
|
@ -182,130 +168,3 @@ void do_irq (struct pt_regs *pt_regs)
|
|||
show_regs (pt_regs);
|
||||
bad_mode ();
|
||||
}
|
||||
|
||||
static ulong timestamp;
|
||||
static ulong lastdec;
|
||||
|
||||
int interrupt_init (void)
|
||||
{
|
||||
S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
|
||||
|
||||
/* use PWM Timer 4 because it has no output */
|
||||
/* prescaler for Timer 4 is 16 */
|
||||
timers->TCFG0 = 0x0f00;
|
||||
if (timer_load_val == 0)
|
||||
{
|
||||
/*
|
||||
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
|
||||
* (default) and prescaler = 16. Should be 10390
|
||||
* @33.25MHz and 15625 @ 50 MHz
|
||||
*/
|
||||
timer_load_val = get_PCLK()/(2 * 16 * 100);
|
||||
}
|
||||
/* load value for 10 ms timeout */
|
||||
lastdec = timers->TCNTB4 = timer_load_val;
|
||||
/* auto load, manual update of Timer 4 */
|
||||
timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
|
||||
/* auto load, start Timer 4 */
|
||||
timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
|
||||
timestamp = 0;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* timer without interrupts
|
||||
*/
|
||||
|
||||
void reset_timer (void)
|
||||
{
|
||||
reset_timer_masked ();
|
||||
}
|
||||
|
||||
ulong get_timer (ulong base)
|
||||
{
|
||||
return get_timer_masked () - base;
|
||||
}
|
||||
|
||||
void set_timer (ulong t)
|
||||
{
|
||||
timestamp = t;
|
||||
}
|
||||
|
||||
void udelay (unsigned long usec)
|
||||
{
|
||||
ulong tmo;
|
||||
ulong start = get_timer(0);
|
||||
|
||||
tmo = usec / 1000;
|
||||
tmo *= (timer_load_val * 100);
|
||||
tmo /= 1000;
|
||||
|
||||
while ((ulong)(get_timer_masked () - start) < tmo)
|
||||
/*NOP*/;
|
||||
}
|
||||
|
||||
void reset_timer_masked (void)
|
||||
{
|
||||
/* reset time */
|
||||
lastdec = READ_TIMER();
|
||||
timestamp = 0;
|
||||
}
|
||||
|
||||
ulong get_timer_masked (void)
|
||||
{
|
||||
ulong now = READ_TIMER();
|
||||
|
||||
if (lastdec >= now) {
|
||||
/* normal mode */
|
||||
timestamp += lastdec - now;
|
||||
} else {
|
||||
/* we have an overflow ... */
|
||||
timestamp += lastdec + timer_load_val - now;
|
||||
}
|
||||
lastdec = now;
|
||||
|
||||
return timestamp;
|
||||
}
|
||||
|
||||
void udelay_masked (unsigned long usec)
|
||||
{
|
||||
ulong tmo;
|
||||
|
||||
tmo = usec / 1000;
|
||||
tmo *= (timer_load_val * 100);
|
||||
tmo /= 1000;
|
||||
|
||||
reset_timer_masked ();
|
||||
|
||||
while (get_timer_masked () < tmo)
|
||||
/*NOP*/;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long).
|
||||
* On ARM it just returns the timer value.
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
return get_timer(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On ARM it returns the number of timer ticks per second.
|
||||
*/
|
||||
ulong get_tbclk (void)
|
||||
{
|
||||
ulong tbclk;
|
||||
|
||||
#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
|
||||
tbclk = timer_load_val * 100;
|
||||
#elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9)
|
||||
tbclk = CFG_HZ;
|
||||
#else
|
||||
# error "tbclk not configured"
|
||||
#endif
|
||||
|
||||
return tbclk;
|
||||
}
|
||||
|
|
180
cpu/arm920t/s3c24x0_interrupts.c
Normal file
180
cpu/arm920t/s3c24x0_interrupts.c
Normal file
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Alex Zuepke <azu@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
|
||||
|
||||
#include <arm920t.h>
|
||||
#if defined(CONFIG_S3C2400)
|
||||
#include <s3c2400.h>
|
||||
#elif defined(CONFIG_S3C2410)
|
||||
#include <s3c2410.h>
|
||||
#endif
|
||||
|
||||
extern void reset_cpu(ulong addr);
|
||||
int timer_load_val = 0;
|
||||
|
||||
/* macro to read the 16 bit timer */
|
||||
static inline ulong READ_TIMER(void)
|
||||
{
|
||||
S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
|
||||
|
||||
return (timers->TCNTO4 & 0xffff);
|
||||
}
|
||||
|
||||
static ulong timestamp;
|
||||
static ulong lastdec;
|
||||
|
||||
int interrupt_init (void)
|
||||
{
|
||||
S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
|
||||
|
||||
/* use PWM Timer 4 because it has no output */
|
||||
/* prescaler for Timer 4 is 16 */
|
||||
timers->TCFG0 = 0x0f00;
|
||||
if (timer_load_val == 0)
|
||||
{
|
||||
/*
|
||||
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
|
||||
* (default) and prescaler = 16. Should be 10390
|
||||
* @33.25MHz and 15625 @ 50 MHz
|
||||
*/
|
||||
timer_load_val = get_PCLK()/(2 * 16 * 100);
|
||||
}
|
||||
/* load value for 10 ms timeout */
|
||||
lastdec = timers->TCNTB4 = timer_load_val;
|
||||
/* auto load, manual update of Timer 4 */
|
||||
timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
|
||||
/* auto load, start Timer 4 */
|
||||
timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
|
||||
timestamp = 0;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* timer without interrupts
|
||||
*/
|
||||
|
||||
void reset_timer (void)
|
||||
{
|
||||
reset_timer_masked ();
|
||||
}
|
||||
|
||||
ulong get_timer (ulong base)
|
||||
{
|
||||
return get_timer_masked () - base;
|
||||
}
|
||||
|
||||
void set_timer (ulong t)
|
||||
{
|
||||
timestamp = t;
|
||||
}
|
||||
|
||||
void udelay (unsigned long usec)
|
||||
{
|
||||
ulong tmo;
|
||||
ulong start = get_timer(0);
|
||||
|
||||
tmo = usec / 1000;
|
||||
tmo *= (timer_load_val * 100);
|
||||
tmo /= 1000;
|
||||
|
||||
while ((ulong)(get_timer_masked () - start) < tmo)
|
||||
/*NOP*/;
|
||||
}
|
||||
|
||||
void reset_timer_masked (void)
|
||||
{
|
||||
/* reset time */
|
||||
lastdec = READ_TIMER();
|
||||
timestamp = 0;
|
||||
}
|
||||
|
||||
ulong get_timer_masked (void)
|
||||
{
|
||||
ulong now = READ_TIMER();
|
||||
|
||||
if (lastdec >= now) {
|
||||
/* normal mode */
|
||||
timestamp += lastdec - now;
|
||||
} else {
|
||||
/* we have an overflow ... */
|
||||
timestamp += lastdec + timer_load_val - now;
|
||||
}
|
||||
lastdec = now;
|
||||
|
||||
return timestamp;
|
||||
}
|
||||
|
||||
void udelay_masked (unsigned long usec)
|
||||
{
|
||||
ulong tmo;
|
||||
|
||||
tmo = usec / 1000;
|
||||
tmo *= (timer_load_val * 100);
|
||||
tmo /= 1000;
|
||||
|
||||
reset_timer_masked ();
|
||||
|
||||
while (get_timer_masked () < tmo)
|
||||
/*NOP*/;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long).
|
||||
* On ARM it just returns the timer value.
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
return get_timer(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On ARM it returns the number of timer ticks per second.
|
||||
*/
|
||||
ulong get_tbclk (void)
|
||||
{
|
||||
ulong tbclk;
|
||||
|
||||
#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
|
||||
tbclk = timer_load_val * 100;
|
||||
#elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9)
|
||||
tbclk = CFG_HZ;
|
||||
#else
|
||||
# error "tbclk not configured"
|
||||
#endif
|
||||
|
||||
return tbclk;
|
||||
}
|
||||
|
||||
#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
|
|
@ -1,24 +1,26 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
/*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
|
||||
|
||||
#if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB)
|
||||
#include <s3c2400.h>
|
||||
#elif defined(CONFIG_S3C2410)
|
||||
|
@ -176,3 +178,5 @@ serial_puts (const char *s)
|
|||
serial_putc (*s++);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2002
|
||||
* (C) Copyright 2001-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
|
@ -30,6 +30,8 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
|
||||
|
||||
#if defined(CONFIG_S3C2400)
|
||||
#include <s3c2400.h>
|
||||
#elif defined(CONFIG_S3C2410)
|
||||
|
@ -95,3 +97,5 @@ ulong get_UCLK(void)
|
|||
{
|
||||
return(get_PLLCLK(UPLL));
|
||||
}
|
||||
|
||||
#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
|
|
@ -118,20 +118,17 @@ reset:
|
|||
|
||||
/* turn off the watchdog */
|
||||
#if defined(CONFIG_S3C2400)
|
||||
#define pWTCON 0x15300000
|
||||
/* Interupt-Controller base addresses */
|
||||
#define INTMSK 0x14400008
|
||||
/* clock divisor register */
|
||||
#define CLKDIVN 0x14800014
|
||||
# define pWTCON 0x15300000
|
||||
# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
|
||||
# define CLKDIVN 0x14800014 /* clock divisor register */
|
||||
#elif defined(CONFIG_S3C2410)
|
||||
#define pWTCON 0x53000000
|
||||
/* Interupt-Controller base addresses */
|
||||
#define INTMSK 0x4A000008
|
||||
#define INTSUBMSK 0x4A00001C
|
||||
/* clock divisor register */
|
||||
#define CLKDIVN 0x4C000014
|
||||
# define pWTCON 0x53000000
|
||||
# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
|
||||
# define INTSUBMSK 0x4A00001C
|
||||
# define CLKDIVN 0x4C000014 /* clock divisor register */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
|
||||
ldr r0, =pWTCON
|
||||
mov r1, #0x0
|
||||
str r1, [r0]
|
||||
|
@ -142,17 +139,18 @@ reset:
|
|||
mov r1, #0xffffffff
|
||||
ldr r0, =INTMSK
|
||||
str r1, [r0]
|
||||
#if defined(CONFIG_S3C2410)
|
||||
# if defined(CONFIG_S3C2410)
|
||||
ldr r1, =0x3ff
|
||||
ldr r0, =INTSUBMSK
|
||||
str r1, [r0]
|
||||
#endif
|
||||
# endif
|
||||
|
||||
/* FCLK:HCLK:PCLK = 1:2:4 */
|
||||
/* default FCLK is 120 MHz ! */
|
||||
ldr r0, =CLKDIVN
|
||||
mov r1, #3
|
||||
str r1, [r0]
|
||||
#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
|
||||
|
||||
/*
|
||||
* we do sys-critical inits only at reboot,
|
||||
|
|
183
cpu/mc9328/cpu.c
183
cpu/mc9328/cpu.c
|
@ -1,183 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* CPU specific code
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <arm920t.h>
|
||||
|
||||
/* read co-processor 15, register #1 (control register) */
|
||||
static unsigned long read_p15_c1 (void)
|
||||
{
|
||||
unsigned long value;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
|
||||
: "=r" (value)
|
||||
:
|
||||
: "memory");
|
||||
|
||||
#ifdef MMU_DEBUG
|
||||
printf ("p15/c1 is = %08lx\n", value);
|
||||
#endif
|
||||
return value;
|
||||
}
|
||||
|
||||
/* write to co-processor 15, register #1 (control register) */
|
||||
static void write_p15_c1 (unsigned long value)
|
||||
{
|
||||
#ifdef MMU_DEBUG
|
||||
printf ("write %08lx to p15/c1\n", value);
|
||||
#endif
|
||||
__asm__ __volatile__(
|
||||
"mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
|
||||
:
|
||||
: "r" (value)
|
||||
: "memory");
|
||||
|
||||
read_p15_c1 ();
|
||||
}
|
||||
|
||||
static void cp_delay (void)
|
||||
{
|
||||
volatile int i;
|
||||
|
||||
/* copro seems to need some delay between reading and writing */
|
||||
for (i = 0; i < 100; i++);
|
||||
}
|
||||
|
||||
/* See also ARM Ref. Man. */
|
||||
#define C1_MMU (1<<0) /* mmu off/on */
|
||||
#define C1_ALIGN (1<<1) /* alignment faults off/on */
|
||||
#define C1_DC (1<<2) /* dcache off/on */
|
||||
#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
|
||||
#define C1_SYS_PROT (1<<8) /* system protection */
|
||||
#define C1_ROM_PROT (1<<9) /* ROM protection */
|
||||
#define C1_IC (1<<12) /* icache off/on */
|
||||
#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
|
||||
#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
|
||||
|
||||
int cpu_init (void)
|
||||
{
|
||||
/*
|
||||
* setup up stacks if necessary
|
||||
*/
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
|
||||
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int cleanup_before_linux (void)
|
||||
{
|
||||
/*
|
||||
* this function is called just before we call linux
|
||||
* it prepares the processor for linux
|
||||
*
|
||||
* we turn off caches etc ...
|
||||
*/
|
||||
|
||||
unsigned long i;
|
||||
|
||||
disable_interrupts ();
|
||||
|
||||
/* turn off I/D-cache */
|
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
|
||||
i &= ~(C1_DC | C1_IC);
|
||||
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
|
||||
|
||||
/* flush I/D-cache */
|
||||
i = 0;
|
||||
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
|
||||
return (0);
|
||||
}
|
||||
|
||||
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
extern void reset_cpu (ulong addr);
|
||||
|
||||
disable_interrupts ();
|
||||
reset_cpu (0);
|
||||
/*NOTREACHED*/
|
||||
return (0);
|
||||
}
|
||||
|
||||
void icache_enable (void)
|
||||
{
|
||||
ulong reg;
|
||||
|
||||
reg = read_p15_c1 ();
|
||||
cp_delay ();
|
||||
write_p15_c1 (reg | C1_IC);
|
||||
}
|
||||
|
||||
void icache_disable (void)
|
||||
{
|
||||
ulong reg;
|
||||
|
||||
reg = read_p15_c1 ();
|
||||
cp_delay ();
|
||||
write_p15_c1 (reg & ~C1_IC);
|
||||
}
|
||||
|
||||
int icache_status (void)
|
||||
{
|
||||
return (read_p15_c1 () & C1_IC) != 0;
|
||||
}
|
||||
|
||||
#ifdef USE_920T_MMU
|
||||
/* It makes no sense to use the dcache if the MMU is not enabled */
|
||||
void dcache_enable (void)
|
||||
{
|
||||
ulong reg;
|
||||
|
||||
reg = read_p15_c1 ();
|
||||
cp_delay ();
|
||||
write_p15_c1 (reg | C1_DC);
|
||||
}
|
||||
|
||||
void dcache_disable (void)
|
||||
{
|
||||
ulong reg;
|
||||
|
||||
reg = read_p15_c1 ();
|
||||
cp_delay ();
|
||||
reg &= ~C1_DC;
|
||||
write_p15_c1 (reg);
|
||||
}
|
||||
|
||||
int dcache_status (void)
|
||||
{
|
||||
return (read_p15_c1 () & C1_DC) != 0;
|
||||
}
|
||||
#endif
|
|
@ -1,249 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Alex Zuepke <azu@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <arm920t.h>
|
||||
#include <mc9328.h>
|
||||
|
||||
#include <asm/proc-armv/ptrace.h>
|
||||
|
||||
extern void reset_cpu(ulong addr);
|
||||
int timer_load_val = 0;
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* enable IRQ interrupts */
|
||||
void enable_interrupts (void)
|
||||
{
|
||||
unsigned long temp;
|
||||
__asm__ __volatile__("mrs %0, cpsr\n"
|
||||
"bic %0, %0, #0x80\n"
|
||||
"msr cpsr_c, %0"
|
||||
: "=r" (temp)
|
||||
:
|
||||
: "memory");
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* disable IRQ/FIQ interrupts
|
||||
* returns true if interrupts had been enabled before we disabled them
|
||||
*/
|
||||
int disable_interrupts (void)
|
||||
{
|
||||
unsigned long old,temp;
|
||||
__asm__ __volatile__("mrs %0, cpsr\n"
|
||||
"orr %1, %0, #0xc0\n"
|
||||
"msr cpsr_c, %1"
|
||||
: "=r" (old), "=r" (temp)
|
||||
:
|
||||
: "memory");
|
||||
return (old & 0x80) == 0;
|
||||
}
|
||||
#else
|
||||
void enable_interrupts (void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
int disable_interrupts (void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
void bad_mode (void)
|
||||
{
|
||||
panic ("Resetting CPU ...\n");
|
||||
reset_cpu (0);
|
||||
}
|
||||
|
||||
void show_regs (struct pt_regs *regs)
|
||||
{
|
||||
unsigned long flags;
|
||||
const char *processor_modes[] = {
|
||||
"USER_26", "FIQ_26", "IRQ_26", "SVC_26",
|
||||
"UK4_26", "UK5_26", "UK6_26", "UK7_26",
|
||||
"UK8_26", "UK9_26", "UK10_26", "UK11_26",
|
||||
"UK12_26", "UK13_26", "UK14_26", "UK15_26",
|
||||
"USER_32", "FIQ_32", "IRQ_32", "SVC_32",
|
||||
"UK4_32", "UK5_32", "UK6_32", "ABT_32",
|
||||
"UK8_32", "UK9_32", "UK10_32", "UND_32",
|
||||
"UK12_32", "UK13_32", "UK14_32", "SYS_32",
|
||||
};
|
||||
|
||||
flags = condition_codes (regs);
|
||||
|
||||
printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
|
||||
"sp : %08lx ip : %08lx fp : %08lx\n",
|
||||
instruction_pointer (regs),
|
||||
regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
|
||||
printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
|
||||
regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
|
||||
printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
|
||||
regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
|
||||
printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
|
||||
regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
|
||||
printf ("Flags: %c%c%c%c",
|
||||
flags & CC_N_BIT ? 'N' : 'n',
|
||||
flags & CC_Z_BIT ? 'Z' : 'z',
|
||||
flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
|
||||
printf (" IRQs %s FIQs %s Mode %s%s\n",
|
||||
interrupts_enabled (regs) ? "on" : "off",
|
||||
fast_interrupts_enabled (regs) ? "on" : "off",
|
||||
processor_modes[processor_mode (regs)],
|
||||
thumb_mode (regs) ? " (T)" : "");
|
||||
}
|
||||
|
||||
void do_undefined_instruction (struct pt_regs *pt_regs)
|
||||
{
|
||||
printf ("undefined instruction\n");
|
||||
show_regs (pt_regs);
|
||||
bad_mode ();
|
||||
}
|
||||
|
||||
void do_software_interrupt (struct pt_regs *pt_regs)
|
||||
{
|
||||
printf ("software interrupt\n");
|
||||
show_regs (pt_regs);
|
||||
bad_mode ();
|
||||
}
|
||||
|
||||
void do_prefetch_abort (struct pt_regs *pt_regs)
|
||||
{
|
||||
printf ("prefetch abort\n");
|
||||
show_regs (pt_regs);
|
||||
bad_mode ();
|
||||
}
|
||||
|
||||
void do_data_abort (struct pt_regs *pt_regs)
|
||||
{
|
||||
printf ("data abort\n");
|
||||
show_regs (pt_regs);
|
||||
bad_mode ();
|
||||
}
|
||||
|
||||
void do_not_used (struct pt_regs *pt_regs)
|
||||
{
|
||||
printf ("not used\n");
|
||||
show_regs (pt_regs);
|
||||
bad_mode ();
|
||||
}
|
||||
|
||||
void do_fiq (struct pt_regs *pt_regs)
|
||||
{
|
||||
printf ("fast interrupt request\n");
|
||||
show_regs (pt_regs);
|
||||
bad_mode ();
|
||||
}
|
||||
|
||||
void do_irq (struct pt_regs *pt_regs)
|
||||
{
|
||||
printf ("interrupt request\n");
|
||||
show_regs (pt_regs);
|
||||
bad_mode ();
|
||||
}
|
||||
|
||||
|
||||
int interrupt_init (void)
|
||||
{
|
||||
|
||||
/* we don't use interrupt */
|
||||
return(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* timer without interrupts
|
||||
*/
|
||||
|
||||
void reset_timer (void)
|
||||
{
|
||||
reset_timer_masked ();
|
||||
}
|
||||
|
||||
ulong get_timer (ulong base)
|
||||
{
|
||||
return get_timer_masked ();
|
||||
}
|
||||
|
||||
void set_timer (ulong t)
|
||||
{
|
||||
/* Nop */
|
||||
}
|
||||
|
||||
void udelay (unsigned long usec)
|
||||
{
|
||||
udelay_masked (usec);
|
||||
}
|
||||
|
||||
void reset_timer_masked (void)
|
||||
{
|
||||
u32 tmp;
|
||||
MX1_TCTL1 = 0x09;
|
||||
tmp = 0x1f; /* a little delay for timer to reset */
|
||||
MX1_TPRER1 = 0x1f;
|
||||
MX1_TCTL1 = 0x19;
|
||||
}
|
||||
|
||||
ulong get_timer_masked (void)
|
||||
{
|
||||
return MX1_TCN1;
|
||||
}
|
||||
|
||||
void udelay_masked (unsigned long usec)
|
||||
{
|
||||
ulong tmo;
|
||||
|
||||
tmo = usec / 1000;
|
||||
tmo *= CFG_HZ;
|
||||
tmo /= 1000;
|
||||
|
||||
reset_timer_masked ();
|
||||
|
||||
while (get_timer_masked () < tmo);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long).
|
||||
* On ARM it just returns the timer value.
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
return get_timer(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On ARM it returns the number of timer ticks per second.
|
||||
*/
|
||||
|
||||
ulong get_tbclk (void) {
|
||||
return CFG_HZ;
|
||||
}
|
|
@ -1,133 +0,0 @@
|
|||
/*
|
||||
* cpu/mc9328/serial.c
|
||||
*
|
||||
* (c) Copyright 2004
|
||||
* Techware Information Technology, Inc.
|
||||
* http://www.techware.com.tw/
|
||||
*
|
||||
* Ming-Len Wu <minglen_wu@techware.com.tw>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mc9328.h>
|
||||
|
||||
#if defined(CONFIG_UART1)
|
||||
/* GPIO PORT B */
|
||||
|
||||
#define reg_GIUS MX1_GIUS_C
|
||||
#define reg_GPR MX1_GPR_B
|
||||
#define GPIO_MASK 0xFFFFE1FF
|
||||
#define UART_BASE 0x00206000
|
||||
|
||||
#elif defined (CONFIG_UART2)
|
||||
/* GPIO PORT C */
|
||||
|
||||
#define reg_GIUS MX1_GIUS_C
|
||||
#define reg_GPR MX1_GPR_C
|
||||
#define GPIO_MASK 0x0FFFFFFF
|
||||
#define UART_BASE 0x207000
|
||||
|
||||
#endif
|
||||
|
||||
#define reg_URXD (*((volatile u32 *)(UART_BASE+0x00)))
|
||||
#define reg_UTXD (*((volatile u32 *)(UART_BASE+0x40)))
|
||||
#define reg_UCR1 (*((volatile u32 *)(UART_BASE+0x80)))
|
||||
#define reg_UCR2 (*((volatile u32 *)(UART_BASE+0x84)))
|
||||
#define reg_UCR3 (*((volatile u32 *)(UART_BASE+0x88)))
|
||||
#define reg_UCR4 (*((volatile u32 *)(UART_BASE+0x8C)))
|
||||
#define reg_UFCR (*((volatile u32 *)(UART_BASE+0x90)))
|
||||
#define reg_USR1 (*((volatile u32 *)(UART_BASE+0x94)))
|
||||
#define reg_USR2 (*((volatile u32 *)(UART_BASE+0x98)))
|
||||
#define reg_UESC (*((volatile u32 *)(UART_BASE+0x9C)))
|
||||
#define reg_UTIM (*((volatile u32 *)(UART_BASE+0xA0)))
|
||||
#define reg_UBIR (*((volatile u32 *)(UART_BASE+0xA4)))
|
||||
#define reg_UBMR (*((volatile u32 *)(UART_BASE+0xA8)))
|
||||
#define reg_UBRC (*((volatile u32 *)(UART_BASE+0xAC)))
|
||||
|
||||
#define TXFE_MASK 0x4000 /* Tx buffer empty */
|
||||
#define RDR_MASK 0x0001 /* receive data ready */
|
||||
|
||||
void serial_setbrg (void) {
|
||||
|
||||
/* config I/O pins for UART */
|
||||
reg_GIUS &= GPIO_MASK;
|
||||
reg_GPR &= GPIO_MASK;
|
||||
|
||||
/* config UART */
|
||||
reg_UCR1 = 5;
|
||||
reg_UCR2 = 0x4027;
|
||||
reg_UCR4 = 1;
|
||||
reg_UFCR = 0xA81;
|
||||
|
||||
reg_UBIR = 0xF;
|
||||
reg_UBMR = 0x8A;
|
||||
reg_UBRC = 8;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialise the serial port with the given baudrate. The settings
|
||||
* are always 8 data bits, no parity, 1 stop bit, no start bits.
|
||||
*
|
||||
*/
|
||||
|
||||
int serial_init (void) {
|
||||
serial_setbrg ();
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read a single byte from the serial port. Returns 1 on success, 0
|
||||
* otherwise. When the function is succesfull, the character read is
|
||||
* written into its argument c.
|
||||
*/
|
||||
int serial_getc (void) {
|
||||
|
||||
while (!(reg_USR2 & RDR_MASK)) ; /* wait until RDR bit set */
|
||||
|
||||
return (u8)reg_URXD;
|
||||
}
|
||||
|
||||
/*
|
||||
* Output a single byte to the serial port.
|
||||
*/
|
||||
void serial_putc (const char c) {
|
||||
|
||||
while (!(reg_USR2 & TXFE_MASK)); /* wait until TXFE bit set */
|
||||
|
||||
reg_UTXD = (u16) c;
|
||||
|
||||
if (c == '\n') { /* carriage return ? append line-feed */
|
||||
while (!(reg_USR2 & TXFE_MASK)); /* wait until TXFE bit set */
|
||||
reg_UTXD = '\r';
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Test whether a character is in the RX buffer
|
||||
*/
|
||||
int serial_tstc (void) {
|
||||
return reg_USR2 & RDR_MASK;
|
||||
}
|
||||
|
||||
void serial_puts (const char *s) {
|
||||
while (*s) {
|
||||
serial_putc (*s++);
|
||||
}
|
||||
}
|
|
@ -1,388 +0,0 @@
|
|||
/*
|
||||
* armboot - Startup Code for ARM920 CPU-core
|
||||
*
|
||||
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
|
||||
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
|
||||
* Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
*
|
||||
* Jump vector table as in table 3.1 in [1]
|
||||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
.globl _start
|
||||
_start: b reset
|
||||
ldr pc, _undefined_instruction
|
||||
ldr pc, _software_interrupt
|
||||
ldr pc, _prefetch_abort
|
||||
ldr pc, _data_abort
|
||||
ldr pc, _not_used
|
||||
ldr pc, _irq
|
||||
ldr pc, _fiq
|
||||
|
||||
_undefined_instruction: .word undefined_instruction
|
||||
_software_interrupt: .word software_interrupt
|
||||
_prefetch_abort: .word prefetch_abort
|
||||
_data_abort: .word data_abort
|
||||
_not_used: .word not_used
|
||||
_irq: .word irq
|
||||
_fiq: .word fiq
|
||||
|
||||
.balignl 16,0xdeadbeef
|
||||
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
*
|
||||
* Startup Code (reset vector)
|
||||
*
|
||||
* do important init only if we don't start from memory!
|
||||
* relocate armboot to ram
|
||||
* setup stack
|
||||
* jump to second stage
|
||||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
|
||||
_TEXT_BASE:
|
||||
.word TEXT_BASE
|
||||
|
||||
.globl _armboot_start
|
||||
_armboot_start:
|
||||
.word _start
|
||||
|
||||
/*
|
||||
* These are defined in the board-specific linker script.
|
||||
*/
|
||||
.globl _bss_start
|
||||
_bss_start:
|
||||
.word __bss_start
|
||||
|
||||
.globl _bss_end
|
||||
_bss_end:
|
||||
.word _end
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* IRQ stack memory (calculated at run-time) */
|
||||
.globl IRQ_STACK_START
|
||||
IRQ_STACK_START:
|
||||
.word 0x0badc0de
|
||||
|
||||
/* IRQ stack memory (calculated at run-time) */
|
||||
.globl FIQ_STACK_START
|
||||
FIQ_STACK_START:
|
||||
.word 0x0badc0de
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* the actual reset code
|
||||
*/
|
||||
|
||||
reset:
|
||||
/*
|
||||
* set the cpu to SVC32 mode
|
||||
*/
|
||||
mrs r0,cpsr
|
||||
bic r0,r0,#0x1f
|
||||
orr r0,r0,#0xd3
|
||||
msr cpsr,r0
|
||||
|
||||
/*
|
||||
* we do sys-critical inits only at reboot,
|
||||
* not when booting from ram!
|
||||
*/
|
||||
#ifdef CONFIG_INIT_CRITICAL
|
||||
bl cpu_init_crit
|
||||
#endif
|
||||
|
||||
relocate: /* relocate U-Boot to RAM */
|
||||
adr r0, _start /* r0 <- current position of code */
|
||||
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
|
||||
cmp r0, r1 /* don't reloc during debug */
|
||||
beq stack_setup
|
||||
|
||||
ldr r2, _armboot_start
|
||||
ldr r3, _bss_start
|
||||
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||
add r2, r0, r2 /* r2 <- source end address */
|
||||
|
||||
copy_loop:
|
||||
ldmia r0!, {r3-r10} /* copy from source address [r0] */
|
||||
stmia r1!, {r3-r10} /* copy to target address [r1] */
|
||||
cmp r0, r2 /* until source end addreee [r2] */
|
||||
ble copy_loop
|
||||
|
||||
/* Set up the stack */
|
||||
stack_setup:
|
||||
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
|
||||
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
|
||||
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
|
||||
#endif
|
||||
sub sp, r0, #12 /* leave 3 words for abort-stack */
|
||||
|
||||
clear_bss:
|
||||
ldr r0, _bss_start /* find start of bss segment */
|
||||
ldr r1, _bss_end /* stop here */
|
||||
mov r2, #0x00000000 /* clear */
|
||||
|
||||
clbss_l:str r2, [r0] /* clear loop... */
|
||||
add r0, r0, #4
|
||||
cmp r0, r1
|
||||
bne clbss_l
|
||||
|
||||
ldr pc, _start_armboot
|
||||
|
||||
_start_armboot: .word start_armboot
|
||||
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
*
|
||||
* CPU_init_critical registers
|
||||
*
|
||||
* setup important registers
|
||||
* setup memory timing
|
||||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
cpu_init_crit:
|
||||
/*
|
||||
* flush v4 I/D caches
|
||||
*/
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
|
||||
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
|
||||
|
||||
/*
|
||||
* disable MMU stuff and caches
|
||||
*/
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
|
||||
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
|
||||
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
|
||||
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
|
||||
/*
|
||||
* before relocating, we have to setup RAM timing
|
||||
* because memory timing is board-dependend, you will
|
||||
* find a memsetup.S in your board directory.
|
||||
*/
|
||||
mov ip, lr
|
||||
bl memsetup
|
||||
mov lr, ip
|
||||
|
||||
mov pc, lr
|
||||
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
*
|
||||
* Interrupt handling
|
||||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
|
||||
@
|
||||
@ IRQ stack frame.
|
||||
@
|
||||
#define S_FRAME_SIZE 72
|
||||
|
||||
#define S_OLD_R0 68
|
||||
#define S_PSR 64
|
||||
#define S_PC 60
|
||||
#define S_LR 56
|
||||
#define S_SP 52
|
||||
|
||||
#define S_IP 48
|
||||
#define S_FP 44
|
||||
#define S_R10 40
|
||||
#define S_R9 36
|
||||
#define S_R8 32
|
||||
#define S_R7 28
|
||||
#define S_R6 24
|
||||
#define S_R5 20
|
||||
#define S_R4 16
|
||||
#define S_R3 12
|
||||
#define S_R2 8
|
||||
#define S_R1 4
|
||||
#define S_R0 0
|
||||
|
||||
#define MODE_SVC 0x13
|
||||
#define I_BIT 0x80
|
||||
|
||||
/*
|
||||
* use bad_save_user_regs for abort/prefetch/undef/swi ...
|
||||
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
|
||||
*/
|
||||
|
||||
.macro bad_save_user_regs
|
||||
sub sp, sp, #S_FRAME_SIZE
|
||||
stmia sp, {r0 - r12} @ Calling r0-r12
|
||||
ldr r2, _armboot_start
|
||||
sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
|
||||
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
||||
ldmia r2, {r2 - r3} @ get pc, cpsr
|
||||
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
|
||||
|
||||
add r5, sp, #S_SP
|
||||
mov r1, lr
|
||||
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
|
||||
mov r0, sp
|
||||
.endm
|
||||
|
||||
.macro irq_save_user_regs
|
||||
sub sp, sp, #S_FRAME_SIZE
|
||||
stmia sp, {r0 - r12} @ Calling r0-r12
|
||||
add r8, sp, #S_PC
|
||||
stmdb r8, {sp, lr}^ @ Calling SP, LR
|
||||
str lr, [r8, #0] @ Save calling PC
|
||||
mrs r6, spsr
|
||||
str r6, [r8, #4] @ Save CPSR
|
||||
str r0, [r8, #8] @ Save OLD_R0
|
||||
mov r0, sp
|
||||
.endm
|
||||
|
||||
.macro irq_restore_user_regs
|
||||
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
|
||||
mov r0, r0
|
||||
ldr lr, [sp, #S_PC] @ Get PC
|
||||
add sp, sp, #S_FRAME_SIZE
|
||||
subs pc, lr, #4 @ return & move spsr_svc into cpsr
|
||||
.endm
|
||||
|
||||
.macro get_bad_stack
|
||||
ldr r13, _armboot_start @ setup our mode stack
|
||||
sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
|
||||
sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
||||
|
||||
str lr, [r13] @ save caller lr / spsr
|
||||
mrs lr, spsr
|
||||
str lr, [r13, #4]
|
||||
|
||||
mov r13, #MODE_SVC @ prepare SVC-Mode
|
||||
@ msr spsr_c, r13
|
||||
msr spsr, r13
|
||||
mov lr, pc
|
||||
movs pc, lr
|
||||
.endm
|
||||
|
||||
.macro get_irq_stack @ setup IRQ stack
|
||||
ldr sp, IRQ_STACK_START
|
||||
.endm
|
||||
|
||||
.macro get_fiq_stack @ setup FIQ stack
|
||||
ldr sp, FIQ_STACK_START
|
||||
.endm
|
||||
|
||||
/*
|
||||
* exception handlers
|
||||
*/
|
||||
.align 5
|
||||
undefined_instruction:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_undefined_instruction
|
||||
|
||||
.align 5
|
||||
software_interrupt:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_software_interrupt
|
||||
|
||||
.align 5
|
||||
prefetch_abort:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_prefetch_abort
|
||||
|
||||
.align 5
|
||||
data_abort:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_data_abort
|
||||
|
||||
.align 5
|
||||
not_used:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_not_used
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
|
||||
.align 5
|
||||
irq:
|
||||
get_irq_stack
|
||||
irq_save_user_regs
|
||||
bl do_irq
|
||||
irq_restore_user_regs
|
||||
|
||||
.align 5
|
||||
fiq:
|
||||
get_fiq_stack
|
||||
/* someone ought to write a more effiction fiq_save_user_regs */
|
||||
irq_save_user_regs
|
||||
bl do_fiq
|
||||
irq_restore_user_regs
|
||||
|
||||
#else
|
||||
|
||||
.align 5
|
||||
irq:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_irq
|
||||
|
||||
.align 5
|
||||
fiq:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_fiq
|
||||
|
||||
#endif
|
||||
|
||||
.align 5
|
||||
.globl reset_cpu
|
||||
reset_cpu:
|
||||
mov ip, #0
|
||||
mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
|
||||
mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
|
||||
mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
|
||||
bic ip, ip, #0x000f @ ............wcam
|
||||
bic ip, ip, #0x2100 @ ..v....s........
|
||||
mcr p15, 0, ip, c1, c0, 0 @ ctrl register
|
||||
mov pc, r0
|
|
@ -108,7 +108,7 @@ cpu_init_f (void)
|
|||
|
||||
CONFIG_READ_BYTE(PCMBCR,val);
|
||||
/* in order not to corrupt data which is being read over the PCI bus
|
||||
* with the PPC as master, we need to reduce the number of PCMRBs to 1,
|
||||
* with the PPC as slave, we need to reduce the number of PCMRBs to 1,
|
||||
* 4.11 in the processor user manual
|
||||
* */
|
||||
|
||||
|
@ -117,6 +117,10 @@ cpu_init_f (void)
|
|||
#else
|
||||
CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */
|
||||
CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */
|
||||
/* default, 4 PCMRBs are used, so don't change the
|
||||
* register is this is _really_ what you want: data
|
||||
* corruption with no performance gain
|
||||
*/
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
|
|
@ -33,7 +33,6 @@
|
|||
|
||||
void get_sys_info (sys_info_t * sysInfo)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
||||
uint plat_ratio,e500_ratio;
|
||||
|
|
|
@ -193,6 +193,10 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
|
|||
|
||||
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
||||
|
||||
#if defined(CONFIG_LWMON)
|
||||
reset_phy();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FADS
|
||||
#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T)
|
||||
/* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
|
||||
|
@ -550,6 +554,8 @@ static void scc_halt (struct eth_device *dev)
|
|||
|
||||
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &=
|
||||
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
|
||||
immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA);
|
||||
}
|
||||
|
||||
#if 0
|
||||
|
|
|
@ -24,49 +24,44 @@
|
|||
#include <common.h>
|
||||
#include <commproc.h>
|
||||
#include <command.h>
|
||||
#include <serial.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
#if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
|
||||
|
||||
#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
|
||||
#define SMC_INDEX 0
|
||||
#undef SCC_INDEX
|
||||
#define PROFF_SMC PROFF_SMC1
|
||||
#define CPM_CR_CH_SMC CPM_CR_CH_SMC1
|
||||
|
||||
#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
|
||||
#define SMC_INDEX 1
|
||||
#undef SCC_INDEX
|
||||
#define PROFF_SMC PROFF_SMC2
|
||||
#define CPM_CR_CH_SMC CPM_CR_CH_SMC2
|
||||
|
||||
#elif defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
|
||||
#undef SMC_INDEX
|
||||
#endif /* CONFIG_8xx_CONS_SMCx */
|
||||
|
||||
#if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
|
||||
#define SCC_INDEX 0
|
||||
#define PROFF_SCC PROFF_SCC1
|
||||
#define CPM_CR_CH_SCC CPM_CR_CH_SCC1
|
||||
|
||||
#elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
|
||||
#undef SMC_INDEX
|
||||
#define SCC_INDEX 1
|
||||
#define PROFF_SCC PROFF_SCC2
|
||||
#define CPM_CR_CH_SCC CPM_CR_CH_SCC2
|
||||
|
||||
#elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
|
||||
#undef SMC_INDEX
|
||||
#define SCC_INDEX 2
|
||||
#define PROFF_SCC PROFF_SCC3
|
||||
#define CPM_CR_CH_SCC CPM_CR_CH_SCC3
|
||||
|
||||
#elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
|
||||
#undef SMC_INDEX
|
||||
#define SCC_INDEX 3
|
||||
#define PROFF_SCC PROFF_SCC4
|
||||
#define CPM_CR_CH_SCC CPM_CR_CH_SCC4
|
||||
|
||||
#else /* CONFIG_8xx_CONS_? */
|
||||
#error "console not correctly defined"
|
||||
#endif
|
||||
#endif /* CONFIG_8xx_CONS_SCCx */
|
||||
|
||||
static void serial_setdivisor(volatile cpm8xx_t *cp)
|
||||
{
|
||||
|
@ -96,7 +91,23 @@ static void serial_setdivisor(volatile cpm8xx_t *cp)
|
|||
* as serial console interface.
|
||||
*/
|
||||
|
||||
int serial_init (void)
|
||||
static void smc_setbrg (void)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *)CFG_IMMR;
|
||||
volatile cpm8xx_t *cp = &(im->im_cpm);
|
||||
|
||||
/* Set up the baud rate generator.
|
||||
* See 8xx_io/commproc.c for details.
|
||||
*
|
||||
* Wire BRG1 to SMCx
|
||||
*/
|
||||
|
||||
cp->cp_simode = 0x00000000;
|
||||
|
||||
serial_setdivisor(cp);
|
||||
}
|
||||
|
||||
static int smc_init (void)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *)CFG_IMMR;
|
||||
volatile smc_t *sp;
|
||||
|
@ -217,7 +228,7 @@ int serial_init (void)
|
|||
|
||||
/* Set up the baud rate generator.
|
||||
*/
|
||||
serial_setbrg ();
|
||||
smc_setbrg ();
|
||||
|
||||
/* Make the first buffer the only buffer.
|
||||
*/
|
||||
|
@ -247,39 +258,8 @@ int serial_init (void)
|
|||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
serial_setbrg (void)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *)CFG_IMMR;
|
||||
volatile cpm8xx_t *cp = &(im->im_cpm);
|
||||
|
||||
/* Set up the baud rate generator.
|
||||
* See 8xx_io/commproc.c for details.
|
||||
*
|
||||
* Wire BRG1 to SMCx
|
||||
*/
|
||||
|
||||
cp->cp_simode = 0x00000000;
|
||||
|
||||
serial_setdivisor(cp);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MODEM_SUPPORT
|
||||
void disable_putc(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
gd->be_quiet = 1;
|
||||
}
|
||||
|
||||
void enable_putc(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
gd->be_quiet = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
serial_putc(const char c)
|
||||
static void
|
||||
smc_putc(const char c)
|
||||
{
|
||||
volatile cbd_t *tbdf;
|
||||
volatile char *buf;
|
||||
|
@ -295,7 +275,7 @@ serial_putc(const char c)
|
|||
#endif
|
||||
|
||||
if (c == '\n')
|
||||
serial_putc ('\r');
|
||||
smc_putc ('\r');
|
||||
|
||||
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
|
||||
|
||||
|
@ -317,8 +297,16 @@ serial_putc(const char c)
|
|||
}
|
||||
}
|
||||
|
||||
int
|
||||
serial_getc(void)
|
||||
static void
|
||||
smc_puts (const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
smc_putc (*s++);
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
smc_getc(void)
|
||||
{
|
||||
volatile cbd_t *rbdf;
|
||||
volatile unsigned char *buf;
|
||||
|
@ -344,8 +332,8 @@ serial_getc(void)
|
|||
return(c);
|
||||
}
|
||||
|
||||
int
|
||||
serial_tstc()
|
||||
static int
|
||||
smc_tstc(void)
|
||||
{
|
||||
volatile cbd_t *rbdf;
|
||||
volatile smc_uart_t *up;
|
||||
|
@ -359,9 +347,41 @@ serial_tstc()
|
|||
return(!(rbdf->cbd_sc & BD_SC_EMPTY));
|
||||
}
|
||||
|
||||
#else /* ! CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
|
||||
struct serial_device serial_smc_device =
|
||||
{
|
||||
"serial_smc",
|
||||
"SMC",
|
||||
smc_init,
|
||||
smc_setbrg,
|
||||
smc_getc,
|
||||
smc_tstc,
|
||||
smc_putc,
|
||||
smc_puts,
|
||||
};
|
||||
|
||||
int serial_init (void)
|
||||
#endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
|
||||
|
||||
#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
|
||||
defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
|
||||
|
||||
static void
|
||||
scc_setbrg (void)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *)CFG_IMMR;
|
||||
volatile cpm8xx_t *cp = &(im->im_cpm);
|
||||
|
||||
/* Set up the baud rate generator.
|
||||
* See 8xx_io/commproc.c for details.
|
||||
*
|
||||
* Wire BRG1 to SCCx
|
||||
*/
|
||||
|
||||
cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
|
||||
|
||||
serial_setdivisor(cp);
|
||||
}
|
||||
|
||||
static int scc_init (void)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *)CFG_IMMR;
|
||||
volatile scc_t *sp;
|
||||
|
@ -426,7 +446,7 @@ int serial_init (void)
|
|||
#ifdef CFG_ALLOC_DPRAM
|
||||
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
|
||||
#else
|
||||
dpaddr = CPM_SERIAL_BASE ;
|
||||
dpaddr = CPM_SERIAL2_BASE ;
|
||||
#endif
|
||||
|
||||
/* Enable SDMA.
|
||||
|
@ -446,7 +466,7 @@ int serial_init (void)
|
|||
|
||||
/* Set up the baud rate generator.
|
||||
*/
|
||||
serial_setbrg ();
|
||||
scc_setbrg ();
|
||||
|
||||
/* Set up the uart parameters in the parameter ram.
|
||||
*/
|
||||
|
@ -497,9 +517,11 @@ int serial_init (void)
|
|||
|
||||
/* Set UART mode, clock divider 16 on Tx and Rx
|
||||
*/
|
||||
sp->scc_gsmrl &= ~0xF;
|
||||
sp->scc_gsmrl |=
|
||||
(SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
|
||||
|
||||
sp->scc_psmr = 0;
|
||||
sp->scc_psmr |= SCU_PSMR_CL;
|
||||
|
||||
/* Mask all interrupts and remove anything pending.
|
||||
|
@ -521,25 +543,8 @@ int serial_init (void)
|
|||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
serial_setbrg (void)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *)CFG_IMMR;
|
||||
volatile cpm8xx_t *cp = &(im->im_cpm);
|
||||
|
||||
/* Set up the baud rate generator.
|
||||
* See 8xx_io/commproc.c for details.
|
||||
*
|
||||
* Wire BRG1 to SCCx
|
||||
*/
|
||||
|
||||
cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
|
||||
|
||||
serial_setdivisor(cp);
|
||||
}
|
||||
|
||||
void
|
||||
serial_putc(const char c)
|
||||
static void
|
||||
scc_putc(const char c)
|
||||
{
|
||||
volatile cbd_t *tbdf;
|
||||
volatile char *buf;
|
||||
|
@ -547,8 +552,15 @@ serial_putc(const char c)
|
|||
volatile immap_t *im = (immap_t *)CFG_IMMR;
|
||||
volatile cpm8xx_t *cpmp = &(im->im_cpm);
|
||||
|
||||
#ifdef CONFIG_MODEM_SUPPORT
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
if (gd->be_quiet)
|
||||
return;
|
||||
#endif
|
||||
|
||||
if (c == '\n')
|
||||
serial_putc ('\r');
|
||||
scc_putc ('\r');
|
||||
|
||||
up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
|
||||
|
||||
|
@ -570,8 +582,16 @@ serial_putc(const char c)
|
|||
}
|
||||
}
|
||||
|
||||
int
|
||||
serial_getc(void)
|
||||
static void
|
||||
scc_puts (const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
scc_putc (*s++);
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
scc_getc(void)
|
||||
{
|
||||
volatile cbd_t *rbdf;
|
||||
volatile unsigned char *buf;
|
||||
|
@ -597,8 +617,8 @@ serial_getc(void)
|
|||
return(c);
|
||||
}
|
||||
|
||||
int
|
||||
serial_tstc()
|
||||
static int
|
||||
scc_tstc(void)
|
||||
{
|
||||
volatile cbd_t *rbdf;
|
||||
volatile scc_uart_t *up;
|
||||
|
@ -612,36 +632,66 @@ serial_tstc()
|
|||
return(!(rbdf->cbd_sc & BD_SC_EMPTY));
|
||||
}
|
||||
|
||||
#endif /* CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
|
||||
|
||||
|
||||
void
|
||||
serial_puts (const char *s)
|
||||
struct serial_device serial_scc_device =
|
||||
{
|
||||
while (*s) {
|
||||
serial_putc (*s++);
|
||||
}
|
||||
"serial_scc",
|
||||
"SCC",
|
||||
scc_init,
|
||||
scc_setbrg,
|
||||
scc_getc,
|
||||
scc_tstc,
|
||||
scc_putc,
|
||||
scc_puts,
|
||||
};
|
||||
|
||||
#endif /* CONFIG_8xx_CONS_SCCx */
|
||||
|
||||
#ifdef CONFIG_MODEM_SUPPORT
|
||||
void disable_putc(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
gd->be_quiet = 1;
|
||||
}
|
||||
|
||||
void enable_putc(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
gd->be_quiet = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
|
||||
void
|
||||
kgdb_serial_init(void)
|
||||
{
|
||||
int i = -1;
|
||||
|
||||
if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
|
||||
{
|
||||
#if defined(CONFIG_8xx_CONS_SMC1)
|
||||
serial_printf("[on SMC1] ");
|
||||
i = 1;
|
||||
#elif defined(CONFIG_8xx_CONS_SMC2)
|
||||
serial_printf("[on SMC2] ");
|
||||
#elif defined(CONFIG_8xx_CONS_SCC1)
|
||||
serial_printf("[on SCC1] ");
|
||||
#elif defined(CONFIG_8xx_CONS_SCC2)
|
||||
serial_printf("[on SCC2] ");
|
||||
#elif defined(CONFIG_8xx_CONS_SCC3)
|
||||
serial_printf("[on SCC3] ");
|
||||
#elif defined(CONFIG_8xx_CONS_SCC4)
|
||||
serial_printf("[on SCC4] ");
|
||||
i = 2;
|
||||
#endif
|
||||
}
|
||||
else if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
|
||||
{
|
||||
#if defined(CONFIG_8xx_CONS_SCC1)
|
||||
i = 1;
|
||||
#elif defined(CONFIG_8xx_CONS_SCC2)
|
||||
i = 2;
|
||||
#elif defined(CONFIG_8xx_CONS_SCC3)
|
||||
i = 3;
|
||||
#elif defined(CONFIG_8xx_CONS_SCC4)
|
||||
i = 4;
|
||||
#endif
|
||||
}
|
||||
|
||||
if (i >= 0)
|
||||
{
|
||||
serial_printf("[on %s%d] ", default_serial_console()->ctlr, i);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
|
|
|
@ -39,7 +39,7 @@
|
|||
#include <linux/ctype.h>
|
||||
#include <malloc.h>
|
||||
#include <post.h>
|
||||
#include <net.h>
|
||||
#include <serial.h>
|
||||
|
||||
#if (defined(CONFIG_SPI)) || (CONFIG_POST & CFG_POST_SPI)
|
||||
|
||||
|
@ -542,13 +542,13 @@ int spi_post_test (int flags)
|
|||
cp->cp_spmode &= ~SPMODE_LOOP;
|
||||
|
||||
/*
|
||||
* SCC2 Ethernet parameter RAM space overlaps
|
||||
* SCC2 parameter RAM space overlaps
|
||||
* the SPI parameter RAM space. So we need to restore
|
||||
* the SCC2 configuration if it is used by UART or Ethernet.
|
||||
* the SCC2 configuration if it is used by UART.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_8xx_CONS_SCC2)
|
||||
serial_init ();
|
||||
#if !defined(CONFIG_8xx_CONS_NONE)
|
||||
serial_reinit_all ();
|
||||
#endif
|
||||
|
||||
if (res != 0) {
|
||||
|
|
37
doc/README.serial_multi
Normal file
37
doc/README.serial_multi
Normal file
|
@ -0,0 +1,37 @@
|
|||
The support for multiple serial interfaces as implemented is mainly
|
||||
intended to allow for modem dial-in / dial-out while still being able
|
||||
to use a serial console on a (different) serial port.
|
||||
|
||||
At the moment, the ports must be split on a SMC and a SCC port on a
|
||||
8xx processor; other configurations are not (yet) supported.
|
||||
|
||||
Support for hardware handshake has not been implemented yet (but is
|
||||
in the works).
|
||||
|
||||
*) The default console depends on the keys pressed:
|
||||
- SMC if keys not pressed (modem not enabled)
|
||||
- SCC if keys pressed (modem enabled)
|
||||
|
||||
*) The console can be switched to SCC by any of the following commands:
|
||||
|
||||
setenv stdout serial_scc
|
||||
setenv stdin serial_scc
|
||||
setenv stderr serial_scc
|
||||
|
||||
*) The console can be switched to SMC by any of the following commands:
|
||||
|
||||
setenv stdout serial_smc
|
||||
setenv stdin serial_smc
|
||||
setenv stderr serial_smc
|
||||
|
||||
*) If a file descriptor is set to "serial" then the current serial device
|
||||
will be used which, in turn, can be switched by above commands.
|
||||
|
||||
*) The baudrate is the same for all serial devices. But it can be switched
|
||||
just after switching the console:
|
||||
|
||||
setenv sout serial_scc; setenv baudrate 38400
|
||||
|
||||
After that press 'enter' at the SCC console. Note that baudrates <38400
|
||||
are not allowed on LWMON with watchdog enabled (see CFG_BAUDRATE_TABLE in
|
||||
include/configs/lwmon.h).
|
|
@ -29,23 +29,23 @@ LIB = libdrivers.a
|
|||
|
||||
OBJS = 3c589.o 5701rls.o ali512x.o \
|
||||
bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
|
||||
cs8900.o ct69000.o dataflash.o dc2114x.o \
|
||||
cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
|
||||
e1000.o eepro100.o \
|
||||
i8042.o i82365.o inca-ip_sw.o keyboard.o \
|
||||
lan91c96.o natsemi.o netarm_eth.o \
|
||||
ns16550.o ns8382x.o ns87308.o \
|
||||
ns16550.o ns8382x.o ns87308.o omap1510_i2c.o \
|
||||
pci.o pci_auto.o pci_indirect.o \
|
||||
pcnet.o plb2800_eth.o \
|
||||
ps2ser.o ps2mult.o pc_keyb.o \
|
||||
rtl8019.o rtl8139.o rtl8169.o \
|
||||
s3c24x0_i2c.o s3c4510b_eth.o s3c4510b_uart.o \
|
||||
sed13806.o sed156x.o \
|
||||
serial.o serial_max3100.o serial_pl010.o serial_pl011.o \
|
||||
serial_xuartlite.o sl811_usb.o \
|
||||
smc91111.o smiLynxEM.o status_led.o sym53c8xx.o \
|
||||
ti_pci1410a.o tigon3.o w83c553f.o omap1510_i2c.o \
|
||||
serial.o serial_imx.o serial_max3100.o \
|
||||
serial_pl010.o serial_pl011.o serial_xuartlite.o \
|
||||
sl811_usb.o smc91111.o smiLynxEM.o status_led.o sym53c8xx.o \
|
||||
ti_pci1410a.o tigon3.o \
|
||||
usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \
|
||||
videomodes.o
|
||||
videomodes.o w83c553f.o
|
||||
|
||||
all: $(LIB)
|
||||
|
||||
|
|
|
@ -1169,7 +1169,6 @@ int drv_video_init (void)
|
|||
{
|
||||
int skip_dev_init;
|
||||
device_t console_dev;
|
||||
char *penv;
|
||||
|
||||
skip_dev_init = 0;
|
||||
|
||||
|
|
590
drivers/dm9000x.c
Normal file
590
drivers/dm9000x.c
Normal file
|
@ -0,0 +1,590 @@
|
|||
/*
|
||||
dm9000.c: Version 1.2 12/15/2003
|
||||
|
||||
A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
|
||||
Copyright (C) 1997 Sten Wang
|
||||
|
||||
This program is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU General Public License
|
||||
as published by the Free Software Foundation; either version 2
|
||||
of the License, or (at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
(C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
|
||||
|
||||
V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
|
||||
06/22/2001 Support DM9801 progrmming
|
||||
E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
|
||||
E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
|
||||
R17 = (R17 & 0xfff0) | NF + 3
|
||||
E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
|
||||
R17 = (R17 & 0xfff0) | NF
|
||||
|
||||
v1.00 modify by simon 2001.9.5
|
||||
change for kernel 2.4.x
|
||||
|
||||
v1.1 11/09/2001 fix force mode bug
|
||||
|
||||
v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
|
||||
Fixed phy reset.
|
||||
Added tx/rx 32 bit mode.
|
||||
Cleaned up for kernel merge.
|
||||
|
||||
--------------------------------------
|
||||
|
||||
12/15/2003 Initial port to u-boot by Sascha Hauer <saschahauer@web.de>
|
||||
|
||||
TODO: Homerun NIC and longrun NIC are not functional, only internal at the
|
||||
moment.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <net.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifdef CONFIG_DRIVER_DM9000
|
||||
|
||||
#include "dm9000x.h"
|
||||
|
||||
/* Board/System/Debug information/definition ---------------- */
|
||||
|
||||
#define DM9801_NOISE_FLOOR 0x08
|
||||
#define DM9802_NOISE_FLOOR 0x05
|
||||
|
||||
/* #define CONFIG_DM9000_DEBUG */
|
||||
|
||||
#ifdef CONFIG_DM9000_DEBUG
|
||||
#define DM9000_DBG(fmt,args...) printf(fmt ,##args)
|
||||
#else /* */
|
||||
#define DM9000_DBG(fmt,args...)
|
||||
#endif /* */
|
||||
enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD =
|
||||
1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO =
|
||||
8, DM9000_1M_HPNA = 0x10
|
||||
};
|
||||
enum DM9000_NIC_TYPE { FASTETHER_NIC = 0, HOMERUN_NIC = 1, LONGRUN_NIC = 2
|
||||
};
|
||||
|
||||
/* Structure/enum declaration ------------------------------- */
|
||||
typedef struct board_info {
|
||||
u32 runt_length_counter; /* counter: RX length < 64byte */
|
||||
u32 long_length_counter; /* counter: RX length > 1514byte */
|
||||
u32 reset_counter; /* counter: RESET */
|
||||
u32 reset_tx_timeout; /* RESET caused by TX Timeout */
|
||||
u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
|
||||
u16 tx_pkt_cnt;
|
||||
u16 queue_start_addr;
|
||||
u16 dbug_cnt;
|
||||
u8 phy_addr;
|
||||
u8 device_wait_reset; /* device state */
|
||||
u8 nic_type; /* NIC type */
|
||||
unsigned char srom[128];
|
||||
} board_info_t;
|
||||
board_info_t dmfe_info;
|
||||
|
||||
/* For module input parameter */
|
||||
static int media_mode = DM9000_AUTO;
|
||||
static u8 nfloor = 0;
|
||||
|
||||
/* function declaration ------------------------------------- */
|
||||
int eth_init(bd_t * bd);
|
||||
int eth_send(volatile void *, int);
|
||||
int eth_rx(void);
|
||||
void eth_halt(void);
|
||||
static int dm9000_probe(void);
|
||||
static u16 phy_read(int);
|
||||
static void phy_write(int, u16);
|
||||
static u16 read_srom_word(int);
|
||||
static u8 DM9000_ior(int);
|
||||
static void DM9000_iow(int reg, u8 value);
|
||||
|
||||
/* DM9000 network board routine ---------------------------- */
|
||||
|
||||
#define DM9000_outb(d,r) ( *(volatile u8 *)r = d )
|
||||
#define DM9000_outw(d,r) ( *(volatile u16 *)r = d )
|
||||
#define DM9000_outl(d,r) ( *(volatile u32 *)r = d )
|
||||
#define DM9000_inb(r) (*(volatile u8 *)r)
|
||||
#define DM9000_inw(r) (*(volatile u16 *)r)
|
||||
#define DM9000_inl(r) (*(volatile u32 *)r)
|
||||
|
||||
#ifdef CONFIG_DM9000_DEBUG
|
||||
static void
|
||||
dump_regs(void)
|
||||
{
|
||||
DM9000_DBG("\n");
|
||||
DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
|
||||
DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
|
||||
DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
|
||||
DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
|
||||
DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
|
||||
DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
|
||||
DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
|
||||
DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(ISR));
|
||||
DM9000_DBG("\n");
|
||||
}
|
||||
#endif /* */
|
||||
|
||||
/*
|
||||
Search DM9000 board, allocate space and register it
|
||||
*/
|
||||
int
|
||||
dm9000_probe(void)
|
||||
{
|
||||
u32 id_val;
|
||||
id_val = DM9000_ior(DM9000_VIDL);
|
||||
id_val |= DM9000_ior(DM9000_VIDH) << 8;
|
||||
id_val |= DM9000_ior(DM9000_PIDL) << 16;
|
||||
id_val |= DM9000_ior(DM9000_PIDH) << 24;
|
||||
if (id_val == DM9000_ID) {
|
||||
printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
|
||||
id_val);
|
||||
return 0;
|
||||
} else {
|
||||
printf("dm9000 not found at 0x%08x id: 0x%08x\n",
|
||||
CONFIG_DM9000_BASE, id_val);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Set PHY operationg mode
|
||||
*/
|
||||
static void
|
||||
set_PHY_mode(void)
|
||||
{
|
||||
u16 phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
|
||||
if (!(media_mode & DM9000_AUTO)) {
|
||||
switch (media_mode) {
|
||||
case DM9000_10MHD:
|
||||
phy_reg4 = 0x21;
|
||||
phy_reg0 = 0x0000;
|
||||
break;
|
||||
case DM9000_10MFD:
|
||||
phy_reg4 = 0x41;
|
||||
phy_reg0 = 0x1100;
|
||||
break;
|
||||
case DM9000_100MHD:
|
||||
phy_reg4 = 0x81;
|
||||
phy_reg0 = 0x2000;
|
||||
break;
|
||||
case DM9000_100MFD:
|
||||
phy_reg4 = 0x101;
|
||||
phy_reg0 = 0x3100;
|
||||
break;
|
||||
}
|
||||
phy_write(4, phy_reg4); /* Set PHY media mode */
|
||||
phy_write(0, phy_reg0); /* Tmp */
|
||||
}
|
||||
DM9000_iow(DM9000_GPCR, 0x01); /* Let GPIO0 output */
|
||||
DM9000_iow(DM9000_GPR, 0x00); /* Enable PHY */
|
||||
}
|
||||
|
||||
/*
|
||||
Init HomeRun DM9801
|
||||
*/
|
||||
static void
|
||||
program_dm9801(u16 HPNA_rev)
|
||||
{
|
||||
__u16 reg16, reg17, reg24, reg25;
|
||||
if (!nfloor)
|
||||
nfloor = DM9801_NOISE_FLOOR;
|
||||
reg16 = phy_read(16);
|
||||
reg17 = phy_read(17);
|
||||
reg24 = phy_read(24);
|
||||
reg25 = phy_read(25);
|
||||
switch (HPNA_rev) {
|
||||
case 0xb900: /* DM9801 E3 */
|
||||
reg16 |= 0x1000;
|
||||
reg25 = ((reg24 + nfloor) & 0x00ff) | 0xf000;
|
||||
break;
|
||||
case 0xb901: /* DM9801 E4 */
|
||||
reg25 = ((reg24 + nfloor) & 0x00ff) | 0xc200;
|
||||
reg17 = (reg17 & 0xfff0) + nfloor + 3;
|
||||
break;
|
||||
case 0xb902: /* DM9801 E5 */
|
||||
case 0xb903: /* DM9801 E6 */
|
||||
default:
|
||||
reg16 |= 0x1000;
|
||||
reg25 = ((reg24 + nfloor - 3) & 0x00ff) | 0xc200;
|
||||
reg17 = (reg17 & 0xfff0) + nfloor;
|
||||
}
|
||||
phy_write(16, reg16);
|
||||
phy_write(17, reg17);
|
||||
phy_write(25, reg25);
|
||||
}
|
||||
|
||||
/*
|
||||
Init LongRun DM9802
|
||||
*/
|
||||
static void
|
||||
program_dm9802(void)
|
||||
{
|
||||
__u16 reg25;
|
||||
if (!nfloor)
|
||||
nfloor = DM9802_NOISE_FLOOR;
|
||||
reg25 = phy_read(25);
|
||||
reg25 = (reg25 & 0xff00) + nfloor;
|
||||
phy_write(25, reg25);
|
||||
}
|
||||
|
||||
/* Identify NIC type
|
||||
*/
|
||||
static void
|
||||
identify_nic(void)
|
||||
{
|
||||
struct board_info *db = &dmfe_info; /* Point a board information structure */
|
||||
u16 phy_reg3;
|
||||
DM9000_iow(DM9000_NCR, NCR_EXT_PHY);
|
||||
phy_reg3 = phy_read(3);
|
||||
switch (phy_reg3 & 0xfff0) {
|
||||
case 0xb900:
|
||||
if (phy_read(31) == 0x4404) {
|
||||
db->nic_type = HOMERUN_NIC;
|
||||
program_dm9801(phy_reg3);
|
||||
DM9000_DBG("found homerun NIC\n");
|
||||
} else {
|
||||
db->nic_type = LONGRUN_NIC;
|
||||
DM9000_DBG("found longrun NIC\n");
|
||||
program_dm9802();
|
||||
}
|
||||
break;
|
||||
default:
|
||||
db->nic_type = FASTETHER_NIC;
|
||||
break;
|
||||
}
|
||||
DM9000_iow(DM9000_NCR, 0);
|
||||
}
|
||||
|
||||
/* General Purpose dm9000 reset routine */
|
||||
static void
|
||||
dm9000_reset(void)
|
||||
{
|
||||
DM9000_DBG("resetting\n");
|
||||
DM9000_iow(DM9000_NCR, NCR_RST);
|
||||
udelay(1000); /* delay 1ms */
|
||||
}
|
||||
|
||||
/* Initilize dm9000 board
|
||||
*/
|
||||
int
|
||||
eth_init(bd_t * bd)
|
||||
{
|
||||
int i, oft, lnk;
|
||||
DM9000_DBG("eth_init()\n");
|
||||
|
||||
/* RESET device */
|
||||
dm9000_reset();
|
||||
dm9000_probe();
|
||||
|
||||
/* NIC Type: FASTETHER, HOMERUN, LONGRUN */
|
||||
identify_nic();
|
||||
|
||||
/* GPIO0 on pre-activate PHY */
|
||||
DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */
|
||||
|
||||
/* Set PHY */
|
||||
set_PHY_mode();
|
||||
|
||||
/* Program operating register */
|
||||
DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */
|
||||
DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */
|
||||
DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
|
||||
DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
|
||||
DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */
|
||||
DM9000_iow(DM9000_SMCR, 0); /* Special Mode */
|
||||
DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
|
||||
DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */
|
||||
|
||||
/* Set Node address */
|
||||
for (i = 0; i < 6; i++)
|
||||
((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
|
||||
printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
|
||||
bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
|
||||
bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
|
||||
for (i = 0, oft = 0x10; i < 6; i++, oft++)
|
||||
DM9000_iow(oft, bd->bi_enetaddr[i]);
|
||||
for (i = 0, oft = 0x16; i < 8; i++, oft++)
|
||||
DM9000_iow(oft, 0xff);
|
||||
|
||||
/* read back mac, just to be sure */
|
||||
for (i = 0, oft = 0x10; i < 6; i++, oft++)
|
||||
DM9000_DBG("%02x:", DM9000_ior(oft));
|
||||
DM9000_DBG("\n");
|
||||
|
||||
/* Activate DM9000 */
|
||||
DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
|
||||
DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */
|
||||
i = 0;
|
||||
while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
|
||||
udelay(1000);
|
||||
i++;
|
||||
if (i == 10000) {
|
||||
printf("could not establish link\n");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* see what we've got */
|
||||
lnk = phy_read(17) >> 12;
|
||||
printf("operating at ");
|
||||
switch (lnk) {
|
||||
case 1:
|
||||
printf("10M half duplex ");
|
||||
break;
|
||||
case 2:
|
||||
printf("10M full duplex ");
|
||||
break;
|
||||
case 4:
|
||||
printf("100M half duplex ");
|
||||
break;
|
||||
case 8:
|
||||
printf("100M full duplex ");
|
||||
break;
|
||||
default:
|
||||
printf("unknown: %d ", lnk);
|
||||
break;
|
||||
}
|
||||
printf("mode\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
Hardware start transmission.
|
||||
Send a packet to media from the upper layer.
|
||||
*/
|
||||
int
|
||||
eth_send(volatile void *packet, int length)
|
||||
{
|
||||
char *data_ptr;
|
||||
u32 tmplen, i;
|
||||
int tmo;
|
||||
DM9000_DBG("eth_send: length: %d\n", length);
|
||||
for (i = 0; i < length; i++) {
|
||||
if (i % 8 == 0)
|
||||
DM9000_DBG("\nSend: 02x: ", i);
|
||||
DM9000_DBG("%02x ", ((unsigned char *) packet)[i]);
|
||||
} DM9000_DBG("\n");
|
||||
|
||||
/* Move data to DM9000 TX RAM */
|
||||
data_ptr = (char *) packet;
|
||||
DM9000_outb(DM9000_MWCMD, DM9000_IO);
|
||||
|
||||
#ifdef CONFIG_DM9000_USE_8BIT
|
||||
/* Byte mode */
|
||||
for (i = 0; i < length; i++)
|
||||
DM9000_outb((data_ptr[i] & 0xff), DM9000_DATA);
|
||||
|
||||
#endif /* */
|
||||
#ifdef CONFIG_DM9000_USE_16BIT
|
||||
tmplen = (length + 1) / 2;
|
||||
for (i = 0; i < tmplen; i++)
|
||||
DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
|
||||
|
||||
#endif /* */
|
||||
#ifdef CONFIG_DM9000_USE_32BIT
|
||||
tmplen = (length + 3) / 4;
|
||||
for (i = 0; i < tmplen; i++)
|
||||
DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
|
||||
|
||||
#endif /* */
|
||||
|
||||
/* Set TX length to DM9000 */
|
||||
DM9000_iow(DM9000_TXPLL, length & 0xff);
|
||||
DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
|
||||
|
||||
/* Issue TX polling command */
|
||||
DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
|
||||
|
||||
/* wait for end of transmission */
|
||||
tmo = get_timer(0) + 5 * CFG_HZ;
|
||||
while (DM9000_ior(DM9000_TCR) & TCR_TXREQ) {
|
||||
if (get_timer(0) >= tmo) {
|
||||
printf("transmission timeout\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
DM9000_DBG("transmit done\n\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
Stop the interface.
|
||||
The interface is stopped when it is brought.
|
||||
*/
|
||||
void
|
||||
eth_halt(void)
|
||||
{
|
||||
DM9000_DBG("eth_halt\n");
|
||||
|
||||
/* RESET devie */
|
||||
phy_write(0, 0x8000); /* PHY RESET */
|
||||
DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
|
||||
DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
|
||||
DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
|
||||
}
|
||||
|
||||
/*
|
||||
Received a packet and pass to upper layer
|
||||
*/
|
||||
int
|
||||
eth_rx(void)
|
||||
{
|
||||
u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
|
||||
u16 RxStatus, RxLen = 0;
|
||||
u32 tmplen, i;
|
||||
|
||||
/* Check packet ready or not */
|
||||
DM9000_ior(DM9000_MRCMDX); /* Dummy read */
|
||||
rxbyte = DM9000_inb(DM9000_DATA); /* Got most updated data */
|
||||
if (rxbyte == 0)
|
||||
return 0;
|
||||
|
||||
/* Status check: this byte must be 0 or 1 */
|
||||
if (rxbyte > 1) {
|
||||
DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
|
||||
DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
|
||||
DM9000_DBG("rx status check: %d\n", rxbyte);
|
||||
}
|
||||
DM9000_DBG("receiving packet\n");
|
||||
|
||||
/* A packet ready now & Get status/length */
|
||||
DM9000_outb(DM9000_MRCMD, DM9000_IO);
|
||||
|
||||
#ifdef CONFIG_DM9000_USE_8BIT
|
||||
RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
|
||||
RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
|
||||
|
||||
#endif /* */
|
||||
#ifdef CONFIG_DM9000_USE_16BIT
|
||||
RxStatus = DM9000_inw(DM9000_DATA);
|
||||
RxLen = DM9000_inw(DM9000_DATA);
|
||||
|
||||
#endif /* */
|
||||
#ifdef CONFIG_DM9000_USE_32BIT
|
||||
tmpdata = DM9000_inl(DM9000_DATA);
|
||||
RxStatus = tmpdata;
|
||||
RxLen = tmpdata >> 16;
|
||||
|
||||
#endif /* */
|
||||
DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
|
||||
|
||||
/* Move data from DM9000 */
|
||||
/* Read received packet from RX SRAM */
|
||||
#ifdef CONFIG_DM9000_USE_8BIT
|
||||
for (i = 0; i < RxLen; i++)
|
||||
rdptr[i] = DM9000_inb(DM9000_DATA);
|
||||
|
||||
#endif /* */
|
||||
#ifdef CONFIG_DM9000_USE_16BIT
|
||||
tmplen = (RxLen + 1) / 2;
|
||||
for (i = 0; i < tmplen; i++)
|
||||
((u16 *) rdptr)[i] = DM9000_inw(DM9000_DATA);
|
||||
|
||||
#endif /* */
|
||||
#ifdef CONFIG_DM9000_USE_32BIT
|
||||
tmplen = (RxLen + 3) / 4;
|
||||
for (i = 0; i < tmplen; i++)
|
||||
((u32 *) rdptr)[i] = DM9000_inl(DM9000_DATA);
|
||||
|
||||
#endif /* */
|
||||
if ((RxStatus & 0xbf00) || (RxLen < 0x40)
|
||||
|| (RxLen > DM9000_PKT_MAX)) {
|
||||
if (RxStatus & 0x100) {
|
||||
printf("rx fifo error\n");
|
||||
}
|
||||
if (RxStatus & 0x200) {
|
||||
printf("rx crc error\n");
|
||||
}
|
||||
if (RxStatus & 0x8000) {
|
||||
printf("rx length error\n");
|
||||
}
|
||||
if (RxLen > DM9000_PKT_MAX) {
|
||||
printf("rx length too big\n");
|
||||
dm9000_reset();
|
||||
}
|
||||
} else {
|
||||
|
||||
/* Pass to upper layer */
|
||||
DM9000_DBG("passing packet to upper layer\n");
|
||||
NetReceive(NetRxPackets[0], RxLen);
|
||||
return RxLen;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
Read a word data from SROM
|
||||
*/
|
||||
static u16
|
||||
read_srom_word(int offset)
|
||||
{
|
||||
DM9000_iow(DM9000_EPAR, offset);
|
||||
DM9000_iow(DM9000_EPCR, 0x4);
|
||||
udelay(200);
|
||||
DM9000_iow(DM9000_EPCR, 0x0);
|
||||
return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
|
||||
}
|
||||
|
||||
/*
|
||||
Read a byte from I/O port
|
||||
*/
|
||||
static u8
|
||||
DM9000_ior(int reg)
|
||||
{
|
||||
DM9000_outb(reg, DM9000_IO);
|
||||
return DM9000_inb(DM9000_DATA);
|
||||
}
|
||||
|
||||
/*
|
||||
Write a byte to I/O port
|
||||
*/
|
||||
static void
|
||||
DM9000_iow(int reg, u8 value)
|
||||
{
|
||||
DM9000_outb(reg, DM9000_IO);
|
||||
DM9000_outb(value, DM9000_DATA);
|
||||
}
|
||||
|
||||
/*
|
||||
Read a word from phyxcer
|
||||
*/
|
||||
static u16
|
||||
phy_read(int reg)
|
||||
{
|
||||
u16 val;
|
||||
|
||||
/* Fill the phyxcer register into REG_0C */
|
||||
DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
|
||||
DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
|
||||
udelay(100); /* Wait read complete */
|
||||
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
|
||||
val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
|
||||
|
||||
/* The read data keeps on REG_0D & REG_0E */
|
||||
DM9000_DBG("phy_read(%d): %d\n", reg, val);
|
||||
return val;
|
||||
}
|
||||
|
||||
/*
|
||||
Write a word to phyxcer
|
||||
*/
|
||||
static void
|
||||
phy_write(int reg, u16 value)
|
||||
{
|
||||
|
||||
/* Fill the phyxcer register into REG_0C */
|
||||
DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
|
||||
|
||||
/* Fill the written data into REG_0D & REG_0E */
|
||||
DM9000_iow(DM9000_EPDRL, (value & 0xff));
|
||||
DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
|
||||
DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
|
||||
udelay(500); /* Wait write complete */
|
||||
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
|
||||
DM9000_DBG("phy_write(reg:%d, value:%d)\n", reg, value);
|
||||
}
|
||||
#endif /* CONFIG_DRIVER_DM9000 */
|
119
drivers/dm9000x.h
Normal file
119
drivers/dm9000x.h
Normal file
|
@ -0,0 +1,119 @@
|
|||
/*
|
||||
* dm9000 Ethernet
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_DRIVER_DM9000
|
||||
|
||||
#define DM9000_ID 0x90000A46
|
||||
#define DM9000_PKT_MAX 1536 /* Received packet max size */
|
||||
#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
|
||||
|
||||
/* although the registers are 16 bit, they are 32-bit aligned.
|
||||
*/
|
||||
|
||||
#define DM9000_NCR 0x00
|
||||
#define DM9000_NSR 0x01
|
||||
#define DM9000_TCR 0x02
|
||||
#define DM9000_TSR1 0x03
|
||||
#define DM9000_TSR2 0x04
|
||||
#define DM9000_RCR 0x05
|
||||
#define DM9000_RSR 0x06
|
||||
#define DM9000_ROCR 0x07
|
||||
#define DM9000_BPTR 0x08
|
||||
#define DM9000_FCTR 0x09
|
||||
#define DM9000_FCR 0x0A
|
||||
#define DM9000_EPCR 0x0B
|
||||
#define DM9000_EPAR 0x0C
|
||||
#define DM9000_EPDRL 0x0D
|
||||
#define DM9000_EPDRH 0x0E
|
||||
#define DM9000_WCR 0x0F
|
||||
|
||||
#define DM9000_PAR 0x10
|
||||
#define DM9000_MAR 0x16
|
||||
|
||||
#define DM9000_GPCR 0x1e
|
||||
#define DM9000_GPR 0x1f
|
||||
#define DM9000_TRPAL 0x22
|
||||
#define DM9000_TRPAH 0x23
|
||||
#define DM9000_RWPAL 0x24
|
||||
#define DM9000_RWPAH 0x25
|
||||
|
||||
#define DM9000_VIDL 0x28
|
||||
#define DM9000_VIDH 0x29
|
||||
#define DM9000_PIDL 0x2A
|
||||
#define DM9000_PIDH 0x2B
|
||||
|
||||
#define DM9000_CHIPR 0x2C
|
||||
#define DM9000_SMCR 0x2F
|
||||
|
||||
#define DM9000_PHY 0x40 /* PHY address 0x01 */
|
||||
|
||||
#define DM9000_MRCMDX 0xF0
|
||||
#define DM9000_MRCMD 0xF2
|
||||
#define DM9000_MRRL 0xF4
|
||||
#define DM9000_MRRH 0xF5
|
||||
#define DM9000_MWCMDX 0xF6
|
||||
#define DM9000_MWCMD 0xF8
|
||||
#define DM9000_MWRL 0xFA
|
||||
#define DM9000_MWRH 0xFB
|
||||
#define DM9000_TXPLL 0xFC
|
||||
#define DM9000_TXPLH 0xFD
|
||||
#define DM9000_ISR 0xFE
|
||||
#define DM9000_IMR 0xFF
|
||||
|
||||
#define NCR_EXT_PHY (1<<7)
|
||||
#define NCR_WAKEEN (1<<6)
|
||||
#define NCR_FCOL (1<<4)
|
||||
#define NCR_FDX (1<<3)
|
||||
#define NCR_LBK (3<<1)
|
||||
#define NCR_RST (1<<0)
|
||||
|
||||
#define NSR_SPEED (1<<7)
|
||||
#define NSR_LINKST (1<<6)
|
||||
#define NSR_WAKEST (1<<5)
|
||||
#define NSR_TX2END (1<<3)
|
||||
#define NSR_TX1END (1<<2)
|
||||
#define NSR_RXOV (1<<1)
|
||||
|
||||
#define TCR_TJDIS (1<<6)
|
||||
#define TCR_EXCECM (1<<5)
|
||||
#define TCR_PAD_DIS2 (1<<4)
|
||||
#define TCR_CRC_DIS2 (1<<3)
|
||||
#define TCR_PAD_DIS1 (1<<2)
|
||||
#define TCR_CRC_DIS1 (1<<1)
|
||||
#define TCR_TXREQ (1<<0)
|
||||
|
||||
#define TSR_TJTO (1<<7)
|
||||
#define TSR_LC (1<<6)
|
||||
#define TSR_NC (1<<5)
|
||||
#define TSR_LCOL (1<<4)
|
||||
#define TSR_COL (1<<3)
|
||||
#define TSR_EC (1<<2)
|
||||
|
||||
#define RCR_WTDIS (1<<6)
|
||||
#define RCR_DIS_LONG (1<<5)
|
||||
#define RCR_DIS_CRC (1<<4)
|
||||
#define RCR_ALL (1<<3)
|
||||
#define RCR_RUNT (1<<2)
|
||||
#define RCR_PRMSC (1<<1)
|
||||
#define RCR_RXEN (1<<0)
|
||||
|
||||
#define RSR_RF (1<<7)
|
||||
#define RSR_MF (1<<6)
|
||||
#define RSR_LCS (1<<5)
|
||||
#define RSR_RWTO (1<<4)
|
||||
#define RSR_PLE (1<<3)
|
||||
#define RSR_AE (1<<2)
|
||||
#define RSR_CE (1<<1)
|
||||
#define RSR_FOE (1<<0)
|
||||
|
||||
#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
|
||||
#define FCTR_LWOT(ot) ( ot & 0xf )
|
||||
|
||||
#define IMR_PAR (1<<7)
|
||||
#define IMR_ROOM (1<<3)
|
||||
#define IMR_ROM (1<<2)
|
||||
#define IMR_PTM (1<<1)
|
||||
#define IMR_PRM (1<<0)
|
||||
|
||||
#endif
|
201
drivers/serial_imx.c
Normal file
201
drivers/serial_imx.c
Normal file
|
@ -0,0 +1,201 @@
|
|||
/*
|
||||
* (c) 2004 Sascha Hauer <sascha@saschahauer.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#if defined (CONFIG_IMX)
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#ifndef CONFIG_IMX_SERIAL_NONE
|
||||
|
||||
#if defined CONFIG_IMX_SERIAL1
|
||||
#define UART_BASE IMX_UART1_BASE
|
||||
#elif defined CONFIG_IMX_SERIAL2
|
||||
#define UART_BASE IMX_UART2_BASE
|
||||
#else
|
||||
#error "define CONFIG_IMX_SERIAL1, CONFIG_IMX_SERIAL2 or CONFIG_IMX_SERIAL_NONE"
|
||||
#endif
|
||||
|
||||
struct imx_serial {
|
||||
volatile uint32_t urxd[16];
|
||||
volatile uint32_t utxd[16];
|
||||
volatile uint32_t ucr1;
|
||||
volatile uint32_t ucr2;
|
||||
volatile uint32_t ucr3;
|
||||
volatile uint32_t ucr4;
|
||||
volatile uint32_t ufcr;
|
||||
volatile uint32_t usr1;
|
||||
volatile uint32_t usr2;
|
||||
volatile uint32_t uesc;
|
||||
volatile uint32_t utim;
|
||||
volatile uint32_t ubir;
|
||||
volatile uint32_t ubmr;
|
||||
volatile uint32_t ubrc;
|
||||
volatile uint32_t bipr[4];
|
||||
volatile uint32_t bmpr[4];
|
||||
volatile uint32_t uts;
|
||||
};
|
||||
|
||||
void serial_setbrg (void)
|
||||
{
|
||||
serial_init();
|
||||
}
|
||||
|
||||
extern void imx_gpio_mode(int gpio_mode);
|
||||
|
||||
/*
|
||||
* Initialise the serial port with the given baudrate. The settings
|
||||
* are always 8 data bits, no parity, 1 stop bit, no start bits.
|
||||
*
|
||||
*/
|
||||
int serial_init (void)
|
||||
{
|
||||
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
|
||||
#ifdef CONFIG_IMX_SERIAL1
|
||||
imx_gpio_mode(PC11_PF_UART1_TXD);
|
||||
imx_gpio_mode(PC12_PF_UART1_RXD);
|
||||
#else
|
||||
imx_gpio_mode(PB30_PF_UART2_TXD);
|
||||
imx_gpio_mode(PB31_PF_UART2_RXD);
|
||||
#endif
|
||||
|
||||
/* Disable UART */
|
||||
base->ucr1 &= ~UCR1_UARTEN;
|
||||
|
||||
/* Set to default POR state */
|
||||
|
||||
base->ucr1 = 0x00000004;
|
||||
base->ucr2 = 0x00000000;
|
||||
base->ucr3 = 0x00000000;
|
||||
base->ucr4 = 0x00008040;
|
||||
base->uesc = 0x0000002B;
|
||||
base->utim = 0x00000000;
|
||||
base->ubir = 0x00000000;
|
||||
base->ubmr = 0x00000000;
|
||||
base->uts = 0x00000000;
|
||||
/* Set clocks */
|
||||
base->ucr4 |= UCR4_REF16;
|
||||
|
||||
/* Configure FIFOs */
|
||||
base->ufcr = 0xa81;
|
||||
|
||||
/* Set the numerator value minus one of the BRM ratio */
|
||||
base->ubir = (CONFIG_BAUDRATE / 100) - 1;
|
||||
|
||||
/* Set the denominator value minus one of the BRM ratio */
|
||||
base->ubmr = 10000 - 1;
|
||||
|
||||
/* Set to 8N1 */
|
||||
base->ucr2 &= ~UCR2_PREN;
|
||||
base->ucr2 |= UCR2_WS;
|
||||
base->ucr2 &= ~UCR2_STPB;
|
||||
|
||||
/* Ignore RTS */
|
||||
base->ucr2 |= UCR2_IRTS;
|
||||
|
||||
/* Enable UART */
|
||||
base->ucr1 |= UCR1_UARTEN | UCR1_UARTCLKEN;
|
||||
|
||||
/* Enable FIFOs */
|
||||
base->ucr2 |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN;
|
||||
|
||||
/* Clear status flags */
|
||||
base->usr2 |= USR2_ADET |
|
||||
USR2_DTRF |
|
||||
USR2_IDLE |
|
||||
USR2_IRINT |
|
||||
USR2_WAKE |
|
||||
USR2_RTSF |
|
||||
USR2_BRCD |
|
||||
USR2_ORE |
|
||||
USR2_RDR;
|
||||
|
||||
/* Clear status flags */
|
||||
base->usr1 |= USR1_PARITYERR |
|
||||
USR1_RTSD |
|
||||
USR1_ESCF |
|
||||
USR1_FRAMERR |
|
||||
USR1_AIRINT |
|
||||
USR1_AWAKE;
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read a single byte from the serial port. Returns 1 on success, 0
|
||||
* otherwise. When the function is successful, the character read is
|
||||
* written into its argument c.
|
||||
*/
|
||||
int serial_getc (void)
|
||||
{
|
||||
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
|
||||
unsigned char ch;
|
||||
|
||||
while(base->uts & UTS_RXEMPTY);
|
||||
|
||||
ch = (char)base->urxd[0];
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HWFLOW
|
||||
static int hwflow = 0; /* turned off by default */
|
||||
int hwflow_onoff(int on)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Output a single byte to the serial port.
|
||||
*/
|
||||
void serial_putc (const char c)
|
||||
{
|
||||
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
|
||||
|
||||
/* Wait for Tx FIFO not full */
|
||||
while (base->uts & UTS_TXFULL);
|
||||
|
||||
base->utxd[0] = c;
|
||||
|
||||
/* If \n, also do \r */
|
||||
if (c == '\n')
|
||||
serial_putc ('\r');
|
||||
}
|
||||
|
||||
/*
|
||||
* Test whether a character is in the RX buffer
|
||||
*/
|
||||
int serial_tstc (void)
|
||||
{
|
||||
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
|
||||
|
||||
/* If receive fifo is empty, return false */
|
||||
if (base->uts & UTS_RXEMPTY)
|
||||
return 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
void
|
||||
serial_puts (const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
serial_putc (*s++);
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_IMX_SERIAL_NONE */
|
||||
#endif /* defined CONFIG_IMX */
|
571
include/asm-arm/arch-arm920t/imx-regs.h
Normal file
571
include/asm-arm/arch-arm920t/imx-regs.h
Normal file
|
@ -0,0 +1,571 @@
|
|||
#ifndef _IMX_REGS_H
|
||||
#define _IMX_REGS_H
|
||||
/* ------------------------------------------------------------------------
|
||||
* Motorola IMX system registers
|
||||
* ------------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
|
||||
# ifndef __ASSEMBLY__
|
||||
# define __REG(x) (*((volatile u32 *)(x)))
|
||||
# define __REG2(x,y) \
|
||||
( __builtin_constant_p(y) ? (__REG((x) + (y))) \
|
||||
: (*(volatile u32 *)((u32)&__REG(x) + (y))) )
|
||||
# else
|
||||
# define __REG(x) (x)
|
||||
# define __REG2(x,y) ((x)+(y))
|
||||
#endif
|
||||
|
||||
#define IMX_IO_BASE 0x00200000
|
||||
|
||||
/*
|
||||
* Register BASEs, based on OFFSETs
|
||||
*
|
||||
*/
|
||||
#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
|
||||
#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE)
|
||||
#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE)
|
||||
#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)
|
||||
#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE)
|
||||
#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)
|
||||
#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE)
|
||||
#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE)
|
||||
#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)
|
||||
#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)
|
||||
#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)
|
||||
#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)
|
||||
#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)
|
||||
#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)
|
||||
#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
|
||||
#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
|
||||
#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
|
||||
#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)
|
||||
#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
|
||||
#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
|
||||
#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
|
||||
#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)
|
||||
#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE)
|
||||
#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)
|
||||
#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)
|
||||
#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)
|
||||
#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)
|
||||
#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
|
||||
#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
|
||||
|
||||
/* SYSCTRL Registers */
|
||||
#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */
|
||||
#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
|
||||
#define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */
|
||||
|
||||
/* Chip Select Registers */
|
||||
#define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */
|
||||
#define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */
|
||||
#define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */
|
||||
#define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */
|
||||
#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
|
||||
#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
|
||||
#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
|
||||
#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */
|
||||
#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
|
||||
#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
|
||||
#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
|
||||
#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */
|
||||
#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
|
||||
|
||||
/* SDRAM controller registers */
|
||||
|
||||
#define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */
|
||||
#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */
|
||||
#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */
|
||||
#define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */
|
||||
|
||||
/* PLL registers */
|
||||
#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
|
||||
#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
|
||||
#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
|
||||
#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
|
||||
#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
|
||||
#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
|
||||
|
||||
#define CSCR_MPLL_RESTART (1<<21)
|
||||
|
||||
/*
|
||||
* GPIO Module and I/O Multiplexer
|
||||
* x = 0..3 for reg_A, reg_B, reg_C, reg_D
|
||||
*/
|
||||
#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
|
||||
#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
|
||||
#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
|
||||
#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
|
||||
#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
|
||||
#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
|
||||
#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
|
||||
#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
|
||||
#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
|
||||
#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
|
||||
#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
|
||||
#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
|
||||
#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
|
||||
#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
|
||||
#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
|
||||
#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
|
||||
#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
|
||||
|
||||
#define GPIO_PIN_MASK 0x1f
|
||||
#define GPIO_PORT_MASK (0x3 << 5)
|
||||
|
||||
#define GPIO_PORTA (0<<5)
|
||||
#define GPIO_PORTB (1<<5)
|
||||
#define GPIO_PORTC (2<<5)
|
||||
#define GPIO_PORTD (3<<5)
|
||||
|
||||
#define GPIO_OUT (1<<7)
|
||||
#define GPIO_IN (0<<7)
|
||||
#define GPIO_PUEN (1<<8)
|
||||
|
||||
#define GPIO_PF (0<<9)
|
||||
#define GPIO_AF (1<<9)
|
||||
|
||||
#define GPIO_OCR_MASK (3<<10)
|
||||
#define GPIO_AIN (0<<10)
|
||||
#define GPIO_BIN (1<<10)
|
||||
#define GPIO_CIN (2<<10)
|
||||
#define GPIO_GPIO (3<<10)
|
||||
|
||||
#define GPIO_AOUT (1<<12)
|
||||
#define GPIO_BOUT (1<<13)
|
||||
|
||||
/* assignements for GPIO alternate/primary functions */
|
||||
|
||||
/* FIXME: This list is not completed. The correct directions are
|
||||
* missing on some (many) pins
|
||||
*/
|
||||
#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 )
|
||||
#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
|
||||
#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
|
||||
#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
|
||||
#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
|
||||
#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
|
||||
#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
|
||||
#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
|
||||
#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
|
||||
#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
|
||||
#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
|
||||
#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
|
||||
#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
|
||||
#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
|
||||
#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
|
||||
#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
|
||||
#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
|
||||
#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
|
||||
#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
|
||||
#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
|
||||
#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
|
||||
#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 )
|
||||
#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
|
||||
#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
|
||||
#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
|
||||
#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
|
||||
#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
|
||||
#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
|
||||
#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
|
||||
#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
|
||||
#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
|
||||
#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
|
||||
#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
|
||||
#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
|
||||
#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
|
||||
#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
|
||||
#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
|
||||
#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
|
||||
#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
|
||||
#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
|
||||
#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
|
||||
#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
|
||||
#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
|
||||
#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
|
||||
#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
|
||||
#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
|
||||
#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
|
||||
#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
|
||||
#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
|
||||
#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
|
||||
#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 )
|
||||
#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
|
||||
#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 )
|
||||
#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
|
||||
#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 )
|
||||
#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
|
||||
#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
|
||||
#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
|
||||
#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
|
||||
#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
|
||||
#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
|
||||
#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
|
||||
#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
|
||||
#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
|
||||
#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
|
||||
#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
|
||||
#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
|
||||
#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
|
||||
#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
|
||||
#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
|
||||
#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
|
||||
#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
|
||||
#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
|
||||
#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
|
||||
#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
|
||||
#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
|
||||
#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
|
||||
#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
|
||||
#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
|
||||
#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
|
||||
#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
|
||||
#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
|
||||
#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
|
||||
#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
|
||||
#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
|
||||
#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
|
||||
#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
|
||||
#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
|
||||
#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
|
||||
#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
|
||||
#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
|
||||
#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
|
||||
#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 )
|
||||
#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
|
||||
#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
|
||||
#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 )
|
||||
#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
|
||||
#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
|
||||
#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
|
||||
#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
|
||||
#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
|
||||
#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
|
||||
#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
|
||||
#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
|
||||
#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
|
||||
#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
|
||||
#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
|
||||
#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
|
||||
#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
|
||||
#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
|
||||
#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
|
||||
#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
|
||||
#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
|
||||
#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
|
||||
#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
|
||||
#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
|
||||
#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
|
||||
#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
|
||||
#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
|
||||
#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
|
||||
#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
|
||||
#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
|
||||
#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
|
||||
#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 )
|
||||
|
||||
/*
|
||||
* DMA Controller
|
||||
*/
|
||||
#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */
|
||||
#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */
|
||||
#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */
|
||||
#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */
|
||||
#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */
|
||||
#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */
|
||||
#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */
|
||||
#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */
|
||||
#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */
|
||||
#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */
|
||||
#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */
|
||||
#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */
|
||||
#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */
|
||||
#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */
|
||||
#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
|
||||
#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
|
||||
#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
|
||||
#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */
|
||||
#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
|
||||
#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
|
||||
#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
|
||||
#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */
|
||||
|
||||
/* TODO: define DMA_REQ lines */
|
||||
|
||||
#define DCR_DRST (1<<1)
|
||||
#define DCR_DEN (1<<0)
|
||||
#define DBTOCR_EN (1<<15)
|
||||
#define DBTOCR_CNT(x) ((x) & 0x7fff )
|
||||
#define CNTR_CNT(x) ((x) & 0xffffff )
|
||||
#define CCR_DMOD_LINEAR ( 0x0 << 12 )
|
||||
#define CCR_DMOD_2D ( 0x1 << 12 )
|
||||
#define CCR_DMOD_FIFO ( 0x2 << 12 )
|
||||
#define CCR_DMOD_EOBFIFO ( 0x3 << 12 )
|
||||
#define CCR_SMOD_LINEAR ( 0x0 << 10 )
|
||||
#define CCR_SMOD_2D ( 0x1 << 10 )
|
||||
#define CCR_SMOD_FIFO ( 0x2 << 10 )
|
||||
#define CCR_SMOD_EOBFIFO ( 0x3 << 10 )
|
||||
#define CCR_MDIR_DEC (1<<9)
|
||||
#define CCR_MSEL_B (1<<8)
|
||||
#define CCR_DSIZ_32 ( 0x0 << 6 )
|
||||
#define CCR_DSIZ_8 ( 0x1 << 6 )
|
||||
#define CCR_DSIZ_16 ( 0x2 << 6 )
|
||||
#define CCR_SSIZ_32 ( 0x0 << 4 )
|
||||
#define CCR_SSIZ_8 ( 0x1 << 4 )
|
||||
#define CCR_SSIZ_16 ( 0x2 << 4 )
|
||||
#define CCR_REN (1<<3)
|
||||
#define CCR_RPT (1<<2)
|
||||
#define CCR_FRC (1<<1)
|
||||
#define CCR_CEN (1<<0)
|
||||
#define RTOR_EN (1<<15)
|
||||
#define RTOR_CLK (1<<14)
|
||||
#define RTOR_PSC (1<<13)
|
||||
|
||||
/*
|
||||
* LCD Controller
|
||||
*/
|
||||
|
||||
#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00)
|
||||
|
||||
#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04)
|
||||
#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
|
||||
#define SIZE_YMAX(y) ( (y) & 0x1ff )
|
||||
|
||||
#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08)
|
||||
#define VPW_VPW(x) ( (x) & 0x3ff )
|
||||
|
||||
#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C)
|
||||
#define CPOS_CC1 (1<<31)
|
||||
#define CPOS_CC0 (1<<30)
|
||||
#define CPOS_OP (1<<28)
|
||||
#define CPOS_CXP(x) (((x) & 3ff) << 16)
|
||||
#define CPOS_CYP(y) ((y) & 0x1ff)
|
||||
|
||||
#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10)
|
||||
#define LCWHB_BK_EN (1<<31)
|
||||
#define LCWHB_CW(w) (((w) & 0x1f) << 24)
|
||||
#define LCWHB_CH(h) (((h) & 0x1f) << 16)
|
||||
#define LCWHB_BD(x) ((x) & 0xff)
|
||||
|
||||
#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14)
|
||||
#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
|
||||
#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
|
||||
#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
|
||||
|
||||
#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18)
|
||||
#define PCR_TFT (1<<31)
|
||||
#define PCR_COLOR (1<<30)
|
||||
#define PCR_PBSIZ_1 (0<<28)
|
||||
#define PCR_PBSIZ_2 (1<<28)
|
||||
#define PCR_PBSIZ_4 (2<<28)
|
||||
#define PCR_PBSIZ_8 (3<<28)
|
||||
#define PCR_BPIX_1 (0<<25)
|
||||
#define PCR_BPIX_2 (1<<25)
|
||||
#define PCR_BPIX_4 (2<<25)
|
||||
#define PCR_BPIX_8 (3<<25)
|
||||
#define PCR_BPIX_12 (4<<25)
|
||||
#define PCR_BPIX_16 (4<<25)
|
||||
#define PCR_PIXPOL (1<<24)
|
||||
#define PCR_FLMPOL (1<<23)
|
||||
#define PCR_LPPOL (1<<22)
|
||||
#define PCR_CLKPOL (1<<21)
|
||||
#define PCR_OEPOL (1<<20)
|
||||
#define PCR_SCLKIDLE (1<<19)
|
||||
#define PCR_END_SEL (1<<18)
|
||||
#define PCR_END_BYTE_SWAP (1<<17)
|
||||
#define PCR_REV_VS (1<<16)
|
||||
#define PCR_ACD_SEL (1<<15)
|
||||
#define PCR_ACD(x) (((x) & 0x7f) << 8)
|
||||
#define PCR_SCLK_SEL (1<<7)
|
||||
#define PCR_SHARP (1<<6)
|
||||
#define PCR_PCD(x) ((x) & 0x3f)
|
||||
|
||||
#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C)
|
||||
#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
|
||||
#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
|
||||
#define HCR_H_WAIT_2(x) ((x) & 0xff)
|
||||
|
||||
#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20)
|
||||
#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
|
||||
#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
|
||||
#define VCR_V_WAIT_2(x) ((x) & 0xff)
|
||||
|
||||
#define LCDC_POS __REG(IMX_LCDC_BASE+0x24)
|
||||
#define POS_POS(x) ((x) & 1f)
|
||||
|
||||
#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28)
|
||||
#define LSCR1_GRAY1(x) (((x) & 0xf) << 4)
|
||||
#define LSCR1_GRAY2(x) ((x) & 0xf)
|
||||
|
||||
#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C)
|
||||
#define PWMR_CLS(x) (((x) & 0x1ff) << 16)
|
||||
#define PWMR_LDMSK (1<<15)
|
||||
#define PWMR_SCR1 (1<<10)
|
||||
#define PWMR_SCR0 (1<<9)
|
||||
#define PWMR_CC_EN (1<<8)
|
||||
#define PWMR_PW(x) ((x) & 0xff)
|
||||
|
||||
#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30)
|
||||
#define DMACR_BURST (1<<31)
|
||||
#define DMACR_HM(x) (((x) & 0xf) << 16)
|
||||
#define DMACR_TM(x) ((x) &0xf)
|
||||
|
||||
#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34)
|
||||
#define RMCR_LCDC_EN (1<<1)
|
||||
#define RMCR_SELF_REF (1<<0)
|
||||
|
||||
#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38)
|
||||
#define LCDICR_INT_SYN (1<<2)
|
||||
#define LCDICR_INT_CON (1)
|
||||
|
||||
#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40)
|
||||
#define LCDISR_UDR_ERR (1<<3)
|
||||
#define LCDISR_ERR_RES (1<<2)
|
||||
#define LCDISR_EOF (1<<1)
|
||||
#define LCDISR_BOF (1<<0)
|
||||
/*
|
||||
* UART Module
|
||||
*/
|
||||
#define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12) /* Receiver Register */
|
||||
#define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12) /* Transmitter Register */
|
||||
#define UCR1(x) __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12) /* Control Register 1 */
|
||||
#define UCR2(x) __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12) /* Control Register 2 */
|
||||
#define UCR3(x) __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12) /* Control Register 3 */
|
||||
#define UCR4(x) __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12) /* Control Register 4 */
|
||||
#define UFCR(x) __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12) /* FIFO Control Register */
|
||||
#define USR1(x) __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12) /* Status Register 1 */
|
||||
#define USR2(x) __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12) /* Status Register 2 */
|
||||
#define UESC(x) __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12) /* Escape Character Register */
|
||||
#define UTIM(x) __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12) /* Escape Timer Register */
|
||||
#define UBIR(x) __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12) /* BRM Incremental Register */
|
||||
#define UBMR(x) __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12) /* BRM Modulator Register */
|
||||
#define UBRC(x) __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12) /* Baud Rate Count Register */
|
||||
#define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12) /* Incremental Preset Register 1 */
|
||||
#define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12) /* Incremental Preset Register 2 */
|
||||
#define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12) /* Incremental Preset Register 3 */
|
||||
#define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12) /* Incremental Preset Register 4 */
|
||||
#define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12) /* BRM Modulator Register 1 */
|
||||
#define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12) /* BRM Modulator Register 2 */
|
||||
#define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12) /* BRM Modulator Register 3 */
|
||||
#define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12) /* BRM Modulator Register 4 */
|
||||
#define UTS(x) __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12) /* UART Test Register */
|
||||
|
||||
/* UART Control Register Bit Fields.*/
|
||||
#define URXD_CHARRDY (1<<15)
|
||||
#define URXD_ERR (1<<14)
|
||||
#define URXD_OVRRUN (1<<13)
|
||||
#define URXD_FRMERR (1<<12)
|
||||
#define URXD_BRK (1<<11)
|
||||
#define URXD_PRERR (1<<10)
|
||||
#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
|
||||
#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
|
||||
#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
|
||||
#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
|
||||
#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
|
||||
#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
|
||||
#define UCR1_IREN (1<<7) /* Infrared interface enable */
|
||||
#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
|
||||
#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
|
||||
#define UCR1_SNDBRK (1<<4) /* Send break */
|
||||
#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
|
||||
#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
|
||||
#define UCR1_DOZE (1<<1) /* Doze */
|
||||
#define UCR1_UARTEN (1<<0) /* UART enabled */
|
||||
#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
|
||||
#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
|
||||
#define UCR2_CTSC (1<<13) /* CTS pin control */
|
||||
#define UCR2_CTS (1<<12) /* Clear to send */
|
||||
#define UCR2_ESCEN (1<<11) /* Escape enable */
|
||||
#define UCR2_PREN (1<<8) /* Parity enable */
|
||||
#define UCR2_PROE (1<<7) /* Parity odd/even */
|
||||
#define UCR2_STPB (1<<6) /* Stop */
|
||||
#define UCR2_WS (1<<5) /* Word size */
|
||||
#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
|
||||
#define UCR2_TXEN (1<<2) /* Transmitter enabled */
|
||||
#define UCR2_RXEN (1<<1) /* Receiver enabled */
|
||||
#define UCR2_SRST (1<<0) /* SW reset */
|
||||
#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
|
||||
#define UCR3_PARERREN (1<<12) /* Parity enable */
|
||||
#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
|
||||
#define UCR3_DSR (1<<10) /* Data set ready */
|
||||
#define UCR3_DCD (1<<9) /* Data carrier detect */
|
||||
#define UCR3_RI (1<<8) /* Ring indicator */
|
||||
#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
|
||||
#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
|
||||
#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
|
||||
#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
|
||||
#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
|
||||
#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
|
||||
#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
|
||||
#define UCR3_BPEN (1<<0) /* Preset registers enable */
|
||||
#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
|
||||
#define UCR4_INVR (1<<9) /* Inverted infrared reception */
|
||||
#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
|
||||
#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
|
||||
#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
|
||||
#define UCR4_IRSC (1<<5) /* IR special case */
|
||||
#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
|
||||
#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
|
||||
#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
|
||||
#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
|
||||
#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
|
||||
#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
|
||||
#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
|
||||
#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
|
||||
#define USR1_RTSS (1<<14) /* RTS pin status */
|
||||
#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
|
||||
#define USR1_RTSD (1<<12) /* RTS delta */
|
||||
#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
|
||||
#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
|
||||
#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
|
||||
#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
|
||||
#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
|
||||
#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
|
||||
#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
|
||||
#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
|
||||
#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
|
||||
#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
|
||||
#define USR2_IDLE (1<<12) /* Idle condition */
|
||||
#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
|
||||
#define USR2_WAKE (1<<7) /* Wake */
|
||||
#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
|
||||
#define USR2_TXDC (1<<3) /* Transmitter complete */
|
||||
#define USR2_BRCD (1<<2) /* Break condition */
|
||||
#define USR2_ORE (1<<1) /* Overrun error */
|
||||
#define USR2_RDR (1<<0) /* Recv data ready */
|
||||
#define UTS_FRCPERR (1<<13) /* Force parity error */
|
||||
#define UTS_LOOP (1<<12) /* Loop tx and rx */
|
||||
#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
|
||||
#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
|
||||
#define UTS_TXFULL (1<<4) /* TxFIFO full */
|
||||
#define UTS_RXFULL (1<<3) /* RxFIFO full */
|
||||
#define UTS_SOFTRST (1<<0) /* Software reset */
|
||||
|
||||
/* General purpose timers registers */
|
||||
#define TCTL1 __REG(IMX_TIM1_BASE)
|
||||
#define TPRER1 __REG(IMX_TIM1_BASE + 0x4)
|
||||
#define TCMP1 __REG(IMX_TIM1_BASE + 0x8)
|
||||
#define TCR1 __REG(IMX_TIM1_BASE + 0xc)
|
||||
#define TCN1 __REG(IMX_TIM1_BASE + 0x10)
|
||||
#define TSTAT1 __REG(IMX_TIM1_BASE + 0x14)
|
||||
#define TCTL2 __REG(IMX_TIM2_BASE)
|
||||
#define TPRER2 __REG(IMX_TIM2_BASE + 0x4)
|
||||
#define TCMP2 __REG(IMX_TIM2_BASE + 0x8)
|
||||
#define TCR2 __REG(IMX_TIM2_BASE + 0xc)
|
||||
#define TCN2 __REG(IMX_TIM2_BASE + 0x10)
|
||||
#define TSTAT2 __REG(IMX_TIM2_BASE + 0x14)
|
||||
|
||||
/* General purpose timers bitfields */
|
||||
#define TCTL_SWR (1<<15) /* Software reset */
|
||||
#define TCTL_FRR (1<<8) /* Freerun / restart */
|
||||
#define TCTL_CAP (3<<6) /* Capture Edge */
|
||||
#define TCTL_OM (1<<5) /* output mode */
|
||||
#define TCTL_IRQEN (1<<4) /* interrupt enable */
|
||||
#define TCTL_CLKSOURCE (7<<1) /* Clock source */
|
||||
#define TCTL_TEN (1) /* Timer enable */
|
||||
#define TPRER_PRES (0xff) /* Prescale */
|
||||
#define TSTAT_CAPT (1<<1) /* Capture event */
|
||||
#define TSTAT_COMP (1) /* Compare event */
|
||||
|
||||
#endif /* _IMX_REGS_H */
|
|
@ -126,6 +126,17 @@ typedef void (interrupt_handler_t)(void *);
|
|||
# endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SERIAL_MULTI
|
||||
|
||||
#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) \
|
||||
|| defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
|
||||
|| defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
|
||||
|
||||
#define CONFIG_SERIAL_MULTI 1
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_SERIAL_MULTI */
|
||||
|
||||
/*
|
||||
* General Purpose Utilities
|
||||
|
@ -403,6 +414,15 @@ ulong get_PLLCLK (void);
|
|||
#if defined CONFIG_INCA_IP
|
||||
uint incaip_get_cpuclk (void);
|
||||
#endif
|
||||
#if defined(CONFIG_IMX)
|
||||
ulong get_systemPLLCLK(void);
|
||||
ulong get_FCLK(void);
|
||||
ulong get_HCLK(void);
|
||||
ulong get_BCLK(void);
|
||||
ulong get_PERCLK1(void);
|
||||
ulong get_PERCLK2(void);
|
||||
ulong get_PERCLK3(void);
|
||||
#endif
|
||||
ulong get_bus_freq (ulong);
|
||||
|
||||
#if defined(CONFIG_MPC85xx)
|
||||
|
|
|
@ -74,9 +74,10 @@
|
|||
#define CPM_I2C_BASE 0x0820
|
||||
#define CPM_SPI_BASE 0x0840
|
||||
#define CPM_FEC_BASE 0x0860
|
||||
#define CPM_WLKBD_BASE 0x0880
|
||||
#define CPM_SERIAL2_BASE 0x0880
|
||||
#define CPM_SCC_BASE 0x0900
|
||||
#define CPM_POST_BASE 0x0980
|
||||
#define CPM_WLKBD_BASE 0x0a00
|
||||
|
||||
#endif
|
||||
|
||||
|
@ -1041,7 +1042,7 @@ typedef struct scc_enet {
|
|||
|
||||
/*** LWMON **********************************************************/
|
||||
|
||||
#if defined(CONFIG_LWMON) && !defined(CONFIG_8xx_CONS_SCC2)
|
||||
#if defined(CONFIG_LWMON)
|
||||
/* Bits in parallel I/O port registers that have to be set/cleared
|
||||
* to configure the pins for SCC2 use.
|
||||
*/
|
||||
|
|
|
@ -43,6 +43,9 @@
|
|||
* CONFIG_PPCHAMELEON_CLK_25
|
||||
* CONFIG_PPCHAMELEON_CLK_33
|
||||
*/
|
||||
#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
|
||||
#define CONFIG_PPCHAMELEON_CLK_33
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
|
||||
#error "* Two external frequencies (SysClk) are defined! *"
|
||||
|
@ -74,11 +77,11 @@
|
|||
|
||||
|
||||
#ifdef CONFIG_PPCHAMELEON_CLK_25
|
||||
#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
|
||||
# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
|
||||
#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||
# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||
#else
|
||||
#error "* External frequency (SysClk) not defined! *"
|
||||
# error "* External frequency (SysClk) not defined! *"
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
|
|
@ -64,6 +64,7 @@
|
|||
* Video console
|
||||
*/
|
||||
#if 1
|
||||
#define CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_SED13806
|
||||
#define CONFIG_VIDEO_SED13806_16BPP
|
||||
|
||||
|
|
|
@ -47,11 +47,9 @@
|
|||
|
||||
#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
|
||||
|
||||
#if 1
|
||||
#define CONFIG_SERIAL_MULTI 1
|
||||
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
|
||||
#else
|
||||
#define CONFIG_8xx_CONS_SCC2
|
||||
#endif
|
||||
#define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */
|
||||
|
||||
|
@ -151,17 +149,6 @@
|
|||
#define CFG_CMD_POST_DIAG 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_8xx_CONS_SCC2 /* Can't use ethernet, then */
|
||||
#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_BSP | \
|
||||
CFG_CMD_BMP | \
|
||||
CFG_CMD_POST_DIAG )
|
||||
#else
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
|
@ -172,7 +159,6 @@
|
|||
CFG_CMD_BSP | \
|
||||
CFG_CMD_BMP | \
|
||||
CFG_CMD_POST_DIAG )
|
||||
#endif
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
|
|
|
@ -16,7 +16,7 @@
|
|||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
|
@ -25,7 +25,6 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
|
@ -40,14 +39,19 @@
|
|||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
|
||||
#define CONFIG_MC9328 1 /* It's a Motorola MC9328 SoC */
|
||||
#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */
|
||||
#define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */
|
||||
#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
/*
|
||||
* Select serial console configuration
|
||||
*/
|
||||
#define CONFIG_IMX_SERIAL1 /* internal uart 1 */
|
||||
/* #define _CONFIG_UART2 */ /* internal uart 2 */
|
||||
/* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */
|
||||
|
||||
#define BOARD_LATE_INIT 1
|
||||
|
||||
|
||||
#define USE_920T_MMU 1
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
#if 0
|
||||
#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
|
||||
|
@ -60,6 +64,8 @@
|
|||
*/
|
||||
|
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
|
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
/*
|
||||
|
@ -67,13 +73,13 @@
|
|||
*/
|
||||
#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
|
||||
#define CS8900_BASE 0x15000300
|
||||
#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
|
||||
#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_UART1 1
|
||||
/* #define CONFIG_UART1 */
|
||||
/* #define CONFIG_UART2 1 */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
@ -85,24 +91,20 @@
|
|||
#define CONFIG_COMMANDS \
|
||||
(CONFIG_CMD_DFL | \
|
||||
CFG_CMD_CACHE | \
|
||||
/*CFG_CMD_NAND |*/ \
|
||||
/*CFG_CMD_EEPROM |*/ \
|
||||
/*CFG_CMD_I2C |*/ \
|
||||
/*CFG_CMD_USB |*/ \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_ELF)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTARGS "root=/dev/docbp mem=48M"
|
||||
#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M"
|
||||
#define CONFIG_ETHADDR 08:00:3e:26:0a:5c
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_IPADDR 192.168.0.22
|
||||
#define CONFIG_SERVERIP 192.168.0.11
|
||||
#define CONFIG_BOOTFILE "mx1ads"
|
||||
/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
|
||||
#define CONFIG_BOOTCOMMAND "tftp; bootm"
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
|
||||
|
@ -114,10 +116,10 @@
|
|||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
||||
#define CFG_HUSH_PARSER 1
|
||||
#define CFG_HUSH_PARSER 1
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT "MX1ADS$ " /* Monitor Command Prompt */
|
||||
|
@ -125,21 +127,20 @@
|
|||
#define CFG_PROMPT "MX1ADS=> " /* Monitor Command Prompt */
|
||||
#endif
|
||||
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
|
||||
/* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x09000000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x08800000 /* default load address */
|
||||
|
||||
|
||||
#define CFG_HZ 1000
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
#define CFG_LOAD_ADDR 0x08800000 /* default load address */
|
||||
/*#define CFG_HZ 1000 */
|
||||
#define CFG_HZ 3686400
|
||||
#define CFG_CPUSPEED 0x141
|
||||
|
||||
/* valid baudrates */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
@ -159,27 +160,35 @@
|
|||
* Physical Memory Map
|
||||
*/
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
|
||||
#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
|
||||
#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */
|
||||
#define CFG_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */
|
||||
#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */
|
||||
#define CFG_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */
|
||||
#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
|
||||
#define CONFIG_SYNCFLASH 1
|
||||
#define PHYS_FLASH_SIZE 0x01000000
|
||||
#define CFG_MAX_FLASH_SECT (16)
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x00ff0000)
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x00ff8000)
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 0x0f000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_SECT_SIZE 0x100000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Enable passing ATAGS
|
||||
*/
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 16780000
|
||||
#define CONFIG_SYSPLL_CLK_FREQ 16000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
291
include/configs/mx1fs2.h
Normal file
291
include/configs/mx1fs2.h
Normal file
|
@ -0,0 +1,291 @@
|
|||
/*
|
||||
* Copyright (C) 2004 Sascha Hauer, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
|
||||
#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
|
||||
#define CONFIG_MX1FS2 1 /* on a mx1fs2 board */
|
||||
#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
|
||||
|
||||
/*
|
||||
* Select serial console configuration
|
||||
*/
|
||||
#undef _CONFIG_UART1 /* internal uart 1 */
|
||||
#define _CONFIG_UART2 /* internal uart 2 */
|
||||
#undef _CONFIG_UART3 /* internal uart 3 */
|
||||
#undef _CONFIG_UART4 /* internal uart 4 */
|
||||
#undef CONFIG_SILENT_CONSOLE /* use this to disable output */
|
||||
|
||||
/*
|
||||
* Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
|
||||
* neccessary in include/cmd_confdefs.h file. (Un)comment for getting
|
||||
* functionality or size of u-boot code.
|
||||
*/
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
|
||||
& ~CFG_CMD_LOADS \
|
||||
& ~CFG_CMD_CONSOLE \
|
||||
& ~CFG_CMD_AUTOSCRIPT \
|
||||
& ~CFG_CMD_NET \
|
||||
& ~CFG_CMD_PING \
|
||||
& ~CFG_CMD_DHCP \
|
||||
| CFG_CMD_JFFS2 \
|
||||
)
|
||||
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Boot options. Setting delay to -1 stops autostart count down.
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 10
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock4 console=ttySMX0,115200n8 rootfstype=jffs2"
|
||||
#define CONFIG_BOOTCOMMAND "bootm 10080000"
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
/*
|
||||
* General options for u-boot. Modify to save memory foot print
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef saves memory */
|
||||
#define CFG_PROMPT "mx1fs2> " /* prompt string */
|
||||
#define CFG_CBSIZE 256 /* console I/O buffer */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */
|
||||
#define CFG_MAXARGS 16 /* max command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x08100000 /* memtest test area */
|
||||
#define CFG_MEMTEST_END 0x08F00000
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */
|
||||
|
||||
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
|
||||
#define CFG_CPUSPEED 0x141 /* core clock - register value */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
/*
|
||||
* Definitions related to passing arguments to kernel.
|
||||
*/
|
||||
#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
|
||||
#define CONFIG_INITRD_TAG 1 /* send initrd params */
|
||||
#undef CONFIG_VFD /* do not send framebuffer setup */
|
||||
|
||||
#define CFG_JFFS_CUSTOM_PART
|
||||
/*
|
||||
* Malloc pool need to host env + 128 Kb reserve for other allocations.
|
||||
*/
|
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) )
|
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
#define CONFIG_STACKSIZE (120<<10) /* stack size */
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/* SDRAM Setup Values
|
||||
* 0x910a8300 Precharge Command CAS 3
|
||||
* 0x910a8200 Precharge Command CAS 2
|
||||
*
|
||||
* 0xa10a8300 AutoRefresh Command CAS 3
|
||||
* 0xa10a8200 Set AutoRefresh Command CAS 2
|
||||
*/
|
||||
#define PRECHARGE_CMD 0x910a8300
|
||||
#define AUTOREFRESH_CMD 0xa10a8300
|
||||
|
||||
#define CONFIG_INIT_CRITICAL
|
||||
|
||||
#define BUS32BIT_VERSION
|
||||
/*
|
||||
* SDRAM Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
|
||||
#define MX1FS2_SDRAM_1 0x08000000 /* SDRAM bank #1 */
|
||||
#ifdef BUS32BIT_VERSION
|
||||
#define MX1FS2_SDRAM_1_SIZE (0x04000000 - 0x100000) /* 64 MB - 1M Framebuffer */
|
||||
#else
|
||||
#define MX1FS2_SDRAM_1_SIZE (0x01FC0000 - 0x100000) /* 32 MB - 1M Framebuffer */
|
||||
#endif
|
||||
/*
|
||||
* Flash Controller settings
|
||||
*/
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
|
||||
#define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
|
||||
|
||||
#ifdef BUS32BIT_VERSION
|
||||
#define MX1FS2_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */
|
||||
#define MX1FS2_FLASH_INTERLEAVE 2 /* ... made of 2 chips */
|
||||
#define MX1FS2_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank*/
|
||||
#define MX1FS2_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
|
||||
#define MX1FS2_JFFS2_PART0_START 0x10200000
|
||||
#define MX1FS2_JFFS2_PART0_SIZE 0x00500000
|
||||
#define MX1FS2_JFFS2_PART1_START 0x10700000
|
||||
#define MX1FS2_JFFS2_PART1_SIZE 0x00900000
|
||||
#else
|
||||
#define MX1FS2_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
|
||||
#define MX1FS2_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
|
||||
#define MX1FS2_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank*/
|
||||
#define MX1FS2_FLASH_SECT_SIZE 0x00010000 /* size of erase sector */
|
||||
#endif
|
||||
#define MX1FS2_FLASH_BASE 0x10000000 /* location of flash memory */
|
||||
#define MX1FS2_FLASH_UNLOCK 1 /* perform hw unlock first */
|
||||
|
||||
/* This should be defined if CFI FLASH device is present. Actually benefit
|
||||
is not so clear to me. In other words we can provide more informations
|
||||
to user, but this expects more complex flash handling we do not provide
|
||||
now.*/
|
||||
#undef CFG_FLASH_CFI
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */
|
||||
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */
|
||||
|
||||
#define CFG_FLASH_BASE MX1FS2_FLASH_BASE
|
||||
|
||||
/*
|
||||
* This is setting for JFFS2 support in u-boot.
|
||||
* Right now there is no gain for user, but later on booting kernel might be
|
||||
* possible. Consider using XIP kernel running from flash to save RAM
|
||||
* footprint.
|
||||
* NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
|
||||
*/
|
||||
#define CFG_JFFS2_FIRST_BANK 0
|
||||
#define CFG_JFFS2_FIRST_SECTOR 5
|
||||
#define CFG_JFFS2_NUM_BANKS 1
|
||||
|
||||
/*
|
||||
* Environment setup. Definitions of monitor location and size with
|
||||
* definition of environment setup ends up in 2 possibilities.
|
||||
* 1. Embeded environment - in u-boot code is space for environment
|
||||
* 2. Environment is read from predefined sector of flash
|
||||
* Right now we support 2. possiblity, but expecting no env placed
|
||||
* on mentioned address right now. This also needs to provide whole
|
||||
* sector for it - for us 256Kb is really waste of memory. U-boot uses
|
||||
* default env. and until kernel parameters could be sent to kernel
|
||||
* env. has no sense to us.
|
||||
*/
|
||||
|
||||
#define CFG_MONITOR_BASE 0x10000000
|
||||
#define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR 0x10020000 /* absolute address for now */
|
||||
#define CFG_ENV_SIZE 0x20000
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
|
||||
|
||||
/* Setup CS4 and CS5 */
|
||||
#define CFG_GIUS_A_VAL 0x0003fffe
|
||||
|
||||
/*
|
||||
* CSxU_VAL:
|
||||
* 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32
|
||||
* |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC |
|
||||
*
|
||||
* CSxL_VAL:
|
||||
* 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0
|
||||
* | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN|
|
||||
*/
|
||||
|
||||
#define CFG_CS0U_VAL 0x00008C00
|
||||
#define CFG_CS0L_VAL 0x22222601
|
||||
#define CFG_CS1U_VAL 0x00008C00
|
||||
#define CFG_CS1L_VAL 0x22222301
|
||||
#define CFG_CS4U_VAL 0x00008C00
|
||||
#define CFG_CS4L_VAL 0x22222301
|
||||
#define CFG_CS5U_VAL 0x00008C00
|
||||
#define CFG_CS5L_VAL 0x22222301
|
||||
|
||||
/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
|
||||
f_ref=16,777MHz
|
||||
|
||||
0x002a141f: 191,9944MHz
|
||||
0x040b2007: 144MHz
|
||||
0x042a141f: 96MHz
|
||||
0x0811140d: 64MHz
|
||||
0x040e200e: 150MHz
|
||||
0x00321431: 200MHz
|
||||
|
||||
0x08001800: 64MHz mit 16er Quarz
|
||||
0x04001800: 96MHz mit 16er Quarz
|
||||
0x04002400: 144MHz mit 16er Quarz
|
||||
|
||||
31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
|
||||
|XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
|
||||
|
||||
#define CFG_MPCTL0_VAL 0x07E723AD
|
||||
#define CFG_MPCTL1_VAL 0x00000040
|
||||
#define CFG_PCDR_VAL 0x00010005
|
||||
#define CFG_GPCR_VAL 0x00000FFB
|
||||
|
||||
#define USE_16M_OSZI /* If you have one, you want to use it
|
||||
The internal 32kHz oszillator jitters */
|
||||
#ifdef USE_16M_OSZI
|
||||
|
||||
#define CFG_SPCTL0_VAL 0x04001401
|
||||
#define CFG_SPCTL1_VAL 0x0C000040
|
||||
#define CFG_CSCR_VAL 0x07030003
|
||||
#define CONFIG_SYS_CLK_FREQ 16780000
|
||||
#define CONFIG_SYSPLL_CLK_FREQ 16000000
|
||||
|
||||
#else
|
||||
|
||||
#define CFG_SPCTL0_VAL 0x07E716D1
|
||||
#define CFG_CSCR_VAL 0x06000003
|
||||
#define CONFIG_SYS_CLK_FREQ 16780000
|
||||
#define CONFIG_SYSPLL_CLK_FREQ 16780000
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Well this has to be defined, but on the other hand it is used differently
|
||||
* one may expect. For instance loadb command do not cares :-)
|
||||
* So advice is - do not relay on this...
|
||||
*/
|
||||
#define CFG_LOAD_ADDR 0x08400000
|
||||
|
||||
#define CFG_FMCR_VAL 0x00000003 /* Reset Default */
|
||||
|
||||
/* Bit[0:3] contain PERCLK1DIV for UART 1
|
||||
0x000b00b ->b<- -> 192MHz/12=16MHz
|
||||
0x000b00b ->8<- -> 144MHz/09=16MHz
|
||||
0x000b00b ->3<- -> 64MHz/4=16MHz */
|
||||
|
||||
#ifdef _CONFIG_UART1
|
||||
#define CONFIG_IMX_SERIAL1
|
||||
#elif defined _CONFIG_UART2
|
||||
#define CONFIG_IMX_SERIAL2
|
||||
#elif defined _CONFIG_UART3 | defined _CONFIG_UART4
|
||||
#define CONFIG_IMX_SERIAL_NONE
|
||||
#define CFG_NS16550
|
||||
#define CFG_NS16550_SERIAL
|
||||
#define CFG_NS16550_CLK 3686400
|
||||
#define CFG_NS16550_REG_SIZE 1
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#ifdef _CONFIG_UART3
|
||||
#define CFG_NS16550_COM1 0x15000000
|
||||
#elif defined _CONFIG_UART4
|
||||
#define CFG_NS16550_COM1 0x16000000
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
357
include/configs/scb9328.h
Normal file
357
include/configs/scb9328.h
Normal file
|
@ -0,0 +1,357 @@
|
|||
/*
|
||||
* Copyright (C) 2003 ETC s.r.o.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* Written by Peter Figuli <peposh@etc.sk>, 2003.
|
||||
*
|
||||
* 2003/13/06 Initial MP10 Support copied from wepep250
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
|
||||
#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
|
||||
#define CONFIG_SCB9328 1 /* on a scb9328tronix board */
|
||||
#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
|
||||
|
||||
#define CONFIG_IMX_SERIAL1
|
||||
/*
|
||||
* Select serial console configuration
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
|
||||
* neccessary in include/cmd_confdefs.h file. (Un)comment for getting
|
||||
* functionality or size of u-boot code.
|
||||
*/
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
|
||||
& ~CFG_CMD_LOADS \
|
||||
& ~CFG_CMD_CONSOLE \
|
||||
& ~CFG_CMD_AUTOSCRIPT \
|
||||
| CFG_CMD_NET \
|
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_DHCP \
|
||||
)
|
||||
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Boot options. Setting delay to -1 stops autostart count down.
|
||||
* NOTE: Sending parameters to kernel depends on kernel version and
|
||||
* 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
|
||||
* parameters at all! Do not get confused by them so.
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY -1
|
||||
#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
|
||||
#define CONFIG_BOOTCOMMAND "bootm 10040000"
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS
|
||||
#define CONFIG_ETHADDR 80:81:82:83:84:85
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_IPADDR 10.10.10.9
|
||||
#define CONFIG_SERVERIP 10.10.10.10
|
||||
|
||||
/*
|
||||
* General options for u-boot. Modify to save memory foot print
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef saves memory */
|
||||
#define CFG_PROMPT "scb9328> " /* prompt string */
|
||||
#define CFG_CBSIZE 256 /* console I/O buffer */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */
|
||||
#define CFG_MAXARGS 16 /* max command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x08100000 /* memtest test area */
|
||||
#define CFG_MEMTEST_END 0x08F00000
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */
|
||||
|
||||
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
|
||||
#define CFG_CPUSPEED 0x141 /* core clock - register value */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
/*
|
||||
* Definitions related to passing arguments to kernel.
|
||||
*/
|
||||
#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
|
||||
#define CONFIG_INITRD_TAG 1 /* send initrd params */
|
||||
#undef CONFIG_VFD /* do not send framebuffer setup */
|
||||
|
||||
|
||||
/*
|
||||
* Malloc pool need to host env + 128 Kb reserve for other allocations.
|
||||
*/
|
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) )
|
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
#define CONFIG_STACKSIZE (120<<10) /* stack size */
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/* SDRAM Setup Values
|
||||
0x910a8300 Precharge Command CAS 3
|
||||
0x910a8200 Precharge Command CAS 2
|
||||
|
||||
0xa10a8300 AutoRefresh Command CAS 3
|
||||
0xa10a8200 Set AutoRefresh Command CAS 2 */
|
||||
|
||||
#define PRECHARGE_CMD 0x910a8200
|
||||
#define AUTOREFRESH_CMD 0xa10a8200
|
||||
#define CONFIG_INIT_CRITICAL
|
||||
|
||||
/*
|
||||
* SDRAM Memory Map
|
||||
*/
|
||||
/* SH FIXME */
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
|
||||
#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */
|
||||
#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */
|
||||
|
||||
/*
|
||||
* Flash Controller settings
|
||||
*/
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Configuration for FLASH memory for the Synertronixx board
|
||||
*/
|
||||
|
||||
/* #define SCB9328_FLASH_32M */
|
||||
|
||||
/* 32MB */
|
||||
#ifdef SCB9328_FLASH_32M
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
|
||||
#define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
|
||||
#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
|
||||
#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
|
||||
#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */
|
||||
#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
|
||||
#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
|
||||
#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
|
||||
#else
|
||||
|
||||
/* 16MB */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
|
||||
#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
|
||||
#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
|
||||
#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
|
||||
#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */
|
||||
#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
|
||||
#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
|
||||
#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
|
||||
#endif /* SCB9328_FLASH_32M */
|
||||
|
||||
/* This should be defined if CFI FLASH device is present. Actually benefit
|
||||
is not so clear to me. In other words we can provide more informations
|
||||
to user, but this expects more complex flash handling we do not provide
|
||||
now.*/
|
||||
#undef CFG_FLASH_CFI
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */
|
||||
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */
|
||||
|
||||
#define CFG_FLASH_BASE SCB9328_FLASH_BASE
|
||||
|
||||
/*
|
||||
* This is setting for JFFS2 support in u-boot.
|
||||
* Right now there is no gain for user, but later on booting kernel might be
|
||||
* possible. Consider using XIP kernel running from flash to save RAM
|
||||
* footprint.
|
||||
* NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
|
||||
*/
|
||||
#define CFG_JFFS2_FIRST_BANK 0
|
||||
#define CFG_JFFS2_FIRST_SECTOR 5
|
||||
#define CFG_JFFS2_NUM_BANKS 1
|
||||
|
||||
/*
|
||||
* Environment setup. Definitions of monitor location and size with
|
||||
* definition of environment setup ends up in 2 possibilities.
|
||||
* 1. Embeded environment - in u-boot code is space for environment
|
||||
* 2. Environment is read from predefined sector of flash
|
||||
* Right now we support 2. possiblity, but expecting no env placed
|
||||
* on mentioned address right now. This also needs to provide whole
|
||||
* sector for it - for us 256Kb is really waste of memory. U-boot uses
|
||||
* default env. and until kernel parameters could be sent to kernel
|
||||
* env. has no sense to us.
|
||||
*/
|
||||
|
||||
/* Setup for PA23 which is Reset Default PA23 but has to become
|
||||
CS5 */
|
||||
|
||||
#define CFG_GPR_A_VAL 0x00800000
|
||||
#define CFG_GIUS_A_VAL 0x0043fffe
|
||||
|
||||
#define CFG_MONITOR_BASE 0x10000000
|
||||
#define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR 0x10020000 /* absolute address for now */
|
||||
#define CFG_ENV_SIZE 0x20000
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
|
||||
|
||||
/*
|
||||
* CSxU_VAL:
|
||||
* 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32
|
||||
* |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC |
|
||||
*
|
||||
* CSxL_VAL:
|
||||
* 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0
|
||||
* | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN|
|
||||
*/
|
||||
|
||||
#define CFG_CS0U_VAL 0x000F2000
|
||||
#define CFG_CS0L_VAL 0x11110d01
|
||||
#define CFG_CS1U_VAL 0x000F0a00
|
||||
#define CFG_CS1L_VAL 0x11110601
|
||||
#define CFG_CS2U_VAL 0x0
|
||||
#define CFG_CS2L_VAL 0x0
|
||||
|
||||
#define CFG_CS3U_VAL 0x000FFFFF
|
||||
#define CFG_CS3L_VAL 0x00000303
|
||||
|
||||
#define CFG_CS4U_VAL 0x000F0a00
|
||||
#define CFG_CS4L_VAL 0x11110301
|
||||
|
||||
/* CNC == 3 too long
|
||||
#define CFG_CS5U_VAL 0x0000C210 */
|
||||
|
||||
/* #define CFG_CS5U_VAL 0x00008400
|
||||
mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
|
||||
kaum langsamer ist */
|
||||
/* #define CFG_CS5U_VAL 0x00009400
|
||||
#define CFG_CS5L_VAL 0x11010D03 */
|
||||
|
||||
#define CFG_CS5U_VAL 0x00008400
|
||||
#define CFG_CS5L_VAL 0x00000D03
|
||||
|
||||
#define CONFIG_DRIVER_DM9000 1
|
||||
#define CONFIG_DRIVER_DM9000 1
|
||||
#define CONFIG_DM9000_BASE 0x16000000
|
||||
#define DM9000_IO CONFIG_DM9000_BASE
|
||||
#define DM9000_DATA (CONFIG_DM9000_BASE+4)
|
||||
/* #define CONFIG_DM9000_USE_8BIT */
|
||||
#define CONFIG_DM9000_USE_16BIT
|
||||
/* #define CONFIG_DM9000_USE_32BIT */
|
||||
|
||||
/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
|
||||
f_ref=16,777MHz
|
||||
|
||||
0x002a141f: 191,9944MHz
|
||||
0x040b2007: 144MHz
|
||||
0x042a141f: 96MHz
|
||||
0x0811140d: 64MHz
|
||||
0x040e200e: 150MHz
|
||||
0x00321431: 200MHz
|
||||
|
||||
0x08001800: 64MHz mit 16er Quarz
|
||||
0x04001800: 96MHz mit 16er Quarz
|
||||
0x04002400: 144MHz mit 16er Quarz
|
||||
|
||||
31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
|
||||
|XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
|
||||
|
||||
#define CPU200
|
||||
|
||||
#ifdef CPU200
|
||||
#define CFG_MPCTL0_VAL 0x00321431
|
||||
#else
|
||||
#define CFG_MPCTL0_VAL 0x040e200e
|
||||
#endif
|
||||
|
||||
/* #define BUS64 */
|
||||
#define BUS72
|
||||
|
||||
#ifdef BUS72
|
||||
#define CFG_SPCTL0_VAL 0x04002400
|
||||
#endif
|
||||
|
||||
#ifdef BUS96
|
||||
#define CFG_SPCTL0_VAL 0x04001800
|
||||
#endif
|
||||
|
||||
#ifdef BUS64
|
||||
#define CFG_SPCTL0_VAL 0x08001800
|
||||
#endif
|
||||
|
||||
/* Das ist der BCLK Divider, der aus der System PLL
|
||||
BCLK und HCLK erzeugt:
|
||||
31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
|
||||
0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
|
||||
0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
|
||||
0x2f001003 : 192MHz/5=38,4MHz
|
||||
0x2f000003 : 64MHz/1
|
||||
Bit 22: SPLL Restart
|
||||
Bit 21: MPLL Restart */
|
||||
|
||||
#ifdef BUS64
|
||||
#define CFG_CSCR_VAL 0x2f030003
|
||||
#endif
|
||||
|
||||
#ifdef BUS72
|
||||
#define CFG_CSCR_VAL 0x2f030403
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Well this has to be defined, but on the other hand it is used differently
|
||||
* one may expect. For instance loadb command do not cares :-)
|
||||
* So advice is - do not relay on this...
|
||||
*/
|
||||
#define CFG_LOAD_ADDR 0x08400000
|
||||
|
||||
#define MHZ16QUARZINUSE
|
||||
|
||||
#ifdef MHZ16QUARZINUSE
|
||||
#define CONFIG_SYSPLL_CLK_FREQ 16000000
|
||||
#else
|
||||
#define CONFIG_SYSPLL_CLK_FREQ 16780000
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 16780000
|
||||
|
||||
/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
|
||||
#define CFG_FMCR_VAL 0x00000001
|
||||
|
||||
/* Bit[0:3] contain PERCLK1DIV for UART 1
|
||||
0x000b00b ->b<- -> 192MHz/12=16MHz
|
||||
0x000b00b ->8<- -> 144MHz/09=16MHz
|
||||
0x000b00b ->3<- -> 64MHz/4=16MHz */
|
||||
|
||||
#ifdef BUS96
|
||||
#define CFG_PCDR_VAL 0x000b00b5
|
||||
#endif
|
||||
|
||||
#ifdef BUS64
|
||||
#define CFG_PCDR_VAL 0x000b00b3
|
||||
#endif
|
||||
|
||||
#ifdef BUS72
|
||||
#define CFG_PCDR_VAL 0x000b00b8
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
|
@ -39,7 +39,7 @@
|
|||
typedef struct {
|
||||
int flags; /* Device flags: input/output/system */
|
||||
int ext; /* Supported extensions */
|
||||
char name[8]; /* Device name */
|
||||
char name[16]; /* Device name */
|
||||
|
||||
/* GENERAL functions */
|
||||
|
||||
|
|
1051
include/mc9328.h
1051
include/mc9328.h
File diff suppressed because it is too large
Load diff
|
@ -297,6 +297,7 @@
|
|||
#define PBESR 0x800000c7 /* PCI Bus Error Status Register */
|
||||
#define PBEAR 0x800000c8 /* Processor/PCI Bus Error Status Register */
|
||||
#define AMBOR 0x800000e0 /* Address Map B Options Register */
|
||||
#define PCMBCR 0x800000e1 /* PCI/Memory Buffer Configuration */
|
||||
#define MCCR1 0x800000f0 /* Memory Control Configuration Register 1 */
|
||||
#define MCCR2 0x800000f4 /* Memory Control Configuration Register 2 */
|
||||
#define MCCR3 0x800000f8 /* Memory Control Configuration Register 3 */
|
||||
|
|
30
include/serial.h
Normal file
30
include/serial.h
Normal file
|
@ -0,0 +1,30 @@
|
|||
#ifndef __SERIAL_H__
|
||||
#define __SERIAL_H__
|
||||
|
||||
#define NAMESIZE 16
|
||||
#define CTLRSIZE 8
|
||||
|
||||
struct serial_device {
|
||||
char name[NAMESIZE];
|
||||
char ctlr[CTLRSIZE];
|
||||
|
||||
int (*init) (void);
|
||||
void (*setbrg) (void);
|
||||
int (*getc) (void);
|
||||
int (*tstc) (void);
|
||||
void (*putc) (const char c);
|
||||
void (*puts) (const char *s);
|
||||
|
||||
struct serial_device *next;
|
||||
};
|
||||
|
||||
extern struct serial_device serial_smc_device;
|
||||
extern struct serial_device serial_scc_device;
|
||||
extern struct serial_device * default_serial_console (void);
|
||||
|
||||
extern void serial_initialize(void);
|
||||
extern void serial_devices_init(void);
|
||||
extern int serial_assign(char * name);
|
||||
extern void serial_reinit_all(void);
|
||||
|
||||
#endif
|
|
@ -250,6 +250,9 @@ void start_armboot (void)
|
|||
#endif /* CONFIG_VFD */
|
||||
|
||||
#ifdef CONFIG_LCD
|
||||
# ifndef PAGE_SIZE
|
||||
# define PAGE_SIZE 4096
|
||||
# endif
|
||||
/*
|
||||
* reserve memory for LCD display (always full pages)
|
||||
*/
|
||||
|
|
|
@ -48,6 +48,7 @@
|
|||
#include <status_led.h>
|
||||
#endif
|
||||
#include <net.h>
|
||||
#include <serial.h>
|
||||
#ifdef CFG_ALLOC_DPRAM
|
||||
#if !(defined(CONFIG_8260)||defined(CONFIG_MPC8560))
|
||||
#include <commproc.h>
|
||||
|
@ -582,6 +583,10 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||
|
||||
monitor_flash_len = (ulong)&__init_end - dest_addr;
|
||||
|
||||
#ifdef CONFIG_SERIAL_MULTI
|
||||
serial_initialize();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* We have to relocate the command table manually
|
||||
*/
|
||||
|
@ -872,7 +877,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||
defined(CONFIG_IP860) || \
|
||||
defined(CONFIG_IVML24) || \
|
||||
defined(CONFIG_IVMS8) || \
|
||||
defined(CONFIG_LWMON) || \
|
||||
defined(CONFIG_MPC8260ADS) || \
|
||||
defined(CONFIG_MPC8266ADS) || \
|
||||
defined(CONFIG_MPC8560ADS) || \
|
||||
|
|
27
post/ether.c
27
post/ether.c
|
@ -49,6 +49,7 @@
|
|||
|
||||
#include <command.h>
|
||||
#include <net.h>
|
||||
#include <serial.h>
|
||||
|
||||
#define MIN_PACKET_LENGTH 64
|
||||
#define MAX_PACKET_LENGTH 256
|
||||
|
@ -77,8 +78,6 @@ static struct {
|
|||
|
||||
static char *ctlr_name[1] = { "SCC" };
|
||||
|
||||
static int used_by_uart[1] = { -1 };
|
||||
|
||||
/* Ethernet Transmit and Receive Buffers */
|
||||
#define DBUF_LENGTH 1520
|
||||
|
||||
|
@ -458,6 +457,7 @@ static void scc_halt (int scc_index)
|
|||
|
||||
immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
|
||||
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA);
|
||||
}
|
||||
|
||||
static int scc_send (int index, volatile void *packet, int length)
|
||||
|
@ -513,7 +513,7 @@ static int scc_recv (int index, void *packet, int max_length)
|
|||
rxIdx++;
|
||||
}
|
||||
|
||||
Done:
|
||||
Done:
|
||||
return length;
|
||||
}
|
||||
|
||||
|
@ -579,16 +579,10 @@ static int test_ctlr (int ctlr, int index)
|
|||
|
||||
res = 0;
|
||||
|
||||
Done:
|
||||
Done:
|
||||
|
||||
ctlr_proc[ctlr].halt (index);
|
||||
|
||||
#if !defined(CONFIG_8xx_CONS_NONE)
|
||||
if (used_by_uart[ctlr] == index) {
|
||||
serial_init ();
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SCC2 Ethernet parameter RAM space overlaps
|
||||
* the SPI parameter RAM space. So we need to restore
|
||||
|
@ -614,16 +608,6 @@ int ether_post_test (int flags)
|
|||
int res = 0;
|
||||
int i;
|
||||
|
||||
#if defined(CONFIG_8xx_CONS_SCC1)
|
||||
used_by_uart[CTLR_SCC] = 0;
|
||||
#elif defined(CONFIG_8xx_CONS_SCC2)
|
||||
used_by_uart[CTLR_SCC] = 1;
|
||||
#elif defined(CONFIG_8xx_CONS_SCC3)
|
||||
used_by_uart[CTLR_SCC] = 2;
|
||||
#elif defined(CONFIG_8xx_CONS_SCC4)
|
||||
used_by_uart[CTLR_SCC] = 3;
|
||||
#endif
|
||||
|
||||
ctlr_proc[CTLR_SCC].init = scc_init;
|
||||
ctlr_proc[CTLR_SCC].halt = scc_halt;
|
||||
ctlr_proc[CTLR_SCC].send = scc_send;
|
||||
|
@ -635,6 +619,9 @@ int ether_post_test (int flags)
|
|||
}
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_8xx_CONS_NONE)
|
||||
serial_reinit_all ();
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
|
|
53
post/uart.c
53
post/uart.c
|
@ -48,7 +48,7 @@
|
|||
#error "Apparently a bad configuration, please fix."
|
||||
#endif
|
||||
#include <command.h>
|
||||
#include <net.h>
|
||||
#include <serial.h>
|
||||
|
||||
#define CTLR_SMC 0
|
||||
#define CTLR_SCC 1
|
||||
|
@ -65,14 +65,13 @@ static int ctlr_list[][2] = { };
|
|||
|
||||
static struct {
|
||||
void (*init) (int index);
|
||||
void (*halt) (int index);
|
||||
void (*putc) (int index, const char c);
|
||||
int (*getc) (int index);
|
||||
} ctlr_proc[2];
|
||||
|
||||
static char *ctlr_name[2] = { "SMC", "SCC" };
|
||||
|
||||
static int used_by_uart[2] = { -1, -1 };
|
||||
|
||||
static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
|
||||
static int proff_scc[] =
|
||||
{ PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
|
||||
|
@ -212,6 +211,10 @@ static void smc_init (int smc_index)
|
|||
sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
|
||||
}
|
||||
|
||||
static void smc_halt(int smc_index)
|
||||
{
|
||||
}
|
||||
|
||||
static void smc_putc (int smc_index, const char c)
|
||||
{
|
||||
volatile cbd_t *tbdf;
|
||||
|
@ -419,6 +422,15 @@ static void scc_init (int scc_index)
|
|||
sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||||
}
|
||||
|
||||
static void scc_halt(int scc_index)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *) CFG_IMMR;
|
||||
volatile cpm8xx_t *cp = &(im->im_cpm);
|
||||
volatile scc_t *sp = (scc_t *) & (cp->cp_scc[scc_index]);
|
||||
|
||||
sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT | SCC_GSMRL_DIAG_LE);
|
||||
}
|
||||
|
||||
static void scc_putc (int scc_index, const char c)
|
||||
{
|
||||
volatile cbd_t *tbdf;
|
||||
|
@ -496,12 +508,6 @@ static int test_ctlr (int ctlr, int index)
|
|||
char test_str[] = "*** UART Test String ***\r\n";
|
||||
int i;
|
||||
|
||||
#if !defined(CONFIG_8xx_CONS_NONE)
|
||||
if (used_by_uart[ctlr] == index) {
|
||||
while (ctlr_proc[ctlr].getc (index) != -1);
|
||||
}
|
||||
#endif
|
||||
|
||||
ctlr_proc[ctlr].init (index);
|
||||
|
||||
for (i = 0; i < sizeof (test_str) - 1; i++) {
|
||||
|
@ -512,13 +518,8 @@ static int test_ctlr (int ctlr, int index)
|
|||
|
||||
res = 0;
|
||||
|
||||
Done:
|
||||
|
||||
#if !defined(CONFIG_8xx_CONS_NONE)
|
||||
if (used_by_uart[ctlr] == index) {
|
||||
serial_init ();
|
||||
}
|
||||
#endif
|
||||
Done:
|
||||
ctlr_proc[ctlr].halt (index);
|
||||
|
||||
if (res != 0) {
|
||||
post_log ("uart %s%d test failed\n",
|
||||
|
@ -533,25 +534,13 @@ int uart_post_test (int flags)
|
|||
int res = 0;
|
||||
int i;
|
||||
|
||||
#if defined(CONFIG_8xx_CONS_SMC1)
|
||||
used_by_uart[CTLR_SMC] = 0;
|
||||
#elif defined(CONFIG_8xx_CONS_SMC2)
|
||||
used_by_uart[CTLR_SMC] = 1;
|
||||
#elif defined(CONFIG_8xx_CONS_SCC1)
|
||||
used_by_uart[CTLR_SCC] = 0;
|
||||
#elif defined(CONFIG_8xx_CONS_SCC2)
|
||||
used_by_uart[CTLR_SCC] = 1;
|
||||
#elif defined(CONFIG_8xx_CONS_SCC3)
|
||||
used_by_uart[CTLR_SCC] = 2;
|
||||
#elif defined(CONFIG_8xx_CONS_SCC4)
|
||||
used_by_uart[CTLR_SCC] = 3;
|
||||
#endif
|
||||
|
||||
ctlr_proc[CTLR_SMC].init = smc_init;
|
||||
ctlr_proc[CTLR_SMC].halt = smc_halt;
|
||||
ctlr_proc[CTLR_SMC].putc = smc_putc;
|
||||
ctlr_proc[CTLR_SMC].getc = smc_getc;
|
||||
|
||||
ctlr_proc[CTLR_SCC].init = scc_init;
|
||||
ctlr_proc[CTLR_SCC].halt = scc_halt;
|
||||
ctlr_proc[CTLR_SCC].putc = scc_putc;
|
||||
ctlr_proc[CTLR_SCC].getc = scc_getc;
|
||||
|
||||
|
@ -561,6 +550,10 @@ int uart_post_test (int flags)
|
|||
}
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_8xx_CONS_NONE)
|
||||
serial_reinit_all ();
|
||||
#endif
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in a new issue