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85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docs
All the 85xx and 86xx UM describe the register as timing_cfg_3 not as ext_refrec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
parent
ef7d30b143
commit
45239cf415
10 changed files with 13 additions and 13 deletions
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@ -192,7 +192,7 @@ long int fixed_sdram(void)
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ddr->cs0_bnds = 0x0000001f;
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ddr->cs0_config = 0x80010202;
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ddr->ext_refrec = 0x00000000;
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ddr->timing_cfg_3 = 0x00000000;
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ddr->timing_cfg_0 = 0x00260802;
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ddr->timing_cfg_1 = 0x3935d322;
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ddr->timing_cfg_2 = 0x14904cc8;
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@ -130,7 +130,7 @@ fixed_sdram(void)
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ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
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ddr->cs0_config = CFG_DDR_CS0_CONFIG;
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ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
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ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
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ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
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ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
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ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
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@ -299,7 +299,7 @@ long int fixed_sdram (void)
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ddr->cs1_config = 0x80010101;
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ddr->cs2_config = 0x00000000;
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ddr->cs3_config = 0x00000000;
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ddr->ext_refrec = 0x00000000;
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ddr->timing_cfg_3 = 0x00000000;
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ddr->timing_cfg_0 = 0x00220802;
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ddr->timing_cfg_1 = 0x38377322;
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ddr->timing_cfg_2 = 0x0fa044C7;
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@ -135,7 +135,7 @@ long int fixed_sdram (void)
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ddr->cs1_config = CFG_DDR_CS1_CONFIG;
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ddr->cs2_config = CFG_DDR_CS2_CONFIG;
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ddr->cs3_config = CFG_DDR_CS3_CONFIG;
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ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
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ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
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ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
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ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
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ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
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@ -166,7 +166,7 @@ long int fixed_sdram (void)
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ddr->cs1_config = CFG_DDR2_CS1_CONFIG;
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ddr->cs2_config = CFG_DDR2_CS2_CONFIG;
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ddr->cs3_config = CFG_DDR2_CS3_CONFIG;
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ddr->ext_refrec = CFG_DDR2_EXT_REFRESH;
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ddr->timing_cfg_3 = CFG_DDR2_EXT_REFRESH;
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ddr->timing_cfg_0 = CFG_DDR2_TIMING_0;
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ddr->timing_cfg_1 = CFG_DDR2_TIMING_1;
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ddr->timing_cfg_2 = CFG_DDR2_TIMING_2;
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@ -610,8 +610,8 @@ spd_sdram(void)
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/*
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* Sneak in some Extended Refresh Recovery.
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*/
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ddr->ext_refrec = (trfc_high << 16);
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debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
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ddr->timing_cfg_3 = (trfc_high << 16);
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debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
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ddr->timing_cfg_1 =
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(0
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@ -644,8 +644,8 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
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/*
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* Sneak in some Extended Refresh Recovery.
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*/
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ddr->ext_refrec = (trfc_high << 16);
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debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
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ddr->timing_cfg_3 = (trfc_high << 16);
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debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
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ddr->timing_cfg_1 =
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(0
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@ -92,7 +92,7 @@ typedef struct ccsr_ddr {
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uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */
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uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */
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char res5[48];
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uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */
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uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
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uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
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uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
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uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
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@ -109,7 +109,7 @@ typedef struct ccsr_ddr {
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uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */
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uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */
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char res7[104];
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uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */
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uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
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uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
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uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
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uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
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@ -114,7 +114,7 @@
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#if 0 /* TODO */
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#define CFG_DDR_CS0_BNDS 0x0000000F
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#define CFG_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
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#define CFG_DDR_EXT_REFRESH 0x00000000
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#define CFG_DDR_TIMING_3 0x00000000
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#define CFG_DDR_TIMING_0 0x00260802
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#define CFG_DDR_TIMING_1 0x3935d322
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#define CFG_DDR_TIMING_2 0x14904cc8
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@ -136,7 +136,7 @@
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#define CFG_DDR_CS1_CONFIG 0x00000000
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#define CFG_DDR_CS2_CONFIG 0x00000000
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#define CFG_DDR_CS3_CONFIG 0x00000000
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#define CFG_DDR_EXT_REFRESH 0x00000000
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#define CFG_DDR_TIMING_3 0x00000000
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#define CFG_DDR_TIMING_0 0x00220802
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#define CFG_DDR_TIMING_1 0x38377322
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#define CFG_DDR_TIMING_2 0x002040c7
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