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Tweak DDR ECC error counter
Enable single-bit error counter when memory was cleared by ddr controller. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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1 changed files with 5 additions and 2 deletions
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@ -786,14 +786,17 @@ spd_sdram(void)
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* Is this an ECC DDR chip?
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* But don't mess with it if the DDR controller will init mem.
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*/
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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#ifdef CONFIG_DDR_ECC
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if (spd.config == 0x02) {
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#ifndef CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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ddr->err_disable = 0x0000000d;
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#endif
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ddr->err_sbe = 0x00ff0000;
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}
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debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
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debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
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#endif
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#endif /* CONFIG_DDR_ECC */
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asm("sync;isync;msync");
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udelay(500);
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