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Tweak DDR ECC error counter

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Enable single-bit error counter when memory was cleared by ddr controller.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Andy Fleming 2007-02-24 01:16:45 -06:00 • committed by Andrew Fleming-AFLEMING
parent 85e7c7a45e
commit 9343dbf85b
1 changed files with 5 additions and 2 deletions
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7
cpu/mpc85xx/spd_sdram.c
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@ -786,14 +786,17 @@ spd_sdram(void)
* Is this an ECC DDR chip?
* But don't mess with it if the DDR controller will init mem.
*/
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
#ifdef CONFIG_DDR_ECC
if (spd.config == 0x02) {
#ifndef CONFIG_ECC_INIT_VIA_DDRCONTROLLER
ddr->err_disable = 0x0000000d;
#endif
ddr->err_sbe = 0x00ff0000;
}
debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
#endif
#endif /* CONFIG_DDR_ECC */
asm("sync;isync;msync");
udelay(500);