Commit graph

982 commits

Author SHA1 Message Date
Peter Korsgaard
c00f69dbcd am33xx: support board specific ddr settings
Move the hardcoded ddr2/ddr3 settings for the ti boards to board code,
so other boards can use different types/timings.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[trini: Make apply with rtc32k_enable() in the file]
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25 11:31:38 -07:00
Peter Korsgaard
7f26a5a26f am33xx: move generic parts of pinmux handling out from board/ti/am335x
So they are available for other boards.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
2012-10-25 11:31:37 -07:00
Peter Korsgaard
e363426e99 am33xx: move ti i2c baseboard header handling to board/ti/am335x/
The i2c header is specific to ti(-derived) boards, and not generic for all
am335x boards.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[trini: Make re-apply with rtc32k_enable() applied]
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25 11:31:36 -07:00
Tom Rini
69916bcf71 am33xx: Add SPI SPL as an option
Add the required config.mk logic for this SoC as well as the BOOT_DEVICE
define.  Finally, enable the options on the am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25 11:30:50 -07:00
Stefano Babic
60c41d907e VIDEO: add macro to set LCD size for DSS driver
Signed-off-by: Stefano Babic <sbabic@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2012-10-25 11:30:49 -07:00
Vaibhav Hiremath
000820b583 am335x: Enable RTC 32K OSC clock
In order to support low power state, you must source kernel system
timers to persistent clock, available across suspend/resume.  In case of
AM335x device, the only source we have is, RTC32K, available in
wakeup/always-on domain.  Having said that, during validation it has
been observed that, RTC clock need couple of seconds delay to stabilize
the RTC OSC clock; and such a huge delay is not acceptable in kernel
especially during early init and also it will impact quick/fast boot
use-cases.

So, RTC32k OSC enable dependency has been shifted to
SPL/first-bootloader.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25 11:30:22 -07:00
Simon Glass
e46e31a83a arm: Change global data baudrate to int
This does not need to be a long, so change it.

Also adjust bi_baudrate to be unsigned.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:45 -07:00
Fabio Estevam
782b028841 mx5: lowlevel_init.S: Fix PLL settings for mx53
Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz.

Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz
instead.

Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI
at 1080p because the IPU clock cannot reach the requested frequency.

Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its
maximum frequency.

Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little
bit to allow easier comparison with the original clock setup from FSL U-boot.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-17 18:09:34 +02:00
Benoît Thébaudeau
5676f598e7 mx25: Clean up imx-regs.h
Clean up i.MX25 imx-regs.h:
 - Update mx31 imx-regs.h filename.
 - Test for __KERNEL_STRICT_NAMES just in case.
 - Define internal RAM size.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-16 12:35:12 +02:00
Eric Nelson
f95c960bcc i.MX6: add HDMI transmitter register declarations from kernel WIP.
Original source from Pengutronix HDMI driver work:

	http://git.pengutronix.de/?p=imx/linux-2.6.git;a=commitdiff;h=72c31cd67ac880bd90785af86f8e46f8ea7b3bb0

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-16 12:35:11 +02:00
Eric Nelson
0fb1e57cb6 i.MX6: set drive strength for parallel RGB pads
Default drive strength is disabled and won't function.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-16 12:35:11 +02:00
Eric Nelson
5ae28d2db2 i.MX: iomux: input pad array can be const
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-10-16 12:35:11 +02:00
Fabio Estevam
dce67bd548 mx6qsabreauto: Pass the board revision to the kernel
The kernel from Freescale expects that the bootloader passes the board revision.

Read the board revision and pass it via get_board_rev().

Without passing the board revision the kernel does not operate properly as the
initialization of peripherals are different in revA versus revB boards.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-16 12:35:11 +02:00
Benoît Thébaudeau
6e3dc12754 mx35: Fix eSDHC clocks
Each eSDHC instance has a dedicated clock.

gd->sdhc_clk must also be set accordingly. This is good for the case only a
single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A
future patch will fix the multi-instance use case (initialization made directly
with fsl_esdhc_initialize()).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
2012-10-16 12:35:10 +02:00
Benoît Thébaudeau
151d63cb91 mx35: Clean up lowlevel_init
Clean up mx35 lowlevel_init:
 - Indent with tabs.
 - Fix comments.
 - Use defined values instead of literal constants.
 - Use defined macros instead of duplicating code.
 - Use macro parameters with default values instead of #define'd configs.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-16 12:35:10 +02:00
Benoît Thébaudeau
85d993cef9 mx25: Clean up lowlevel_init
Clean up mx25 lowlevel_init:
 - Add comments.
 - Do not use write32 repeatedly with the same value in order not to increase
   code size.
 - Make register values configurable.
 - Use macro parameters with default values instead of literal constants.
 - Use defined macros instead of duplicating code.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: John Rigby <jcrigby@gmail.com>
Cc: Matthias Weisser <weisserm@arcor.de>
2012-10-15 11:54:14 -07:00
Benoît Thébaudeau
9e0081d573 mx31: Fix PDR0_CSI_PODF
The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0
register is actually composed of two bit-fields: one pre-divider and one
post-divider. This patch fixes the CCM access macros and the code using them
accordingly.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:14 -07:00
Benoît Thébaudeau
b809b3ac13 mx35: Define MAX and AIPS registers
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:14 -07:00
Benoît Thébaudeau
df7e420bbd mx31: Add more CCM access macros
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:13 -07:00
Benoît Thébaudeau
9baefa465d mx25: Clean up clocks API
Use the standard mxc_get_clock() instead of exporting internal functions and
using literal constant values.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:13 -07:00
Benoît Thébaudeau
17c7cf71b4 mx25 clocks: Fix MXC_FEC_CLK
mxc_get_clock(MXC_FEC_CLK) should return the IPG clock, not the AHB clock.

Also, imx_get_fecclk() was correct but reimplemented the calculation of the IPG
clock, so remove the duplicated code.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:13 -07:00
Benoît Thébaudeau
c3b5189031 mx25: Define more standard clocks
Define AHB, IPG and CSPI clocks.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:12 -07:00
Benoît Thébaudeau
323846561a mx5/6 clocks: Fix SDHC clocks
The i.MX5 eSDHC clocks were considered as coming from the IPG clock although
they have dedicated clock paths.

Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must
be set accordingly. This is good for the case only a single SDHC instance is
used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix
the multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
2012-10-15 11:54:12 -07:00
Benoît Thébaudeau
b94792982f mx5 clocks: Fix get_lp_apm()
If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024.
In that case:
 - on i.MX51, this clock comes from the output of the FPM,
 - on i.MX53, this clock comes from the output of PLL4.

This patch fixes the code accordingly.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:11 -07:00
Benoît Thébaudeau
649dc8abd9 mx5 clocks: Add and use CCSR definitions
This fixes config_pll_clk(), which used 0x20 instead of 0x200 for PLL4_CLOCK.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:11 -07:00
Benoît Thébaudeau
414e1660c8 mx51: Fix USB PHY clocks
The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
have different clock gate control bit-fields.

The existing code was correct only for i.MX53, so this patch fixes the i.MX51
use case.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Jana Rapava <fermata7@gmail.com>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
2012-10-15 11:54:11 -07:00
Benoît Thébaudeau
248cdf0b52 mx5: Fix clock gate values
The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one
of these bits like what was done is wrong and can lead to unpredictable behavior
depending on the original value of these bit-fields.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:10 -07:00
Benoît Thébaudeau
1f5e4ee0b9 mx5: Use explicit clock gate names
Use clock gate definitions having names showing clearly the gated clock instead
of names giving only a register field index.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:10 -07:00
Benoît Thébaudeau
846b38981f mx5 clocks: Cleanup
Clean up the i.MX5 clock driver:
 - Use readl() and writel() instead of their __raw_ counterparts.
 - Use the clr/setbits_le32() family of macros rather than expanding code.
 - Use accessor macros for bit-fields instead of _MASK and _OFFSET.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:10 -07:00
Benoît Thébaudeau
833b6435de mx5/6: Define default SoC input clock frequencies
Define default SoC input clock frequencies for i.MX5/6 in order to get rid of
duplicated definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Liu <r64343@freescale.com>
Cc: Matt Sealey <matt@genesi-usa.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-15 11:54:10 -07:00
Matthias Weisser
e7bed5c2b3 imx: Use MXC_I2C_CLK in imx i2c driver
i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using
MXC_I2C_CLK on all imx systems using i2c.

Signed-off-by: Matthias Weisser <weisserm@arcor.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:10 -07:00
Eric Benard
8a57fdc640 mx25: add CPU revision 1.2
tested on a MCIMX257CJM4A which now reports :
CPU:   Freescale i.MX25 rev1.2 at 399 MHz

Signed-off-by: Eric Bénard <eric@eukrea.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2012-10-15 11:54:10 -07:00
Eric Nelson
2af7e81015 i.MX6: get rid of redundant struct src_regs (dupe of struct src)
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15 11:54:09 -07:00
Eric Nelson
de710a14b5 i.MX6: define struct iomuxc and IOMUX_GPR2 register bitfields
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:09 -07:00
Eric Nelson
e66ad6e747 i.MX6: Add ANATOP_PFD_480 bitfield constants
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:09 -07:00
Eric Nelson
a83e1b7b8c i.MX6: define IOMUX_GPR3 register bitfields
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15 11:54:09 -07:00
Eric Nelson
344da71a20 i.MX6: define bitfields for CHSCCDR register
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15 11:54:09 -07:00
Eric Nelson
da6df2d1c8 i.MX6: change register name for CCM_CHSCCDR to match ref. manual
Register CCM_CHSCCDR (offset 0x34 in CCM) is named CCM_CHSCCDR in
reference manual, but was named chscdr in struct mxc_ccm_reg.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15 11:54:08 -07:00
Eric Nelson
0bb7e316f0 i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fields
Add meaningful constants for each clock channels and use them for
enabling and disabling i.MX6 clocks.

Includes an update to enable/disable the IPU1 clock in
drivers/video/ipu_common to remove IMX5x register access
when used on i.MX6 as discussed in V1:

     http://patchwork.ozlabs.org/patch/185129/

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15 11:54:08 -07:00
Lukasz Dalek
539e9ffd92 pxa: Add code to examine cpu model and revision
Add function which return CPU model and revision which can be used for
cpu detection.

Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
2012-10-15 11:54:07 -07:00
Lucas Stach
c0720afbb5 tegra: nand: add board pinmux
Boards may require a different pinmux setup for NAND than the default one.
Add a way to call into board specific code to set this up.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15 11:54:07 -07:00
Lucas Stach
516f00b324 tegra: clean up board include hell
The prototypes used in board files were all scattered out, which lead to
code duplication between SPL and normal U-Boot and some prototypes not actually
being used. Consolidate this in a common board header.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15 11:54:07 -07:00
Lucas Stach
ac56d959a3 tegra: add funcmux entry for NAND attached to KBC
Secondary config for the Flash attachment.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15 11:54:07 -07:00
Lucas Stach
65530a842e tegra20: add clock_set_pllout function
Common practice on Tegra 2 boards is to use the pllp_out4 FO
to generate the ULPI reference clock. For this to work we have
to override the default hardware generated output divider.

This function adds a clean way to do so.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15 11:54:07 -07:00
Lucas Stach
3f44e44f33 tegra20: complete periph_id enum
Most Tegra boards output the ULPI reference clock on pad DEV2.

Complete the periph_id enum so that we are able to enable this
clock output circuit.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15 11:54:06 -07:00
Tom Warren
150c24936b Tegra20: Move some include files to arch-tegra for sharing with Tegra30
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs
that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20'
'root' file.

All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15 11:54:06 -07:00
Lucas Stach
6d365ea0ac tegra20: add USB ULPI init code
This adds the required code to set up a ULPI USB port. It is
mostly a port of the Linux ULPI setup code with some tweaks
added for more correctness, discovered along the way of
debugging this.

To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT
have to be set in the board configuration file.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2012-10-15 11:54:01 -07:00
Lucas Stach
a896211ff1 tegra20: port to new ehci interface
EHCI interface now supports more than one controller. Wire up our usb functions
to use this new interface.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
2012-10-15 11:54:00 -07:00
Lucas Stach
676ae068d9 usb: ehci: rework to take advantage of new lowlevel interface
Kill off ehci-core.h
It was used to specify some static controller data. To support more than
one controller being active at any time we have to carry the controller
data ourselfes. Change the ehci interface accordingly.

NOTE: OMAP implemented the ehci stuff a bit backwards and should be fixed
to do the same thing as other platforms. But the change for now is at least
compile clean.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2012-10-15 11:54:00 -07:00
Dinh Nguyen
777544085d ARM: Add Altera SOCFPGA Cyclone5
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Chin Liang See <clsee@altera.com>
Signed-off-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Tom Trini <trini@ti.com>
Cc: Wolfgang Denx <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefan Roese <sr@denx.de>
----
v8: Remove no_return attribute for reset_cpu

Based on v2012.10-rc2
2012-10-04 18:11:52 +02:00
Albert ARIBAUD
386c6cb10d Merge remote-tracking branch 'u-boot-marvell/master' 2012-10-03 16:44:29 +02:00
Dinh Nguyen
7029394d82 ARM: kirkwood/orion5x: Use reset_cpu definition in include/common.h
include/common.h has the reset_cpu defined already. No need to
re-define here.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-By: Prafulla Wadaskar <Prafulla@marvell.com>
2012-10-03 16:43:13 +05:30
Gerlando Falauto
b3168f4be8 kirkwood: implement kw_sdram_size_adjust
Size of the SDRAM chips might differ between any two (otherwise
identical) instances of the same board.

So add a function kw_sdram_size_adjust() which reads out the current
ram size for a given bank, and adjusts the Kirkwood's SDRAM window size
register accordingly.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
2012-10-03 16:43:13 +05:30
Luka Perkov
6d4ebd159e kirkwood: fix mpp.h coding style
Signed-off-by: Luka Perkov <uboot@lukaperkov.net>
2012-10-03 16:43:13 +05:30
Gabriel Huau
5d889ae79e ARM : Add GPIO Driver and IOMUX definition for S3C2440
It's now possible to use the gpio driver interface
for s3c2440. This patch add iomux definitions too.

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
2012-10-03 10:50:20 +02:00
Hideyuki Sano
1a31ca4a78 arm: rmobile: Add support for ATMARK-TECHNO Armadillo-800EVA board
The Armadillo-800EVA board has Renesas R-Mobile R8A7740, 512MB DDR3-SDRAM,
Ethernet, and more.

This patch supports the following functions:
 - 512MB DDR3-SDRAM
 - Serial console (SCIF)
 - Ethernet MAC(MII) & PHY(SMSC)

Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:25 +02:00
Nobuhiro Iwamatsu
62d0b6bab1 arm: rmobile: Add support PFC of Renesas R8A7740
Renesas R8A7740 has GPIO based PFC. This privode framework of PFC.
The code included in this base from linux kernel.

Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:25 +02:00
Nobuhiro Iwamatsu
cfa291b7b8 arm: rmobile: Add support Renesas R8A7740
Renesas R8A7740 is CPU with Cortex-A9.
This supports the basic register definition and GPIO.

Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:25 +02:00
Tetsuyuki Kobayashi
2c1157df46 arm: rmobile: kzm9g: Add dummy member to struct sh73a0_rwdt
Add dummy member to struct sh73a0_rwdt in sh73a0.h.
Without this, initializing watch dog timer goes wrong.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:23 +02:00
Tetsuyuki Kobayashi
4306abda00 arm: rmobile: kzm9g: enable reset command
Do soft power on reset in U-Boot reset command.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:23 +02:00
Tetsuyuki Kobayashi
a12633122c arm: rmobile: kzm9g: Adjust low level hardware setting
Adjust low level hardware setting in s_init.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:22 +02:00
Nobuhiro Iwamatsu
8d811ca36a arm: rmobile: Add supoprt for KMC KZM-A9-GT board
The KZM-A9-GT board has Renesas R-Mobile SH73A0, 512MB DDR2-SDRAM,
USB, Ethernet, and more.

This patch supports the following functions:
	- 512MB DDR2-SDRAM
	- 16MB NOR Flash memory
	- Serial console (SCIF)
	- Ethernet (SMSC)
	- I2C

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:22 +02:00
Nobuhiro Iwamatsu
b045a23773 arm: rmobile: Add support PFC of Renesas SH73A0
Renesas SH73A0 has GPIO based PFC. This privode framework of PFC.
The code included in this base from linux kernel.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:22 +02:00
Nobuhiro Iwamatsu
1cdf2482d1 arm: rmobile: Add support Renesas SH73A0
Renesas SH73A0 is CPU with Cortex-A9.
This supports the basic register definition and GPIO.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:22 +02:00
Nobuhiro Iwamatsu
4fb44e22ec arm: rmobile: Add basic support for Renesas R-Mobile
This patch adds minimum support for R-Mobile. Only minimal support with timer.
This CPU can uses the peripheral of Renesas SuperH.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:22 +02:00
Nobuhiro Iwamatsu
a6cd85aad2 ARMv7: Add register definition of global timer
ARMv7 has global timer. This provides the register definition of this timer.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:22 +02:00
Joel A Fernandes
90207b6268 am33xx: Fix fetching of mmc1 bootmode from bootrom for AM33XX
U-boot should not ignore getting the bootmode passed on from the bootrom.
With this, U-boot SPL knows it was loaded from MMC1 and use this info to
read full U-boot from MMC1 as well.

Cc: pprakash@ti.com
Cc: trini@ti.com
Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-01 10:02:15 -07:00
Ilya Yanok
7ac2fe2da2 OMAP: networking support for SPL
This patch adds support for networking in SPL. Some devices are
capable of loading SPL via network so it makes sense to load the
main U-Boot binary via network too. This patch tries to use
existing network code as much as possible. Unfortunately, it depends
on environment which in turn depends on other code so SPL size
is increased significantly. No effort was done to decouple network
code and environment so far.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-01 10:02:14 -07:00
Albert ARIBAUD
1c27059a2f Merge remote-tracking branch 'u-boot/master' 2012-09-30 23:49:17 +02:00
Albert ARIBAUD
8f0732ac3d Merge remote-tracking branch 'u-boot-imx/master' 2012-09-29 11:12:34 +02:00
Tom Rini
3f7f2414ef ARM: SPL: Convert davinci to CONFIG_SPL_FRAMEWORK
- Convert the non-relocation part of board_init_f to spl_board_init, turn on CONFIG_SPL_BOARD_INIT in the configs.
- Remove duplicated code.
- Add spl_boot_device() that returns the statically chosen boot device.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 11:20:10 -07:00
Tom Rini
6507f133f3 SPL: Create arch/arm/lib/spl.c for board_init_f and jump_to_image_linux
In SPL (CONFIG_SPL_FRAMEWORK) board_init_f must setup the stack pointer,
clear the BSS and call board_init_r.  We mark this as weak as some
platforms may need to perform additional initalization at this point.
We provide a gd that we know will be in a usable location, once the BSS
has been cleared to help with this as well.  Finally, we no longer call
relocate_code so remove that from the armv7 version.

Next, both board_init_f and jump_to_image_linux are going to be
inherently arch-specific, so move these versions to arch/arm/lib/spl.c

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:49:59 -07:00
Tom Rini
47f7bcae8c SPL: Move the omap SPL framework to common/spl
Add a new flag, CONFIG_SPL_FRAMEWORK to opt into the common/spl SPL
framework, enable on all of the previously using boards.  We move the
spl_ymodem.c portion to common/ and spl_mmc.c to drivers/mmc/.  We leave
the NAND one in-place as we plan to replace it later in this series.

We use common/spl to avoid linker problems with respect to merging
constant strings in objects.   Otherwise all strings in common/ will be
linked in and kept which grows SPL in size too much.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:49:59 -07:00
Tom Rini
d4c4e0e117 ARM: SPL: Start hooking in the current SPI SPL support
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:49:58 -07:00
Tom Rini
f0881250f9 ARM: SPL: Make spl_mmc.c more generic
Move the default omap/related-centric board_mmc_init to
arch/arm/cpu/armv7/omap-common/boot-common.c and move the type defines
to <asm/spl.h>.  Also use mmc->read_bl_len rather than MMCSD_SECTOR_SIZE

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:49:58 -07:00
Tom Rini
55cdbb8d4e ARM: SPL: Add <asm/spl.h> and <asm/arch/spl.h>
Move the SPL prototypes from <asm/omap_common.h> into <asm/spl.h> and
add <asm/arch/spl.h> for arch specific portions of CONFIG_SPL_FRAMEWORK.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:49:57 -07:00
Tom Rini
8082fda9fc ARM: SPL: Remove NAND_MODE_HW_ECC from spl_nand.c
This detection code doesn't (and can't) do anything currently, so
remove.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:48:39 -07:00
Tom Rini
37189a1958 ARM: SPL: Rename omap_boot_mode to spl_boot_mode()
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:48:39 -07:00
Tom Rini
8e1b836ec5 ARM: SPL: Rename omap_boot_device to spl_boot_device
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:48:38 -07:00
Tom Rini
861a86f460 omap-common: SPL: Add CONFIG_SPL_DISPLAY_PRINT / spl_display_print()
Only omap4/5 currently have a meaningful set of display text and overo
had been adding a function to display nothing.  Change how this works to
be opt-in and only turned on for omap4/5 now.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:48:38 -07:00
Benoît Thébaudeau
362635bd50 mx51evk: Add CONFIG_REVISION_TAG
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG
information.

If this data is not present, the kernel misconfigures the TZIC, which results in
the timer interrupt handler never being called, so the kernel deadlocks while
calibrating its delay.

Suggested-by: Greg Topmiller <Greg.Topmiller@jdsu.com>
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-23 19:55:06 +02:00
Tom Rini
495dbd72dd Merge branch 'master' of git://git.denx.de/u-boot-arm 2012-09-21 14:53:13 -07:00
Albert ARIBAUD
d193c1b6eb Merge remote-tracking branch 'u-boot-imx/master' 2012-09-21 00:26:19 +02:00
Marek Vasut
535c74f80c ARM: Remove apollon board
This board is the only board that still sticks to OneNAND IPL.
Remove this board, since we have SPL around for a while and
OneNAND is well supported in the SPL framework. The board can
be revived if necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Tom Rini <trini@ti.com>
2012-09-18 12:01:51 -07:00
Tom Rini
037e9d33db Merge branch 'master' of git://git.denx.de/u-boot-i2c 2012-09-17 11:39:03 -07:00
Stefano Babic
19f59ea6db MX6: drop binary constants from iomux header
Constants set with binary value (0b...) are not compiled
from old toolchain when used by the clrsetbits_le32 macro.
Replaces them with the corresponding hex value.

The error reported (for example with the mx6qsabrelite board)
is something like:

mx6qsabrelite.c:369:1: error: invalid suffix "b101" on integer constant
mx6qsabrelite.c:369:1: error: invalid suffix "b10010" on integer constant
mx6qsabrelite.c:369:1: error: invalid suffix "b0000" on integer constant
mx6qsabrelite.c:369:1: error: invalid suffix "b10001" on integer constant

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-09-17 13:17:06 +02:00
Tom Warren
29f3e3f248 Tegra: Change Tegra20 to Tegra in common code, prep for T30
Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.

Upcoming Tegra30 port will use common code/defines/names where possible.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2012-09-10 13:01:24 -07:00
Jim Lin
312693c3dd tegra: nand: Add Tegra NAND driver
A device tree is used to configure the NAND, including memory
timings and block/pages sizes.

If this node is not present or is disabled, then NAND will not
be initialized.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07 13:54:31 -07:00
Simon Glass
35e1132c88 tegra: Add NAND support to funcmux
Add selection of NAND flash pins to the funcmux.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07 13:54:30 -07:00
Benoît Thébaudeau
0dc7b82e4e mx31: Define default SoC input clock frequencies
Define default SoC input clock frequencies for i.MX31 in order to get rid of
duplicated definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Helmut Raiger <helmut.raiger@hale.at>
2012-09-06 14:23:30 +02:00
Benoît Thébaudeau
9c6c5c0676 mx35: Define default SoC input clock frequencies
Define default SoC input clock frequencies for i.MX35 in order to get rid of
duplicated definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-06 11:05:17 +02:00
Benoît Thébaudeau
1b2080f338 mx25: Define default SoC input clock frequencies
Define default SoC input clock frequencies for i.MX25 in order to get rid of
duplicated definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Matthias Weisser <weisserm@arcor.de>
2012-09-06 11:05:09 +02:00
Benoît Thébaudeau
82e1b543b5 mx35: Fix clock dividers
The clock dividers that were used do not match at all the reference manual. They
were either completely broken, or came from an early silicon revision
incompatible with the current one.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-09-06 11:05:01 +02:00
Benoît Thébaudeau
9ba81baabb mx35: Add definitions for clock gate values
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-09-06 11:04:53 +02:00
Koen Kooi
a532278074 omap4 i2c: add support for i2c bus 4
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
2012-09-06 06:01:09 +02:00
Jaehoon Chung
8458e0283f mmc: s5p_sdhci: fixed wrong function argument
Useless code is removed, and get buswidth value.
buswidth value will be used to choice the 4bit or 8bit.
(Now used 4bit mode in sdhci.c by default)

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-09-05 17:33:26 -05:00
Stefano Babic
fb380bfa8c OMAP3: video: add macros to set display parameters
Add a common macros to set the registers for horizontal
and vertical timing.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-09-04 17:05:39 -07:00
Stefano Babic
baee780013 video: drop duplicate set of DISPC_CONFIG register
Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-09-04 17:05:39 -07:00
Arnout Vandecappelle (Essensium/Mind)
4aaf06415f OMAP3: add definition of CTRL_WKUP_CTRL register
AM/DM37x SoCs add the CTRL_WKUP_CTRL register.  It contains the
GPIO_IO_PWRDNZ bit, which is required to be set to enable the I/O pads
of gpio_126, gpio_127 and gpio_129.

Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
Cc: Tom Rini <trini@ti.com>
2012-09-04 17:05:38 -07:00
Valentin Longchamp
8203b201ea kw_spi: fix clock prescaler computation
The computation was not correct with low clock values: setting a 1MHz
clock would result in an overlap that would then configure a 25Mhz
clock.

This patch implements a correct computation method according to the
kirkwood functionnal spec. table 600 (Serial Memory Interface
Configuration Register).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2012-09-03 17:28:51 +05:30
Wolfgang Denk
7cdcaef0b2 Merge branch 'master' of git://git.denx.de/u-boot-usb
* 'master' of git://git.denx.de/u-boot-usb:
  MUSB driver: Timeout is never detected as the while loop does not end
  usb: fix ulpi_set_vbus prototype
  pxa25x: Add UDC registers definitions
  USB: Fix strict aliasing in ohci-hcd
  usb: Optimize USB storage read/write
  ehci: Optimize qTD allocations
  usb_stor_BBB_transport: Do not delay when not required
  usb_storage: Remove EHCI constraints
  usb_storage: Restore non-EHCI support
  ehci-hcd: Boost transfer speed
  ehci: cosmetic: Define used constants
  ehci: Fail for multi-transaction interrupt transfers
  arm:trats: Enable g_dnl composite USB gadget with embedded DFU function on TRATS
  arm:trats: Support for USB UDC driver at TRATS board.
  dfu:cmd: Support for DFU u-boot command
  dfu: MMC specific routines for DFU operation
  dfu: DFU backend implementation
  dfu:usb: DFU USB function (f_dfu) support for g_dnl composite gadget
  dfu:usb: Support for g_dnl composite download gadget.
  ehci: cosmetic: Define the number of qt_buffers

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-09-02 16:38:48 +02:00
Łukasz Dałek
a6a78be025 pxa25x: Add UDC registers definitions
Signed-off-by: Łukasz Dałek <luk0104@gmail.com>
2012-09-01 16:21:53 +02:00
Benoît Thébaudeau
8e99ecd74b mxc: Define architecture identifier
Define ARCH_MXC for i.MX devices. This is useful to identify features or
behaviors common to all i.MX SoCs.

The i.MX28 is omitted because its architecture is a bit different (like imx/mxc
vs. mxs in Linux).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
2012-09-01 14:58:30 +02:00
fabio.estevam@freescale.com
a123312f4d mxs: Convert timeout parameter to 'unsigned int'
For representing a timeout value, it makes more sense to pass it as
'unsigned int'.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:30 +02:00
Marek Vasut
615a4ad0f6 MX28: DMA: Align the struct mxs_dma_desc
Align this structure to DMA alignment size.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:29 +02:00
trem
e71c39def6 gpio: add gpio api support to mx27 (v4)
The gpio api has been tested on an armadeus apf27.

Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:29 +02:00
Matt Sealey
af369d9831 mx5: add iomux-mx51.h include
Allow usage of the imx-common/iomux-v3.h framework by including pad settings
for the i.MX51. The content of the file is taken from Linux kernel at
commit 5d23b39 plus the required changes to make it work in U-Boot.

The contained pad settings are the minimum required to make an Efika MX boot
and get all the currently-implemented peripherals working in U-Boot.

It is recommended that this file not be just a dumping ground for pins but
only contain the settings required for all the boards using it.

Changes for v2:
 * reference commit id from Linux kernel
 * additionally roll in the USB pads
 * removed GPIO_NUMBER define

Signed-off-by: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:29 +02:00
Otavio Salvador
72f8ebf17e mxs: Rename 'mx28_dram_init' to 'mxs_dram_init'
The DRAM initialization, after SPL has complete, is exactly the same
for all mxs SoCs so we should name it accordinly.

The following boards has been changed:

 * apx4devkit
 * m28evk
 * mx28evk
 * sc_sps_1

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
2012-09-01 14:58:28 +02:00
Otavio Salvador
6e829b672e mxs: Replace i.MX233 by i.MX23 on copyright header
All other header are going to use i.MX23 so we change this for
consistency.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:28 +02:00
Benoît Thébaudeau
483920f273 mx35: Remove declaration of non-existing function
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:28 +02:00
Benoît Thébaudeau
7c80326d34 mx35: Move clock enums to clock.h
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:28 +02:00
Benoît Thébaudeau
d365e2d7c3 mx35: Remove declaration of non-existing function
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:28 +02:00
Benoît Thébaudeau
fe24d6143d mx35: Fix broken pin definitions
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:28 +02:00
Benoît Thébaudeau
4311c1ab6a mx5: Undeclare imx_decode_pll()
The imx_decode_pll() function does not exist for mx5, so remove its declaration.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:27 +02:00
Stefano Babic
5fecb36ca0 MX: Set a common gpio.h for all i.MX
Each i.MX has its own gpio.h, defining the same structure.
The internal GPIO controller has the same layout
(at least for the register used by u-boot) and can be shared.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Tested-by: Matt Sealey <matt@genesi-usa.com>
2012-09-01 14:58:27 +02:00
Fabio Estevam
c55068e5b8 mxs: Use correct function name to initialize dram
commit d92591a (mxs: Convert sys_proto.h prefixes to 'mxs') introduced
a mxs_dram_init() function, which is not used anywhere.

Fix it, so that the following warning goes away:

mx28evk.c: In function ‘dram_init’:
mx28evk.c:67:2: warning: implicit declaration of function ‘mx28_dram_init’ [-Wimplicit-function-declaration]

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:27 +02:00
Troy Kisky
124a06d7fb imx-common/cmd_bmode.c: add imx bmode (bootmode) command
This is useful for forcing the ROM's
usb downloader to activate upon a watchdog reset.
Or, you can boot from either SD Card.

Currently, support added for MX53 and MX6Q
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Note: MX53 support untested.
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Troy Kisky
d1c679a46d iomux: move IOMUX_GPR13_xxx defines
Move mx6 specific defines to arch-mx6 directory.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Benoît Thébaudeau
83209cb785 mx35: Remove duplicate GPIO3_BASE_ADDR
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Benoît Thébaudeau
f2d3ae0739 mx3: Fix typo on IPU_CONF_CSI_EN
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Benoît Thébaudeau
34a31bf52b mx35: Fix typo on EDIO
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
trem
78befb695d rtc: add support of mx27 rtc
This driver has been tested on board armadeus apf27.

Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:25 +02:00
Otavio Salvador
fa7a51cb82 mxs: Convert sys_proto.h prefixes to 'mxs'
The sys_proto.h functions (except the boot modes) are compatible with
i.MX233 and i.MX28 so we use 'mxs' prefix for its methods.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:25 +02:00
Otavio Salvador
af963ba8f4 mxs: rename regs-clkctrl.h to regs-clkctrl-mx28.h
The CLKCTRL registers are SoC specific so we ought to have it clear on
filename.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:25 +02:00
Donghwa Lee
6fff52b93a video: support exynos pwm backlight driver
This patch support exynos pwm backlight driver. It can control backlight
power and brightness by using pwm.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:24 +02:00
Donghwa Lee
a29c832263 video: exynos fb driver supports display port feature
If dp_enabled was set, exynos fb driver support display port feature.
This patch depends on [PATCH] video: support exynos fimd driver
for various exynos series.

http://marc.info/?l=u-boot&m=134119605104467&w=2

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:24 +02:00
Donghwa Lee
d2a6982f9b video: support exynos display port drivers
This patch set supports exynos display port drivers.

DisplayPort is an industry standard device to accommodate the increasing board
adoption of digital display technology within the PC and consumer electronics.
The interface supports internal chip-to-chip and external box-to-box digital
display connections.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:24 +02:00
Donghwa Lee
c401505000 EXYNOS5: add display port base address
This patch add display port base address for EXYNOS5. In case of EXYNOS4,
use DEVICE_NOT_AVAILABLE macro because DP is not supported.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:24 +02:00
Donghwa Lee
b6516677c0 EXYNOS5: support display port phy control function
This patch support display port phy control function.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:24 +02:00
Donghwa Lee
ee93dcfa2e video: support exynos fimd driver for various exynos series
This patch supports exynos fimd driver for various exynos series different from
existing it supports only exynos4 chip.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:24 +02:00
Rajeshwari Shinde
fd8ef01452 EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0
This patch modifies the pinmux settings of MMC and UART as per
Exynos5250 Rev 1.0.
It also corrects the gpio offset calculations.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:23 +02:00
Rajeshwari Shinde
10bc1a7f49 EXYNOS5: CLOCK: Add BPLL support
This patch adds support for BPLL clock.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:23 +02:00
Rajeshwari Shinde
6071bcaec1 EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:23 +02:00
Rajeshwari Shinde
87f2e079db Exynos5: DDR3: Add DDR3 memory setup for Exynos5250 Rev 1.0
The patch adds the memory initialization sequence of DDR3.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:23 +02:00
Rajeshwari Shinde
526b570699 EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0
Define additional registers for clock control in Exynos5250 Rev 1.0

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:23 +02:00
Rajeshwari Shinde
589c397169 ARCH: SPL: Add parametric board initializer
Add a structure for table-driven configuration mechanism such that no recompilation
is needed to update the configuration parameters, rather than hard-coding
board initialization parameters.

Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:22 +02:00
Allen Martin
c037c93bf9 ARM: add tegra20 support to arm720t
Add support for tegra20 arm7 boot processor.  This processor is used
to power on the Cortex A9 and transfer control to it.  In tegra this
processor is an ARM7TDMI not an ARM720T, but since we don't use cache
it was easier to just reuse the ARM720T code as the processors are
otherwise identical except for cache and MMU.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01 14:58:22 +02:00
Allen Martin
00a2749d7b tegra20: rename tegra2 -> tegra20
This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01 14:58:21 +02:00
Stephen Warren
efad6cf881 ARM: add basic support for the Broadcom BCM2835 SoC
This SoC is used in the Raspberry Pi, for example.

For more details, see:
http://www.broadcom.com/products/BCM2835
http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf.

Initial support is enough to boot to a serial console, execute a minimal
set of U-Boot commands, download data over a serial port, and boot a
Linux kernel. No storage or network drivers are implemented.

GPIO driver originally by Vikram Narayanan <vikram186@gmail.com>
with many fixes from myself.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2012-09-01 14:58:21 +02:00
Mathieu J. Poirier
75dfe964cb u8500: Enabling power to MMC device on AB8500 V2
Register mapping has changed on power control chip between
the first and second revision.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:20 +02:00
Mathieu J. Poirier
1e37322e5a u8500: Moving processor-specific functions to cpu area.
Functions such as providing power to the MMC device and reading
the processor version register should be in the cpu area for
access by multiple u8500-based boards.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:20 +02:00
Mathieu J. Poirier
b95f9ec7d8 snowball: applying power to LAN and GBF controllers
LAN and GBF need to be powered explicitely, doing so with
interface to AB8500 companion chip.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01 14:58:20 +02:00
Mathieu J. Poirier
101a769d75 snowball: Moving to ux500.v2 addess scheme for PRCMU access
Addresses between ux500.v1 and ux500.v2 have changed slightly,
hence mandating a review of the PRCMU access methods.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01 14:58:20 +02:00
Mathieu J. Poirier
81637e26b3 snowball: Adding CPU clock initialisation
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01 14:58:20 +02:00
Mathieu J. Poirier
9652de7c48 snowball: Adding architecture dependent initialisation
Enabling timers and clocks in PRCMU and cleaning up mailbox.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01 14:58:19 +02:00
Mathieu J. Poirier
42cb8fb6cb u8500: Moving prcmu to cpu directory
This is to allow the prcmu functions to be used by multiple
u8500-based processors.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01 14:58:19 +02:00
Mathieu J. Poirier
84dee301c3 snowball: Add support for ux500 based snowball board
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>

Conflicts:

	drivers/gpio/Makefile
2012-09-01 14:58:19 +02:00
Satyanarayana, Sandhya
6995a28937 am33xx evm: Update secure_emif_sdram_config during ddr init
This patch updates secure_emif_sdram_config with the
same value written to sdram_config during ddr3 initialization.

During suspend/resume, this value is copied into sdram_config.
With this, a write to sdram_config at the end of resume sequence
which triggers an init sequence can be avoided.

Without this register write in place, the DDR_RESET line goes
low for a few cycles during resume which is a violation of the
JEDEC spec.

Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
2012-09-01 14:58:19 +02:00
Sughosh Ganu
25f8bf6eff da8xx/hawkboard: Add support for ohci host controller
Also enable the ohci port on hawkboard. These additions result in an
increased u-boot size -- adjust the same accordingly in the board's
config.

Move the usb header for da8xx platforms under arch-davinci.

Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
2012-09-01 14:58:19 +02:00
Tom Rini
41aebf8106 omap4/5/am33xx: Make lowlevel_init available to all armv7 platforms
Make the lowlevel_init function that these platforms have which just
sets up the stack and calls a C function available to all armv7
platforms.  As part of this we change some of the macros that are used
to be more clear.  Previously (except for am335x evm) we had been
setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are
equivalent to simply referencing NON_SECURE_SRAM_END.  On am335x evm we
should have been doing this initially and do now.

Cc: Sricharan R <r.sricharan@ti.com>
Tested-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:19 +02:00
Tom Rini
0689a2ef19 am33xx: Correct MMC1, remove MMC2 support
- Correct the MMC1 base offset
- Remove MMC2 (that area is reserved and not MMC2).
- Add the real BOOT_DEVICE_MMC2 value

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:18 +02:00
Otavio Salvador
1e0cf5c34b mxs: Reowork SPL to use 'mxs' prefix for methods
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:17 +02:00
Otavio Salvador
9c471142bc mxs: prefix register structs with 'mxs' prefix
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:17 +02:00
Otavio Salvador
ddcf13b152 mxs: prefix register acessor macros with 'mxs' prefix
As the register accessing mode is the same for all i.MXS SoCs we ought
to use 'mxs' prefix intead of 'mx28'.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:17 +02:00
Otavio Salvador
3a0398d7b9 mxs: reorganize source directory for easy sharing of code in i.MXS SoCs
Most code can be shared between i.MX23 and i.MX28 as both are from
i.MXS family; this source directory structure makes easy to share code
among them.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:17 +02:00
Otavio Salvador
b0261b1212 MX28: extend print_cpuinfo() to use chip information
The information now is gathered from HW_DIGCTL_CHIPID register and
includes the chip modem and revision on the output.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:16 +02:00
Bo Shen
f7fa2f3740 arm : Atmel : add at91sam9x5ek board support
Add at91sam9x5ek board support, this board support the following SoCs
  AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35

Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up

Signed-off-by: Bo Shen <voice.shen@atmel.com>
[move MAINTAINERS entry to right place]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01 14:58:14 +02:00
Laurence Withers
de9d2e3d60 DaVinci DA8xx: replace magic number for DDR speed
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
2012-09-01 14:58:14 +02:00
Laurence Withers
88ac6b9d14 DaVinci DA850: UART2 clock ID comes from ASYNC3
On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
controller 0 or 1. Fix the definition of the ID to match.

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
2012-09-01 14:58:14 +02:00
Laurence Withers
8a54aa0da7 DaVinci DA8xx: tidy up clock ID definition
Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in
place, it is clear how to define new clock IDs, and how these map to the
numbers presented in the technical reference manual.

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
db7dd8109c am33xx: Rework pinmux functions
- Move definition of the EEPROM contents to <asm/arch/sys_proto.h>
  - Make some defines a little less generic now.
- Pinmux must be done by done by SPL now.
- Create 3 pinmux functions, uart0, i2c0 and board.
- Add pinmux specific to Starter Kit EVM for MMC now.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
65d750be59 am33xx: Add support for TI AM335x StarterKit EVM
- Board requires gpio0 #7 to be set to power DDR3.
- Board uses DDR3, add a way to determine which DDR type to call
  config_ddr with.
- Both of the above require filling in the header structure early, move
  it into the data section.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
d4898ea896 am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and support
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
a74f0c7cb5 am33xx: Correct and clean up ddr_regs struct
The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported).  Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero, remove.  Next, setting of the
'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the
ddr_data entries, so program it there.  Finally, comment on how we are
configuring the DATA1 registers that correspond to the DATA0 (dt0)
registers defined in the struct.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
82afcc9efd am33xx: Do not touch 'ratio1' fields
The various ratio1 fields are not documented in any of the documentation
I can find.  Removing these and testing has yielded success, so remove
the code that sets them and move their locations into the reserved
fields.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
5ac3b7ada1 am33xx: Rework config_io_ctrl slightly
This function sets a number of related registers to the same value (the
registers in question all have the same field descriptions and are
related in operation).  Rather than defining a struct and setting the
value repeatedly, just pass in the value.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
ff7ec0f945 am33xx: Use emif_regs struct for storing initialization values
Rather than defining our own structs to note what to use when
programming the EMIF and related re-use the emif_regs struct.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
87a1acbb69 am33xx: Turn a number of 'int' functions to 'void'
A number of memory initalization functions were int and always returned
0.  Further it's not feasible to be doing error checking here, so simply
turn them into void functions.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
c48c895433 am33xx: Document what we're doing with ddrctrl->ddrckectrl
- Remove the call to set ddrctrl->ddrioctrl as it's all zeros.
- Comment what we're really setting in ddrctrl->ddrckectrl which is that
  we're operating in the normal mode where EMIF/PHY clock is controlled
  by the PHY.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Vaibhav Bedia
7d8a961d31 am335x: ddr_defs: Update EMIF parameters
EMIF parameters are calculated based on the AC timing
parameters from the SDRAM datasheet and the DDR frequency.

Current values for these paramters in AM335x U-Boot code,
though reliable, are not fully optimal. The most optimal
settings can be derived based on the guidelines published
at [1]. A pre-computed set of values with the most optimum
settings for AM335x EVM and BeagleBone can be found at [2].

[1] http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
[2] http://processors.wiki.ti.com/index.php/OMAP_and_Sitara_CCS_support#AM335x

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
c8da4a587c am33xx: Clean up unused DDR defines, prefix more with 'DDR2'
- Remove a handful of unused defines.
- Prefix more values with 'DDR2' as DDR3 will require different values.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
b971dfad6a am33xx: Move the call to ddr_pll_config, make it take the frequency
Depending on if we have DDR2 or DDR3 on the board we will need to call
ddr_pll_config with a different value.  This call can be delayed
slightly to the point where we know which type of memory we have.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
fda35eb982 am33xx: Pass to config_ddr the type of memory that is connected
We need to pass in the type of memory that is connected to the board.
The only reliable way to do this is to know what type of board we are
running on (which later will be knowable in s_init()).  For now, pass in
the value of DDR2.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
bce58fece5 am33xx: Make config_cmd_ctrl / config_ddr_data take const structs
Rework the EMIF4/DDR code slightly to setup the structs that
config_cmd_ctrl and config_ddr_data take to be setup at compile time and
mark them as const.  This lets us simplify the calling path slightly as
well as making it easier to deal with DDR3.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
7d5eb34908 am33xx: Convert to using <asm/emif.h> to describe the EMIF
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:11 +02:00
Tom Rini
79b3e6b75b am33xx: Remove DMM_BASE define
The am33xx does not have a DMM, so don't define the base.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:11 +02:00
Javier Martinez Canillas
41708a5db4 OMAP3: mem: Add Numonyx OneNAND 200MHz timing information
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
2012-09-01 14:58:11 +02:00
Chandan Nath
89017e150e am33xx: pin mux defintions for CPSW switch
This patch adds pin mux settings for CPSW switch found on
TI AM335X based boards (MII and RGMII modes).

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
[Ilya: split pinmux into separate patch]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-09-01 14:58:11 +02:00
Chandan Nath
e79cd8eb9b am33xx: CPSW init and definitions
This patch adds platform-specific initialization for CPSW
switch on TI AM33XX SoCs.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
[Ilya: split init out of original patch]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-09-01 14:58:11 +02:00
Mikhail Kshevetskiy
680866a502 arm/davinci/da850: add uart0 pinmux
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
Tested-by: Sughosh Ganu <urwithsughosh@gmail.com>
2012-09-01 14:58:10 +02:00
Mikhail Kshevetskiy
89473d233f arm/davinci: fix DDR2/mDDR memory controller initialization for Omap L138
follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of
OMAP-L138 DSP+ARM Processor Technical Reference Manual

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
Tested-by: Christian Riesch <christian.riesch@omicron.at>
2012-09-01 14:58:10 +02:00
Lad, Prabhakar
ecc98ec18c da850/omap-l138: Add MMC support for DA850/OMAP-L138
This patch adds support for MMC/SD on DA850/OMAP-L138.

Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
2012-09-01 14:58:09 +02:00
Steve Sakoman
3b97152b63 omap: am33xx: enable gpio support
This patch uses the code in omap-common to support gpio modules 1-3
on am33xx based boards.

It adds base address and register definitions, enables clocks to the
modules, and enables building the common gpio code for CONFIG_AM33XX
as well as CONFIG_OMAP

Signed-off-by: Steve Sakoman <steve@sakoman.com>
2012-09-01 14:58:09 +02:00
Mike Frysinger
47fde91f0c global_data: unify global flag defines
All the global flag defines are the same across all arches.  So unify them
in one place, and add a simple way for arches to extend for their needs.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-08-09 21:46:32 +02:00
Rajeshwari Shinde
91dffb16ff I2C: Move struct s3c24x0_i2c to a common place.
struct s3c24x0_i2c is being moved to common local header file so that
the same can be used by s3c series and exynos series SoCs.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31 08:02:41 +02:00
Rajeshwari Shinde
c65c05f57f EXYNOS: PINMUX: Add pinmux support for I2C
This patch adds pinmux code for I2C.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31 08:02:28 +02:00
Rajeshwari Shinde
8da3eb1b22 EXYNOS5: define EXYNOS5_I2C_SPACING
This patch defined EXYNOS5_I2C_SPACING used to calculate I2C channel
base address.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31 08:02:07 +02:00
Rajeshwari Shinde
1a758aec3d EXYNOS: Add I2C base address.
This patch adds the base address for I2C.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31 08:01:56 +02:00
Rajeshwari Shinde
989feb8c52 EXYNOS: CLK: Add i2c clock
This adds i2c clock information for EXYNOS5.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31 08:01:32 +02:00
Troy Kisky
cc54a0f7cc imx-common: add i2c.c for bus recovery support
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31 08:00:57 +02:00
Troy Kisky
df369dcdb0 i.mx53: add definition for I2C3_BASE_ADDR
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31 08:00:44 +02:00
Troy Kisky
af2a35fb1f i.mx: iomux-v3.h: move to imx-common include directory
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31 08:00:19 +02:00
Ashok
6b8ac524e7 mx6: Make pad name macro consistent with the datasheet
Use the same name as defined in the datasheet.
DSP_CLK -> DISP_CLK

Signed-off-by: Ashok Kumar Reddy Kourla <ashokkourla2000@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-07-20 23:03:28 +02:00
Wolfgang Denk
66714b1a6d Merge branch 'next' of git://git.denx.de/u-boot-video
* 'next' of git://git.denx.de/u-boot-video:
  ipu_common: Add ldb_clk for use in parenting the pixel clock
  ipu_common: Do not hardcode the ipu_clk frequency
  ipu_common: Rename MXC_CCM_BASE
  ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53
  ipu_common: Only apply the erratum to MX51
  video: Rename CONFIG_VIDEO_MX5
  mx6: Allow mx6 to access the IPUv3 registers
  common lcd: minor coding style changes

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-18 10:47:03 +02:00
Troy Kisky
de6f604de2 mxc_i2c: specify i2c base address in config file
The following platforms had their config files changed
flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd
and mx53loco.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-11 10:54:29 +02:00
Fabio Estevam
05d4df1d8a mx6: Allow mx6 to access the IPUv3 registers
Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10 11:35:38 +02:00
Wolfgang Denk
895f3e0542 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  tegra: define fdt_load/fdt_high variables
  tegra: enable bootz command
  tegra: usb: Fix device enumeration problem of USB1
  tegra: trimslice: set up serial flash pinmux
  tegra: add pin_mux_spi() board initialization function
  tegra: add GMC/GMD funcmux entry for SFLASH
  tegra: bootcmd: start USB only when needed
  tegra: bootcmd enhancements
  tegra: add enterrcm command
  tegra: enable CONFIG_ENV_VARS_UBOOT_CONFIG
  Add env vars describing U-Boot target board
  tegra: usb: fix wrong error check
  tegra: add ULPI on USB2 funcmux entry
  tegra: fix leftover CONFIG_TEGRA2_MMC & _SPI build switches
  tegra: Add Tamonten Evaluation Carrier support
  tegra: Use SD write-protect GPIO on Tamonten
  tegra: Implement gpio_early_init() on Tamonten
  tegra: Allow boards to perform early GPIO setup
  tegra: plutux: Add device tree support
  tegra: medcom: Add device tree support
  tegra: Rework Tamonten support
  beagle: add eeprom expansion board info for bct brettl4

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-10 08:54:41 +02:00
Jim Lin
8b3f7bf7ec tegra: usb: Fix device enumeration problem of USB1
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like "usb reset" in u-boot command line).
This will be treated as an error and stops later device enumeration.

Therefore we clear that bit after Port Reset in order to proceed
later device enumeration.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-09 22:44:34 +02:00
Stephen Warren
a016e144ed tegra: add GMC/GMD funcmux entry for SFLASH
This is used on TrimSlice.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-09 22:44:33 +02:00
Lucas Stach
f97daaa231 tegra: add ULPI on USB2 funcmux entry
This is needed as a prerequisite for Tegra USB ULPI support
within U-Boot.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-09 22:44:33 +02:00