This patch adds the front led initialization and the application
buffer enable to the eraly board inititlaization.
Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com>
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
In order to improve power consumption ls102x allows to disable peripherals
that are not in use.
This patch follows SELI8 HW design description and disables peripherals
that are not in use in our designs, the same configuration is applicable
and for EXPU1.
This patch uses available hwconfig option for updating ls102x device
disable configuration.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The default behavior in the latest u-boot revisions is to rotate the
active net device to the next available if the requested link is not
established.
For our ls102x based devices this would mean that if active debug net
device is not available, u-boot will rotate and set the next net device
that is one of the estar adapters.
To return from this situation manual action to set correct ethact
adapter will be needed and this can be annoying when working in
debug mode.
Setting ethrotate=no will disable net adapter rotation and will make sure
that the primary adapter is always used.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This is most probably a typo, and in older u-uboot versions is same as
'saveenv', in the newer uboot versions there is a separate 'save' command
that is different from 'saveenv'.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
In our designs we reserve PRAM area at the end of the RAM, and in order
this area to be visible and taken into account by the u-boot memory mgmt
CONFIG_PRAM has to be defined.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
From production view this is standard test executed during production on
all linux based foxmc cards.
On CENT2 HW defined memory region is zero means that some DDR accesses are
done by memory_post_dataline and memory_post_addrline but pattern tests
are skipped that's why mem_regions is fast there.
On ls102x for the complete DDR region of 1GiB memory_regions_post_test
takes approx. 4min and this is too much for production, so this patch
defines only 1MiB region as compromise.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The EXPU1 design is a new 40G capable ethernet service unit card for
Hitachi-Powergrids wired-com product lines.
The base SoC is same as for already added SELI8 card, consequently the
already added u-boot support for SELI8 is reused.
Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com>
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
[Fixed new line error at EOF]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Address and size cells on SOC are set to 1. But gpio nodes are specified
with 2 cells. This fixes the gpio nodes to correct cells.
Signed-off-by: Lasse Klok Mikkelsen <lkmi@prevas.dk>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Current tsec adapter sets adapter gigabit capabilities by default, and in
reality this must not always be the case.
It is possible that tsec adapter is used for 100Mbps connection, and in
this case setting 1000Mbps capabilities can lead to some side effects such
longer autoneg process.
In our ls102x designs this problem leads to long autoneg times (> 4 sec)
in case board rgmii link is 100Mbps capable only.
Limiting the rgmii link capabilities provides faster and smoother
link establishment.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Commit df86d32 breaks linux kernel and product application boot.
Linux kernel and our product application scripts are expecting 0x prefix
for hexadecimal values, while env_set_hex writes them without a prefix.
This patch partially revert env_set_hex usage for affected env variables.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
During the mainlining of the board this was by mistake set to sector size.
Our user space env scripts are expecting envsize of 0x4000, and setting
this differently will break our cross-platform compatibility.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
is used instead.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Michael Walle <michael@walle.cc> [for kontron-sl28]
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
For eSDHC, power supply is through peripheral circuit.
Some eSDHC versions have value 0 of the bit but that
does not reflect the truth. 3.3V is common for SD/MMC,
and is supported for all boards with eSDHC in current
u-boot. So, make 3.3V is supported in default in code.
CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT can be enabled if
future board does not support 3.3V.
This is also a fix-up for one previous patch, which converted
to use IS_ENABLED() for CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
that is not a Kconfig option.
Fixes: 52faec3182 ("mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()")
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
These boards, according to the schematic and per the board I own, use an
M24256-BWDW6TP I2C EEPROM which requires two address bytes.
This fixes the 'mac' command which is used to program, among other
things, the MAC addresses for the ethernet interfaces on the board.
Signed-off-by: Matt Merhar <mattmerhar@protonmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
IFC NOR flash base address of ls2088a is 0x580000000,
and offset of env crc is 0x500000, so fix the macro
CONFIG_ENV_ADDR to fix synchronous exception(access illegal address)
Fixes: 59071804c1 ("configs: ls2080a: Correct ENV_ADDR value")
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Stop to initialize the PCIe controller if it's disabled by RCW.
Fixes: 118e58e26e ("pci: layerscape: Split the EP and RC driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Read Linux PPFE firmware from flash partition and pass it to Linux through
FDT entry. So that we can avoid placing PPFE firmware in Linux rootfs.
(FDT may increase at max by 64KB)
Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
For cpu release command, check whether PSCI is supported firstly,
if supported, use PSCI to kick off secondary cores, otherwise still
use spin table.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
[Fixed checkpatch alignment CHECKs]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Add check for return value of adjust_vdd()
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This adds the unit test for the K210 PLL to the sandbox defconfigs.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that the k210 clock driver does not depend on CCF, we should no longer
imply it (and probably should not have in the first place). We can also
reduce the pre-relocation malloc arena back to something sensible.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Linux has had some stability issues when using AISRAM with a different
frequency from SRAM. Mirror their change here now that we relocate into
AISRAM.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Now that we have only one clock driver, we don't need to have our own
subdirectory. Move the driver back with the rest of the clock drivers.
The MAINTAINERS for kendryte pinctrl is also fixed since it has always been
wrong.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This driver no longer serves a purpose now that we have moved away from
CCF. Drop it.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This speeds up boot by preventing multiple reconfigurations of the PLLs.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This adds support for setting clock rates, which was left out of the
initial CCF expunging. There are several tricky bits here, mostly related
to the PLLS:
* The PLL's bypass is broken. If the PLL is reconfigured, any child clocks
will be stopped.
* PLL0 is the parent of ACLK which is the CPU and SRAM's clock. To prevent
stopping the CPU while we configure PLL0's rate, ACLK is reparented
to IN0 while PLL0 is disabled.
* PLL1 is the parent of the AISRAM clock. This clock cannot be reparented,
so we instead just disallow changing PLL1's rate after relocation (when
we are using the AISRAM).
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Since we are no longer using CCF we cannot use the default soc_clk_dump.
Instead, implement our own.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Now that there no separate PLL driver, we can no longer make the PLL
functions static. By moving the PLL driver in with the rest of the clock
code, we can make these functions static again. We still keep the pll
header for unit testing, but it is pretty reduced.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This is effectively a complete rewrite to remove all dependency on CCF.
The code is now smaller, and so is the binary. It also takes up less memory
at runtime (since we don't have to create 40 udevices). In general, I am
much happier with this driver as much of the complexity and late binding
has been removed.
The k210_*_params structs which were previously used to initialize CCF
clocks are now used as the complete configuration. Since we can write our
own division logic, we can now do away with several "half" clocks which
only existed to provide constant factors of two.
The clock IDs have been renumbered to remove unused clocks. This may not be
the last time they are renumbered, since we have diverged with Linux. There
are also still a few clocks left out which may need to be added back in.
In general, I have tried to leave out behavioral changes. However, there is
a small bugfix regarding ACLK. According to the technical reference manual,
its mux comes *after* its divider (which is present only for PLL0). This
would have required yet another intermediate clock to fix with CCF, but
with the new driver it is just 2 lines of code :)
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc
state for SPL only") it has been impossible to set clock defaults before
relocation. This is annoying on boards without SPL, since there is no way
to set clock defaults before U-Boot proper. In particular, the aisram rate
must be changed before relocation on the K210, since U-Boot will hang if we
try and change the rate while we are using aisram.
To get around this, extend the stage parameter to allow force setting
defaults, even if they would be otherwise postponed for later. A device
tree property was decided against because of the concerns in the original
commit thread about the overhead of repeatedly parsing the device tree.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Current logic in riscv_get_ipi() for Andes PLICSW does not look
correct. The mask to test IPI pending bits for a hart should be
left shifted by (8 * gd->arch.boot_hart), just the same as what
is done in riscv_send_ipi().
Fixes: 8b3e97badf ("riscv: add functions for reading the IPI status")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
The doc says CONFIG_SKIP_LOWLEVEL_INIT is in ax25-ae350.h, while
actually it is not. Remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The
intention was to use gdb to load device tree before running U-Boot
SPL/proper from RAM. When we switch to OF_SEPARATE we will have to
use our own DT but without "u-boot,dm-spl" in several essential
nodes, SPL does not boot.
Let's add all the required "u-boot,dm-spl" for SPL config.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
All the device nodes that refer to plic0 as their interrupt parent
have 2 cells encoded in their interrupts property, but plic0 only
provides 1 cell in #interrupt-cells which is incorrect.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
PLIC nodes don't have child nodes, so #address-cells is not needed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
There are two spaces before "debug' in bootargs. Drop one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The SPDX license header is currently missing. Add one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
When using bootefi to boot a EFI binary, u-boot is supposed to
provide networking service for EFI application. Currently, 'pfe stop'
command is called from bootcmd before running bootefi. As a result
network stops working for EFI applications and console is flooded with
"Rx pkt not on expected port" messages.
Implement board_quiesce_devices() for ls1012a boards and call
pfe_command_stop() from it instead of calling 'pfe stop' from
*_bootcmd and bootcmd.
Tested-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
[Fixed checkpatch space error]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
It was noticed that the clock isn't continuously enabled when there is
no link. This is because the 125MHz clock is derived from the internal
PLL which seems to go into some kind of power-down mode every once in a
while. The LS1028A expects a contiuous clock. Thus enable the PLL all
the time.
Also, the RGMII pad voltage is wrong, it was configured to 2.5V (that is
the VDDH regulator). The correct voltage is 1.8V, i.e. the VDDIO
regulator.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
