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https://github.com/AsahiLinux/u-boot
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mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()
Make the code cleaner and drop the old-style #ifdef constructs where it is possible. Signed-off-by: Michael Walle <michael@walle.cc>
This commit is contained in:
Michael Walle
Peng Fan
parent
c7f4418c8b
commit
52faec3182
1 changed files with 63 additions and 71 deletions
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@ -109,17 +109,15 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
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if (data) {
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xfertyp |= XFERTYP_DPSEL;
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#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
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if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
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if (!IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO) &&
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cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
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cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
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xfertyp |= XFERTYP_DMAEN;
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#endif
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if (data->blocks > 1) {
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xfertyp |= XFERTYP_MSBSEL;
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xfertyp |= XFERTYP_BCEN;
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#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
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xfertyp |= XFERTYP_AC12EN;
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#endif
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if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111))
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xfertyp |= XFERTYP_AC12EN;
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}
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if (data->flags & MMC_DATA_READ)
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@ -143,7 +141,6 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
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return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
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}
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#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
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/*
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* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
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*/
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@ -206,9 +203,7 @@ static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
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}
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}
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}
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#endif
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#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
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static void esdhc_setup_watermark_level(struct fsl_esdhc_priv *priv,
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struct mmc_data *data)
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{
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@ -228,7 +223,6 @@ static void esdhc_setup_watermark_level(struct fsl_esdhc_priv *priv,
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wml_value << 16);
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}
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}
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#endif
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static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data)
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{
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@ -261,11 +255,10 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
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return -EINVAL;
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}
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#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
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esdhc_setup_watermark_level(priv, data);
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#else
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esdhc_setup_dma(priv, data);
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#endif
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if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO))
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esdhc_setup_watermark_level(priv, data);
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else
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esdhc_setup_dma(priv, data);
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/* Calculate the timeout period for data transactions */
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/*
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@ -298,14 +291,13 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
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if (timeout < 0)
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timeout = 0;
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#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
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if ((timeout == 4) || (timeout == 8) || (timeout == 12))
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if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) &&
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(timeout == 4 || timeout == 8 || timeout == 12))
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timeout++;
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#endif
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#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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timeout = 0xE;
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#endif
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if (IS_ENABLED(ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE))
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timeout = 0xE;
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esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
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return 0;
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@ -325,10 +317,9 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
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struct fsl_esdhc *regs = priv->esdhc_regs;
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unsigned long start;
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#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
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if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111) &&
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cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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return 0;
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#endif
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esdhc_write32(®s->irqstat, -1);
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@ -426,37 +417,37 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
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/* Wait until all of the blocks are transferred */
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if (data) {
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#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
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esdhc_pio_read_write(priv, data);
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#else
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flags = DATA_COMPLETE;
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if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
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cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
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flags = IRQSTAT_BRR;
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if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO)) {
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esdhc_pio_read_write(priv, data);
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} else {
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flags = DATA_COMPLETE;
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if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
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cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
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flags = IRQSTAT_BRR;
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do {
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irqstat = esdhc_read32(®s->irqstat);
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do {
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irqstat = esdhc_read32(®s->irqstat);
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if (irqstat & IRQSTAT_DTOE) {
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err = -ETIMEDOUT;
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goto out;
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}
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if (irqstat & IRQSTAT_DTOE) {
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err = -ETIMEDOUT;
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goto out;
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}
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if (irqstat & DATA_ERR) {
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err = -ECOMM;
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goto out;
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}
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} while ((irqstat & flags) != flags);
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if (irqstat & DATA_ERR) {
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err = -ECOMM;
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goto out;
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}
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} while ((irqstat & flags) != flags);
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/*
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* Need invalidate the dcache here again to avoid any
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* cache-fill during the DMA operations such as the
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* speculative pre-fetching etc.
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*/
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dma_unmap_single(priv->dma_addr,
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data->blocks * data->blocksize,
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mmc_get_dma_dir(data));
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#endif
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/*
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* Need invalidate the dcache here again to avoid any
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* cache-fill during the DMA operations such as the
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* speculative pre-fetching etc.
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*/
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dma_unmap_single(priv->dma_addr,
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data->blocks * data->blocksize,
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mmc_get_dma_dir(data));
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}
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}
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out:
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@ -735,12 +726,10 @@ static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
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u32 caps;
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caps = esdhc_read32(®s->hostcapblt);
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#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
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caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
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#endif
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#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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caps |= HOSTCAPBLT_VS33;
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#endif
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if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))
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caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
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if (IS_ENABLED(CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33))
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caps |= HOSTCAPBLT_VS33;
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if (caps & HOSTCAPBLT_VS18)
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cfg->voltages |= MMC_VDD_165_195;
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if (caps & HOSTCAPBLT_VS30)
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@ -761,19 +750,18 @@ static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
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#ifdef CONFIG_OF_LIBFDT
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__weak int esdhc_status_fixup(void *blob, const char *compat)
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{
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#ifdef CONFIG_FSL_ESDHC_PIN_MUX
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if (!hwconfig("esdhc")) {
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if (IS_ENABLED(CONFIG_FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) {
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do_fixup_by_compat(blob, compat, "status", "disabled",
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sizeof("disabled"), 1);
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return 1;
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}
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#endif
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return 0;
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}
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#ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
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static int fsl_esdhc_get_cd(struct udevice *dev);
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#if CONFIG_IS_ENABLED(DM_MMC)
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static int fsl_esdhc_get_cd(struct udevice *dev);
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static void esdhc_disable_for_no_card(void *blob)
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{
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struct udevice *dev;
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@ -792,6 +780,10 @@ static void esdhc_disable_for_no_card(void *blob)
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sizeof("disabled"), 1);
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}
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}
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#else
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static void esdhc_disable_for_no_card(void *blob)
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{
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}
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#endif
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void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
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@ -800,9 +792,10 @@ void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
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if (esdhc_status_fixup(blob, compat))
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return;
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#ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
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esdhc_disable_for_no_card(blob);
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#endif
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if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND))
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esdhc_disable_for_no_card(blob);
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do_fixup_by_compat_u32(blob, compat, "clock-frequency",
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gd->arch.sdhc_clk, 1);
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}
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@ -884,10 +877,9 @@ int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
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printf("No max bus width provided. Assume 8-bit supported.\n");
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}
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#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
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if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
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if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK))
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mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
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#endif
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mmc_cfg->ops = &esdhc_ops;
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fsl_esdhc_get_cfg_common(priv, mmc_cfg);
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@ -959,10 +951,10 @@ static int fsl_esdhc_probe(struct udevice *dev)
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if (ret)
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return ret;
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#ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
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if (!fsl_esdhc_get_cd(dev))
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if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND) &&
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!fsl_esdhc_get_cd(dev))
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esdhc_setbits32(&priv->esdhc_regs->proctl, PROCTL_VOLT_SEL);
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#endif
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return 0;
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}
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