[backport from linux commit bedcf9d1dcf88ed38731f0ac9620e5a421e1e9d6]
Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's rename "video_pll1" to
"video_pll" to be consistent with the RM and avoid misunderstandings.
No functional changes intended.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-3-dario.binacchi@amarulasolutions.com
[backport from linux commit a429c60baefd95ab43a2ce7f25d5b2d7a2e431df]
The IMX8MN platform does not have any video processing unit (VPU), and
indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there
is no occurrence of its pll. From an analysis of the code and the RM
itself, I think vpu pll is used instead of m7 alternate pll, probably
for copy and paste of code taken from modules of similar architectures.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-2-dario.binacchi@amarulasolutions.com
Tracing is typically enabled by the time driver model starts up, so there
is no point in adding a 'notrace' to the timer-init function. However,
once the driver model timer is enabled, we do need to be able to access
the timer's private data when reading the timer, so add it to the core
function needed for that.
Update the function's documentation while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
When dropping the unused fotg210 gadget driver a leading 0 was
introduced to the next line, drop it.
Fixes: e9b4678bc7 ("usb: Drop unused fotg210 gadget")
Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch fixes the mpc8xx SPI driver:
- A stub callbacks for mode and speed,
- Use chip selects defined as GPIOs,
- Write proper value to disable relocation, other it fails on mpc885,
- Don't modify ports setup, ports can be different from one board to
another and are already set by board_early_init_r().
This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
Ports A, C and D are 16 bits ports.
Ports B and E are 32 bits ports.
The "compatible" is used to determine each port type.
This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
Register mii_bus with read and write callbacks to allow the 'mii'
command to work. Use a timeout of 10 ms to wait for the R/W
operations to complete.
Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
Replace 'phys_addr_t iobase' with 'struct ftmac100 *ftmac100' in
struct ftmac100_data. It allows to remove casting in a number of places.
Since priv->iobase is phys_addr_t, use phys_to_virt() to make
a pointer from it.
Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
So it will be named similarly to the related ftgmac100 driver.
The old name 'nds32_mac' is not referred to anywhere in U-Boot.
Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Bootmenu requires an input device with arrows and enter key.
A common smartphone luckily has power, volume up/down buttons,
which may be used for controlling bootmenu.
To use driver, add 'button-kbd' to stdin.
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Linux event code must be used in input devices, using buttons.
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
GPIO button driver requires direction functions to probe
button gpio. Those functions are blank, since pwrkey is not
really gpio, and don't support direction settings.
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Add support for Qualcomm I2C QUP driver which is inspired from
corresponding driver in Linux: drivers/i2c/busses/i2c-qup.c.
Currently this driver only support FIFO polling mode which is sufficient
to support devices like eeprom, rtc etc.
Co-developed-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
The Qualcom ETHQOS hardware supports an RGMII macro which needs to be
configured according to following link speeds:
- SPEED_1000
- SPEED_100
- SPEED_10
So add a corresponding glue driver to configure RGMII macro.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The GMAC controller on QCS404 SoC (support added by upcoming patch) fails
to work with maximum tx/rx_fifo_sz supported by the hardware (16K). So
allow platforms to override FIFO size using corresponding DT node
properties.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_ATMEL_PIO4 defined in Kconfig
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_OF_BOARD defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_FASTBOOT_FLASH_NAND defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
This converts 5 usages of this option to the non-SPL form, since there is
no SPL_FASTBOOT_FLASH_MMC defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_ARCH_VERSAL defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_DISPLAY_AER_BRIEF defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_ZYNQMP_FIRMWARE defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 4 usages of this option to the non-SPL form, since there is
no SPL_XEN_SERIAL defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_VIDEO_BPP32 defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_VIDEO_BPP16 defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_USB_MUSB_HOST defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_TPM_RNG defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_SUPPORT_EMMC_RPMB defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This converts 12 usages of this option to the non-SPL form, since there is
no SPL_SANDBOX_CLK_CCF defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_SANDBOX defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_RENESAS_SDHI defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 6 usages of this option to the non-SPL form, since there is
no SPL_IMX_MODULE_FUSE defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_HW_WATCHDOG defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_FASTBOOT_MMC_USER_SUPPORT defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_FASTBOOT_FLASH defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_DEBUG_UART_ZYNQ defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 7 usages of this option to the non-SPL form, since there is
no SPL_CMD_CLK defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_A003399_NOR_WORKAROUND defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_MMC_QUIRKS defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This is not used and appears to be associated with the faraday board which
has been removed. Drop the driver and Kconfig options.
Signed-off-by: Simon Glass <sjg@chromium.org>
These are not used. Drop the drivers and Kconfig option. Also drop an
old declaration in the netdev.h header.
Signed-off-by: Simon Glass <sjg@chromium.org>
The SPL_TPL part is in the wrong place. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 71d4393f84 ("sysreset: Add Atmel/Microchip sysreset driver")
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
This is not used since this commit:
76386d6195 arm: Remove cm_t35 board
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <sjg@chromium.org>
These drivers are not used and have not been converted to driver model.
Drop them and references to the non-existent CONFIG options they use.
Signed-off-by: Simon Glass <sjg@chromium.org>
This driver is not used and has lain unconverted since:
fc47cf9d05 arm: exynos: i2c: Convert exynos boards to use DM_I2C
Drop it and the entire mfd directory, since there is nothing left.
Signed-off-by: Simon Glass <sjg@chromium.org>
This driver and bat_trats2 are not used. Drop them and the entire battery
directory, since there is nothing left.
Signed-off-by: Simon Glass <sjg@chromium.org>
This option does not exist, so the Makefile rule does nothing. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This is not used since this commit:
570c3dcfc1 arm: Remove spear600 boards and the rest of SPEAr support
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
This is not used since this commit:
8d1e3cb140 powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
This is not used since this commit:
7458f18e5c ppc: Remove MPC8313ERDB boards
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is not used since this commit:
3cf02f5ffa imx6: remove not longer supported aristainetos boards
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <sjg@chromium.org>
The KONA and KONA_GPIO options don't exist anymore, since this commit:
0f6807e77b arm: Remove bcm28155_ap board
Drop the dead code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a bootdev device for qfw so that it can be used with standard boot.
This simply checks for the correct method and then does the read. Most of
the other logic is handed in a new bootmeth driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present virtio tries to attach QEMU services to a bootdev device, which
cannot work. Add a check for this.
Also use bootdev_setup_sibling_blk() to create the bootdev device, since
it allows the correct name to be used and bootdev_get_sibling_blk() to
work as expected.
The bootdev is not created on sandbox since it does have a real virtio
device and it is not possible to read blocks.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: a60f7a3e35 ("bootstd: Add a virtio bootdev")
Reported-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Added tidss video driver support which enables display
on oldi panel using AM62x, it creates a simple pipeline
framebuffer==>vidl1==>ovr1==>vp1==>oldi_panel and
calculates clock rates for panel from panel node in
device tree.
To compile TIDSS when user sets CONFIG_VIDEO_TIDSS
add rule in Makefile. Include tidss folder location
in Kconfig.
TIDSS is ported from linux kernel version 5.10.145
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
This patch updates the necessary Kconfigs to make simple panel
driver independent of backlight driver and compiling backlight
related code in simple-panel driver conditionally to when user
has set CONFIG_BACKLIGHT.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
ofnode_decode_display_timing supports reading timing parameters from
subnode of display-timings node, for displays supporting multiple
resolution, in case if a display supports single resolution, it fails
reading directly from display-timings node, to support it
ofnode_decode_panel_timing is added.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The commit 82f7b869f5 ("video: Drop CONFIG_AM335X_LCD") removed not
only the LCD legacy implementation but also the code with driver model
support. The patch restores the code with driver model support.
Fixes: 82f7b869f5 ("video: Drop CONFIG_AM335X_LCD")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Prevent a NULL pointer dereference in the probe path by checking the
return valud of dev_read_addr_ptr() against NULL.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Remove the instances in which we have multiple blank lines.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
There were some cases in which the function parameters were not aligned
to the open paranthesis. Fix those instances.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Remove all the explicit casts from the void* returned by calloc.
With this we also improve a bit the length of those lines and there is
no need to split the assignment.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The fsl-mc driver printed debug information which used the 0x prefix for
decimal values. This only confuses anyone looking through the log.
Because of this, just remove the prefix and use the "DPXY.<id>" notation
which is the standard one for the DPAA2 objects.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The break statement is just after a goto statement, thus it will not get
executed. Just remove it.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The cur_ptr variable is set to the start of the log buffer but then it's
not used. Just remove the assignment altogether.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Add a DSA driver for the MV88E6xxx compatible Ethernet switches.
Cc: Marek Behún <marek.behun@nic.cz>
Cc: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Add support for DM_MDIO by registering a UCLASS_MDIO driver and
attempting to use it. This is necessary if wanting to use a DSA
driver for example hanging off of the FEC MAC.
Care is taken to fallback to non DM_MDIO mii bus as several boards define
DM_MDIO without having the proper device-tree configuration necessary
such as an mdio subnode, a phy-mode prop, and either a valid phy-handle
prop or fixed-phy subnode which will cause dm_eth_phy_connect() to fail.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Remove the unnecessary xmit and recv functions.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Add timer support for T20/T30/T114/T124 and T210 based devices.
Driver is based on DM, has device tree support and can be
used on SPL and early boot stage.
Arm64 Tegra (apart T210) according to comment in tegra-common.h use
architected timer.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
Enum clock_osc_freq was designed to use only with T20.
This patch remaps it to use additional frequencies, added in
T30+ SoC while maintaining backwards compatibility with T20.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Tested-by: Thierry Reding <treding@nvidia.com> # T30, T124, T210
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
The current set of U-Boot upstream R-Car Gen3 DTs all contain generic
"renesas,etheravb-rcar-gen3" compatible strings, drop the SoC specific
compatible string support from U-Boot to reduce size and duplication.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but
similar enough to reuse code. Introduce a new CPG library, factor out
the SD clock and RPC clock handling and hook them to the generic Gen3
CPG driver so we have an equal state.
Based on Linux commit [1] and [2] by Wolfram Sang
[1] 8bb67d87346a ("clk: renesas: rcar-gen3: Factor out CPG library")
[2] 6f21d145b90f ("clk: renesas: cpg-lib: Move RPC clock registration to
the library")
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Add rcar_clk_* prefix to all functions
- Rebase on changes to
clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
- Use u32_encode_bits/GENMASK bitfield ops
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. Hence, new clock types are introduced
respectively.
Based on Linux commit 381081ffc294 ("clk: renesas: r8a77970: Add SD0H/SD0
clocks for SDHI") by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead
- Do not modify r8a77970-cpg-mssr.c much, drop enum r8a77970_clk_types
which is now part of common clock types in rcar-gen3-cpg.h instead
The old SD handling code was huge and could not handle all the details
which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to
another design. Have SDnH a separate clock, use the existing divider
clocks and move the errata handling from the clock driver to the SDHI
driver where it belongs.
Based on Linux series by Wolfram Sang, commit bb6d3fa98a41 ("clk:
renesas: rcar-gen3: Switch to new SD clock handling") and commit
e5f7e81ee430a ("mmc: renesas_sdhi: Parse DT for SDnH")
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Add rcar_clk_* prefix to all functions
- Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead
- Use DIV_ROUND_CLOSEST, else if parent clock = 199999992 and
rate = 200000000, the divider would be 0 and table lookup
would fail.
- Turn rcar_clk_get_table_val into signed integer, so it can
return 0 as a valid value and negative values as errors.
- Make the code operate on correct clock and add comment
which explains the reasoning behind it.
- Rebase on changes to
clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car
E3, but uses a different pre-divider for the PLL0 parent. Add a new
macro to describe it, reusing the existing clock type for R-Car E3.
As both E3/D3 RPCSRC clock divider are different from the rest of R-Car
Gen3, keep the original implementation from Linux.
Based on Linux commit 40745482eec8 ("clk: renesas: r8a774c0: Add RPC
clocks") by Lad Prabhakar and 9d18f81b3535 ("clk: renesas: r8a77995: Add
RPC clocks") by Geert Uytterhoeven.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Add D3 tweaks
Introduce new helper function to handle clock type that uses
clk_div_table struct. Based vaguely on Linux code. Make use
of clk_div_table in RPC clocks handling.
The E3/D3 RPCSRC need to be handled differently and will be addressed in
subsequence patch.
Based on Linux commit db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC
clocks") by Sergei Shtylyov.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Squash patches to avoid adding unused code:
clk: renesas: Make use of clk_div_table in RPC clocks handling
clk: renesas: Introduce rcar_clk_get_rate64_div_table function
- Move the new code to the beginning of clk-rcar-gen3 to avoid
tables mixed with code
- Use rcar_ prefix for get_table_div function
- Get rid of custom macros, use GENMASK. Use custom field_get
implementation as the generic FIELD_GET does not support
constant mask and u32_get_bits requires higher optimization level
- Pass in the register bit mask instead of width/shift combination
- Turn rcar_clk_get_rate64_div_table into s64, as it can return -EINVAL
Replace custom local structure with matching one from clk-provider.h .
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
V3M handles SDnH differently than other Gen3 SoCs, so let's add a
separate entry for that. This will allow better SDnH handling in the
future.
Based on Linux commit 627151b4966f ("mmc: renesas_sdhi: Flag
non-standard SDnH handling for V3M") by Wolfram Sang
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
It is unnecessary, so clean it up.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # update commit message, mention ES3.0
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Support R8A77961 M3-W+ SoC.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Still uses 0x3 for now, adjust the offset value to TMPPORT3 accordingly
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Adjust HS400 calibration tables based on Linux settings
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Further filter out HS400 support on certain SoCs.
Since M3-W r1.2 does not support HS400, drop the calibration table and
rename the one for M3-W r1.3 to r8a7796_rev13_calib_table
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Early ES revisions of M3-W SoCs requires 4-tap HS400. Reflect the status
from datasheet.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Drop 'core' parameter from gen3_clk_get_rate64_pll_mul_reg() function
as it is only used in debug print. No functional change except for the
debug print, which is disabled by default.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Since commit f7b4e4c094 ("clk: renesas: Synchronize R-Car Gen3 tables
with Linux 5.12"), the custom macros for RPC clocks were dropped.
Use pre-defined offset for RPC clocks, same as what Linux does, instead
of retrieving it from the macros
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add trivial reset driver extension to the CPG clock driver. The change
turns current CPG UCLASS_CLK driver instance into an UCLASS_NOP proxy
driver, which in turn binds both generic rcar3_clk UCLASS_CLK clock
driver as well as generic rcar_rst UCLASS_RESET reset driver to the
CPG DT node. This way, any other drivers which use the 'reset' DT
property can now obtain valid reset handle backed by a reset driver.
The clock tables have been updated to represent the CPG driver and only
implement the generic CPG proxy driver bind call, which binds the clock
and reset drivers.
The DM_RESET is now enabled for all R-Car Gen3 platforms.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add support for the R-Car M3-W+ (R8A77961) SoC.
R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), which allows for
both SoCs to share a driver.
Based on Linux commit 2ba738d56db4 ("clk: renesas: r8a7796: Add R8A77961
CPG/MSSR support")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Rename CONFIG_CLK_R8A7796 for R-Car M3-W (R8A77960) to
CONFIG_CLK_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961),
which will use CONFIG_CLK_R8A77961.
Based on Linux commit 92d1ebae9abf ("clk: renesas: Rename CLK_R8A7796
to CLK_R8A77960")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A779A0 V3U clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Rename CLK_TYPE_R8A779A0_ to CLK_TYPE_GEN4_ to match the new
clock tables. Add CLK_TYPE_GEN4_SD, CLK_TYPE_GEN4_RPC and
CLK_TYPE_GEN4_RPCD2 macros and handling into Gen3 CPG core.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Currently, SDnH is handled together with SDn. This caused lots of
problems, so we want SDnH as a separate clock. Introduce a dummy SDnH
type here which creates a fixed-factor clock with factor 1. That allows
us to convert the per-SoC CPG drivers while keeping the old behaviour
for now. A later patch then will add the proper functionality.
Based on Linux series by Wolfram Sang:
commit a31cf51bf6b4b ("clk: renesas: rcar-gen3: Add dummy SDnH clock"),
commit 1abd04480866c ("clk: renesas: rcar-gen3: Add SDnH clock"),
commit 63494b6f98f26 ("clk: renesas: r8a779a0: Add SDnH clock to V3U")
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Switch to gen3_clk_get_rate64
R-Car M3-W+ (R8A77961) is pin compatible with R-Car M3-W (R8A77960),
which allows for both SoCs to share a driver.
Based on Linux commit 708c69e9eacc ("pinctrl: sh-pfc: r8a7796: Add
R8A77961 PFC support") and 74ce7a8044b0 ("pinctrl: renesas: r8a7796:
Optimize pinctrl image size for R8A774A1")
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Note that the Kconfig option name has been updated to match the
Linux kernel Kconfig option name, from PINCTRL_PFC_R8A7796 to
PINCTRL_PFC_R8A77960 .
Also note that a new Kconfig option has been added to enable support
for R8A77961 M3-W+ , the Kconfig option name is PINCTRL_PFC_R8A77961 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A7795 H3 PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Note that the Kconfig option name has been updated to match the
Linux kernel Kconfig option name, from PINCTRL_PFC_R8A7795 to
PINCTRL_PFC_R8A77951 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A7791 M2-W and R8A7793 M2-N PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car PFC core with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Parts picked from
pinctrl: renesas: Synchronize R-Car Gen2/Gen3 tables with Linux 5.18.3
- Add pin groups for the green and high8 subsets of the Video IN pins
- Add MediaLB pins
- Add bias support for various SoCs
- Share more pin group data, to reduce size and ease review
- Miscellaneous cleanups, fixes and improvements.
This contains port of Linux kernel commit
6210905586ae ("pinctrl: renesas: Add shorthand for reserved register fields")
to handle negative entries in GROUP() macros correctly.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car device trees with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
The following script has been used for the synchronization:
$ for i in $(cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) ; do
if [ -e /linux-2.6/arch/arm64/boot/dts/renesas/$i ] ; then
cp /linux-2.6/arch/arm64/boot/dts/renesas/$i arch/arm/dts/ ;
elif [ -e /linux-2.6/arch/arm/boot/dts/$i ] ; then
cp /linux-2.6/arch/arm/boot/dts/$i arch/arm/dts/
else
echo "NOT FOUND: $i"
fi
done
$ git add $( ( cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) | tr " " "\n" | sed 's@^@arch/arm/dts/@g' )
Move the include/dt-bindings/{clk,clock}/versaclock.h header used by
the renesas boards to match Linux 6.1.y as well.
Keep arch/arm/dts/r8a774c0-u-boot.dtsi sdhi3 node as it is now used
by the arch/arm/dts/r8a774c0-cat874.dts board.
Pick s@spi-flash@flash@ change in arch/arm/dts/r8a779a0-falcon-u-boot.dts
from "ARM: dts: Synchronize R-Car V3U DTs with Linux 5.18.3" .
Adjust R8A77990 Ebisu CONFIG_SYS_MMC_ENV_DEV from 2 to 0 to reflect
the card enumeration in ebisu.dtsi /aliases DT node .
Adjust R8A7795 and R8A7796 ULCB CONFIG_SYS_MMC_ENV_DEV from 1 to 0 to
reflect the card enumeration in ulcb.dtsi /aliases DT node .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> # r8a779a0-falcon-u-boot.dts
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> # r8a779a0-falcon-u-boot.dts
Unlike in Linux, -supply is not automatically appended to regulator
requests. Add it.
Fixes: 2645bc0e12 ("arm: layerscape: Add sfp driver")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
SCFW has fixed a overflow issue in sc_rm_is_pad_owned API. This
requires u-boot to update API implementation, since it will cause
compatible issue. Otherwise all pad checking will have problem and
cause pad setting not continue.
Due to the compatible issue, the new u-boot only works with new
SCFW (API version: 1.21 and later).
old scfw + old u-boot: API overflow issue
old scfw + new u-boot, or new scfw + old u-boot: API compatible issue
new scfw + new u-boot: Working
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Jason Liu <Jason.hui.liu@nxp.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Add support for HS400 in mode2timing array.
Add a quirk for Versal NET platform to indicate that HS400 is supported
through bit63 of capability register.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
HS400 is indicated in bit63 of capability register in few IP's.
Add a quirk to check this and add HS400 to host capabilities.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Check if the low level driver supports config_dll callback function and
call it if it does. Call with dll disable before calling set_clock and
with dll enable after it.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Add support for eMMC 5.1 for Versal NET platform
- Add new compatible string(xlnx,versal-net-5.1-emmc).
- Add CONFIG_ARCH_VERSAL_NET condition wherever required.
- Add DLL and Delay Chain mode support
- Add input and output tap delays for eMMC.
- Add Strobe select tap for HS400 mode.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Add more capable "bkops" command which allows enabling and disabling both
manual and automatic bkops. The existing 'mmc bkops-enable' subcommand is
poorly named to cover all the possibilities, hence the new-ish subcommand.
Note that both commands are wrappers around the same common code.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Instead of waiting for empty FIFO condition before writing a
character, wait for non-full FIFO condition.
This helps in saving several tens of milliseconds during boot
(depending verbosity).
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Tested-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Fabio Estevam <festevam@denx.de>
The u-boot console may show some corrupted characters when
printing in board_init() due to reset or baudrate change
of the UART (probe) before the TX FIFO has been completely
drained.
To fix this issue, and in case UART is still running, we now
try to flush the FIFO before proceeding to UART reinitialization.
For this we're waiting for Transmitter Complete bit, indicating
that the FIFO and the shift register are empty.
flushing has a 4ms timeout guard, which is normally more than
enough to consume the FIFO @ low baudrate (9600bps).
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Tested-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
The default configuration of the PMIC behavior makes the PMIC
power cycle most regulators on WDOG_B assertion. This power
cycling causes the memory contents of OCRAM to be lost.
Some systems neeeds some memory that survives reset and
reboot, therefore this patch is created.
The implementation is taken almost verbatim from Linux commit
2364a64d0673f ("regulator: pca9450: Make warm reset on WDOG_B assertion")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The DDR calibration tool for i.MX8M currently produces 3732 MTps rate in
lpddr4_timing.c , while the PHY code expects 3733 MTps rate. Support both
variants to avoid surprises where the system fails to boot.
Signed-off-by: Marek Vasut <marex@denx.de>
When a system has multiple XHCI controllers, some of the
properties described in the descriptor of the root hub (such as
the number of ports) might differ between controllers. Fix this
by switching from a single global hub descriptor to a hub
descriptor per controller.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Marek Vasut <marex@denx.de>
This driver supports the PCIe controller on the Apple M1 and
M2 SoCs. The code is adapted from the Linux driver.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Systems such as Apple's M1 and M2 SoCs may have separate IOMMUs
for each PCIe root port. In this case the right IOMMU for a
PCI device behind a particular root port is described by an
"iommu-map" property in the device tree. Parse this property
and use it to find the right IOMMU device for PCI devices.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
An XHCI controller that sits behind an IOMMU needs to map and unmap
its memory buffers to do DMA. Implement this by inroducing new
xhci_dma_map() and xhci_dma_unmap() helper functions. The
xhci_dma_map() function replaces the existing xhci_virt_to_bus()
function in the sense that it returns the bus address in the case
of simple address translation in the absence of an IOMMU. The
xhci_bus_to_virt() function is eliminated by storing the CPU
address of the allocated scratchpad memory in struct xhci_ctrl.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Implement translation table support for all the variations of
Apple's DART IOMMU that can be found on Apple's M1 and M2 SoCs.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Test that the map and unmap operations work for devices that
have DMA translated by an IOMMU and devices that don't have
DMA translated by an IOMMU.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
In order to support IOMMUs in non-bypass mode we need device ops
to map and unmap DMA memory. The map operation enters a mapping
for a region specified by CPU address and size into the translation
table of the IOMMU and returns a DMA address suitable for
programming the device to do DMA. The unmap operation removes
this mapping from the translation table of the IOMMU.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
There are no SPL/TPL variants of CONFIG_CLK_EXYNOS and
CONFIG_ARCH_APPLE, so switch from CONFIG_IS_ENABLED to
IS_ENABLED.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Don't define an empty version for pinconfig_post_bind(). Just guard the
call and let the linker garbage collection do the rest. This way, we
also don't have to do any guesswork.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Marek Vasut <marex@denx.de>
If CONFIG_PINCTRL_FULL is enabled, never fall back to the simple
implementation. pinctrl_select_state() is called for each device and it
is expected to fail. A fallback to the simple imeplementation doesn't
make much sense.
To keep the return code consistent, we need to change the -EINVAL (which
was ignored before) to -ENOSYS.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
makefile:
- Add multi_dtb_fit dependency
clk:
- Handle error cases
microblaze:
- Disable falcon mode and cleanup code around
xilinx:
- Enable regular expression matching in board_fit_config_name_match()
- Fix FRU handling for 0xC1 format
- Fix Xilinx legacy format eeprom parsing
zynqmp:
- Some DT updates/cleanups
- Fix IDcode for xck24
- Remove empty mini config files
- Add support for k24
versal:
- Remove empty mini config files
versal_net:
- Setup timer when runs in EL3
- Build u-boot.elf for mini configurations
zynq-gem:
- Add support for new compatible strings
- Remove support for Avnet Ultrazedev SOM
- Handle SGMII with PCS phy
spi:
- Add support for gigadevice parts
misc:
- Remove CONFIG_TARGET_VENUS ifdef
- Add missing headers to remove sparse warnings
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Merge tag 'xilinx-for-v2023.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx chnages for v2023.04-rc1
makefile:
- Add multi_dtb_fit dependency
clk:
- Handle error cases
microblaze:
- Disable falcon mode and cleanup code around
xilinx:
- Enable regular expression matching in board_fit_config_name_match()
- Fix FRU handling for 0xC1 format
- Fix Xilinx legacy format eeprom parsing
zynqmp:
- Some DT updates/cleanups
- Fix IDcode for xck24
- Remove empty mini config files
- Add support for k24
versal:
- Remove empty mini config files
versal_net:
- Setup timer when runs in EL3
- Build u-boot.elf for mini configurations
zynq-gem:
- Add support for new compatible strings
- Remove support for Avnet Ultrazedev SOM
- Handle SGMII with PCS phy
spi:
- Add support for gigadevice parts
misc:
- Remove CONFIG_TARGET_VENUS ifdef
- Add missing headers to remove sparse warnings
In our system using ZynqMP with an external SGMII PHY it's necessary
to wait for the PCS link and auto negotiation to finish before the xfer
starts. Otherwise the first packet(s) might get dropped, resulting in a
delay at the start of the ethernet transfers.
This is only done when the PHY link is already up, which is done in
phy_startup(). As waiting for the PHY link bits via pcsstatus does not
make much sense, when the link is not available in general (e.g. no
cable connected).
This patch adds the necessary code including a minimal delay of 1 ms
which fixes problems of dropped first packages.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Michal Simek <michal.simek@amd.com>
Cc: Katakam Harini <harini.katakam@amd.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Sean Anderson <sean.anderson@seco.com>
Link: https://lore.kernel.org/r/20230125070908.1343256-1-sr@denx.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
tuning_loop_counter is of char type, which is not capable of handling
the entire data range of this variable. This is pointed by below sparse
warning. Change datatype to int to fix this.
warning: comparison is always false due to limited range of data type.
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230120053617.32463-5-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
There is a unused variable ret, due to which we are getting sparse warning
as below.
warning: variable 'ret' set but not used [-Wunused-but-set-variable].
Return ret incase of error.
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230120053617.32463-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Binman positioning by ELF symbol
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Merge tag 'dm-pull-26jan23' of https://source.denx.de/u-boot/custodians/u-boot-dm
FIT improvements with split-elf, especially for Rockchip
Binman positioning by ELF symbol
Use a more accurate check for determining if the full format string will
be handled correctly, since SPL_USE_TINY_PRINTF can be disabled.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Infineon S25FS256T is 256Mbit Quad SPI NOR flash. The key features and
differences comparing to other Spansion/Cypress flash familes are:
- 4-byte address mode by factory default
- Quad mode is enabled by factory default
- Supports mixture of 128KB and 64KB sectors by OTP configuration
(this patch supports uniform 128KB only)
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Rename s25hx_t prefix to s25 so that the single set of fixup hooks can
support all other S25 families.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Acked-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Fix the issue where some flash chips like cypress S25HS256T return the
value of the same register over and over in DAC mode.
For example in the TI K3-AM62x Processors refer [0] Technical Reference
Manual there is a layer of digital logic in front of the QSPI/OSPI
Drive when used in DAC mode. This is part of the Flash Subsystem (FSS)
which provides access to external Flash devices.
The FSS0_0_SYSCONFIG Register (Offset = 4h) has a BIT Field for
OSPI_32B_DISABLE_MODE which has a Reset value = 0. This means, OSPI 32bit
mode enabled by default.
Thus, by default controller operates in 32 bit mode causing it to always
align all data to 4 bytes from a 4byte aligned address. In some flash
chips like cypress for example if we try to read some regs in DAC mode
then it keeps sending the value of the first register that was requested
and inorder to read the next reg, we have to stop and re-initiate a new
transaction.
This causes wrong register values to be read than what is desired when
registers are read in DAC mode. Hence if the data.nbytes is very less
then prefer STIG mode for such small reads.
[0] https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf
Tested-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
[jagan: add tab space for comments]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Setup the Addr bit field while issuing register reads in STIG mode. This
is needed for example flashes like cypress define in their transaction
table that to read any register there is 1 cmd byte and a few more address
bytes trailing the cmd byte. Absence of addr bytes will obviously fail
to read correct data from flash register that maybe requested by flash
driver because the controller doesn't even specify which address of the
flash register the read is being requested from.
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cypress defines two flavors of configuration registers, volatile and
non volatile, and both use the same bit fields. Rename the bitfields in
the configuration registers so that they can be used for both flavors.
Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Introduce Socionext F_OSPI controller driver. This controller is used to
communicate with slave devices such as SPI flash memories. It supports
4 slave devices and up to 8-bit wide bus, but supports master mode only.
This driver uses spi-mem framework for SPI flash memory access, and
can only operate indirect access mode and single data rate mode.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Use log_warning() instead of printf() to print out driver information
Signed-off-by: Pengfei Fan <fanpengfei1@eswincomputing.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Fix some typos in spi drivers
Signed-off-by: Pengfei Fan <fanpengfei1@eswincomputing.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
up to the commit "mv_ddr: a3700: Use the right size for memset to not overflow"
d5acc10c287e40cc2feeb28710b92e45c93c702c
This patch was created by following steps:
1. Replace all a38x files in U-Boot tree by files from upstream github
Marvell mv-ddr-marvell repository.
2. Run following command to omit portions not relevant for a38x, ddr3, and ddr4:
files=drivers/ddr/marvell/a38x/*
unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_APN806 \
-UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \
-UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DCONFIG_ARMADA_38X -UCONFIG_ARMADA_39X \
-UCONFIG_64BIT $files
3. Manually change license to SPDX-License-Identifier
(upstream license in upstream github repository contains long license
texts and U-Boot is using just SPDX-License-Identifier.
After applying this patch, a38x, ddr3, and ddr4 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.
The only change in this patch are:
1. Some fixes with include files.
2. Some function return and basic type defines changes in
mv_ddr_plat.c (to correct Marvell bug).
3. Remove of dead code in newly copied files (as a result of the
filter script stripping out everything other than a38x, dd3, and ddr4).
Reference:
"ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository"
107c3391b9
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This contains some fixes, and the first bunch of some clean up patches
to get rid of legacy GPIO and PMIC code.
Highlight is the DM AXP PMIC driver, which is required to convert some
drivers over to use DM regulators, and also is required to get rid
of some less optimal PMIC setup code in Trusted Firmware. This isn't
enabled by any defconfig yet, but can be enabled manually and works. For
the full glory some patches are still missing, and this requires more
testing, which would be simpler if the core code is upstream.
We need extensions to be set up before we start trying to boot any of the
bootdevs. Add a new priority before all the others for tht sort of thing.
Also add a 'none' option, so that the first one is not 0.
While we are here, comment enum bootdev_prio_t fully and expand the test
for the 'bootdev hunt' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a bootdev for SPI flash so that these devices can be used with
standard boot. It only supports loading a script.
Add a special case for the label, since we want to use "spi", not
"spi_flash".
Enable the new bootdev on sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
The controller indicates the number of ports but also has a port map
which specifies which ports are actually valid. Make use of this to
avoid trying to send commands to an invalid port.
This avoids a crash on some controllers.
Signed-off-by: Simon Glass <sjg@chromium.org>
The test code for virtio is fairly simplistic and does not actually create
a block device. Add a way to specify the device type in the device tree.
Add a block device so that we can do more testing.
Signed-off-by: Simon Glass <sjg@chromium.org>
This has a special meaning in driver model. There is clearly a device, so
it does not make sense to return this error code. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present this only unbinds block devices of a certain type. But SCSI
device can have different types of children, including bootdevs.
Unbind all children so tht everything is clean and ready for a new scan.
Signed-off-by: Simon Glass <sjg@chromium.org>
