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pinctrl: renesas: Synchronize R8A77980 V3H PFC tables with Linux 6.1.7
Synchronize R-Car R8A77980 V3H PFC tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
84d7588cc6
commit
3bf4933555
1 changed files with 302 additions and 213 deletions
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@ -21,12 +21,23 @@
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#include "sh_pfc.h"
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#define CPU_ALL_GP(fn, sfx) \
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PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_28(1, fn, sfx), \
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PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_25(4, fn, sfx), \
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PORT_GP_15(5, fn, sfx)
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PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
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#define CPU_ALL_NOGP(fn) \
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PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(DCUTRST_N, "DCUTRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
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/*
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* F_() : just information
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@ -88,7 +99,7 @@
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#define GPSR1_0 F_(IRQ0, IP2_27_24)
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/* GPSR2 */
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#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
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#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
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#define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
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#define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
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#define GPSR2_26 F_(SDA3, IP10_7_4)
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@ -253,11 +264,11 @@
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#define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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@ -269,9 +280,6 @@
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#define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP10_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP10_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP10_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define PINMUX_GPSR \
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\
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@ -331,9 +339,9 @@ FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \
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FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \
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FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \
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FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \
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FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 \
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FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 \
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FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28
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FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 \
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FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 \
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FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28
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/* MOD_SEL0 */ /* 0 */ /* 1 */
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#define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
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@ -832,8 +840,17 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N),
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};
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/*
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* Pins not associated with a GPIO port.
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*/
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enum {
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GP_ASSIGN_LAST(),
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NOGP_ALL(),
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};
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static const struct sh_pfc_pin pinmux_pins[] = {
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PINMUX_GPIO_GP_ALL(),
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PINMUX_NOGP_ALL(),
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};
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/* - AVB -------------------------------------------------------------------- */
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@ -1347,30 +1364,14 @@ static const unsigned int intc_ex_irq5_mux[] = {
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};
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/* - MMC -------------------------------------------------------------------- */
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static const unsigned int mmc_data1_pins[] = {
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/* MMC_D0 */
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RCAR_GP_PIN(3, 8),
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};
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static const unsigned int mmc_data1_mux[] = {
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MMC_D0_MARK,
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};
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static const unsigned int mmc_data4_pins[] = {
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/* MMC_D[0:3] */
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RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
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RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
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};
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static const unsigned int mmc_data4_mux[] = {
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MMC_D0_MARK, MMC_D1_MARK,
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MMC_D2_MARK, MMC_D3_MARK,
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};
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static const unsigned int mmc_data8_pins[] = {
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static const unsigned int mmc_data_pins[] = {
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/* MMC_D[0:7] */
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RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
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RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
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RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
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RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
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};
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static const unsigned int mmc_data8_mux[] = {
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static const unsigned int mmc_data_mux[] = {
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MMC_D0_MARK, MMC_D1_MARK,
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MMC_D2_MARK, MMC_D3_MARK,
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MMC_D4_MARK, MMC_D5_MARK,
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@ -1669,22 +1670,6 @@ static const unsigned int qspi0_ctrl_pins[] = {
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static const unsigned int qspi0_ctrl_mux[] = {
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QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
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};
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static const unsigned int qspi0_data2_pins[] = {
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/* MOSI_IO0, MISO_IO1 */
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RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
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};
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static const unsigned int qspi0_data2_mux[] = {
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QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
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};
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static const unsigned int qspi0_data4_pins[] = {
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/* MOSI_IO0, MISO_IO1, IO2, IO3 */
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RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
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RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
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};
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static const unsigned int qspi0_data4_mux[] = {
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QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
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QSPI0_IO2_MARK, QSPI0_IO3_MARK
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};
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/* - QSPI1 ------------------------------------------------------------------ */
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static const unsigned int qspi1_ctrl_pins[] = {
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@ -1694,36 +1679,14 @@ static const unsigned int qspi1_ctrl_pins[] = {
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static const unsigned int qspi1_ctrl_mux[] = {
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QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
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};
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static const unsigned int qspi1_data2_pins[] = {
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/* MOSI_IO0, MISO_IO1 */
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RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
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};
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static const unsigned int qspi1_data2_mux[] = {
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QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
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};
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static const unsigned int qspi1_data4_pins[] = {
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/* MOSI_IO0, MISO_IO1, IO2, IO3 */
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RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
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RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
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};
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static const unsigned int qspi1_data4_mux[] = {
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QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
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QSPI1_IO2_MARK, QSPI1_IO3_MARK
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};
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/* - RPC -------------------------------------------------------------------- */
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static const unsigned int rpc_clk1_pins[] = {
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static const unsigned int rpc_clk_pins[] = {
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/* Octal-SPI flash: C/SCLK */
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RCAR_GP_PIN(5, 0),
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};
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static const unsigned int rpc_clk1_mux[] = {
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QSPI0_SPCLK_MARK,
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};
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static const unsigned int rpc_clk2_pins[] = {
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/* HyperFlash: CK, CK# */
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RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
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};
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static const unsigned int rpc_clk2_mux[] = {
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static const unsigned int rpc_clk_mux[] = {
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QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
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};
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static const unsigned int rpc_ctrl_pins[] = {
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@ -1945,37 +1908,33 @@ static const unsigned int tpu_to3_mux[] = {
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};
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/* - VIN0 ------------------------------------------------------------------- */
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static const union vin_data vin0_data_pins = {
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.data24 = {
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RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
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RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
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RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
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RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
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RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
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RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
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RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
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RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
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RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
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RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
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RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
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RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
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},
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static const unsigned int vin0_data_pins[] = {
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RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
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RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
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RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
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RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
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RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
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RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
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RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
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RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
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RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
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RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
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RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
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RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
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};
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static const union vin_data vin0_data_mux = {
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.data24 = {
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VI0_DATA0_MARK, VI0_DATA1_MARK,
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VI0_DATA2_MARK, VI0_DATA3_MARK,
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VI0_DATA4_MARK, VI0_DATA5_MARK,
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VI0_DATA6_MARK, VI0_DATA7_MARK,
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VI0_DATA8_MARK, VI0_DATA9_MARK,
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VI0_DATA10_MARK, VI0_DATA11_MARK,
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VI0_DATA12_MARK, VI0_DATA13_MARK,
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VI0_DATA14_MARK, VI0_DATA15_MARK,
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VI0_DATA16_MARK, VI0_DATA17_MARK,
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VI0_DATA18_MARK, VI0_DATA19_MARK,
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VI0_DATA20_MARK, VI0_DATA21_MARK,
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VI0_DATA22_MARK, VI0_DATA23_MARK,
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},
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static const unsigned int vin0_data_mux[] = {
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VI0_DATA0_MARK, VI0_DATA1_MARK,
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VI0_DATA2_MARK, VI0_DATA3_MARK,
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VI0_DATA4_MARK, VI0_DATA5_MARK,
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VI0_DATA6_MARK, VI0_DATA7_MARK,
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VI0_DATA8_MARK, VI0_DATA9_MARK,
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VI0_DATA10_MARK, VI0_DATA11_MARK,
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VI0_DATA12_MARK, VI0_DATA13_MARK,
|
||||
VI0_DATA14_MARK, VI0_DATA15_MARK,
|
||||
VI0_DATA16_MARK, VI0_DATA17_MARK,
|
||||
VI0_DATA18_MARK, VI0_DATA19_MARK,
|
||||
VI0_DATA20_MARK, VI0_DATA21_MARK,
|
||||
VI0_DATA22_MARK, VI0_DATA23_MARK,
|
||||
};
|
||||
static const unsigned int vin0_data18_pins[] = {
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
|
|
@ -2029,25 +1988,21 @@ static const unsigned int vin0_clk_mux[] = {
|
|||
};
|
||||
|
||||
/* - VIN1 ------------------------------------------------------------------- */
|
||||
static const union vin_data12 vin1_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
|
||||
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
|
||||
},
|
||||
static const unsigned int vin1_data_pins[] = {
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
|
||||
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
|
||||
};
|
||||
static const union vin_data12 vin1_data_mux = {
|
||||
.data12 = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
},
|
||||
static const unsigned int vin1_data_mux[] = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin1_sync_pins[] = {
|
||||
/* VI1_VSYNC#, VI1_HSYNC# */
|
||||
|
|
@ -2138,9 +2093,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(intc_ex_irq3),
|
||||
SH_PFC_PIN_GROUP(intc_ex_irq4),
|
||||
SH_PFC_PIN_GROUP(intc_ex_irq5),
|
||||
SH_PFC_PIN_GROUP(mmc_data1),
|
||||
SH_PFC_PIN_GROUP(mmc_data4),
|
||||
SH_PFC_PIN_GROUP(mmc_data8),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(mmc_cd),
|
||||
SH_PFC_PIN_GROUP(mmc_wp),
|
||||
|
|
@ -2180,13 +2135,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(pwm4_a),
|
||||
SH_PFC_PIN_GROUP(pwm4_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
SH_PFC_PIN_GROUP(rpc_clk1),
|
||||
SH_PFC_PIN_GROUP(rpc_clk2),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
|
||||
BUS_DATA_PIN_GROUP(rpc_clk, 1),
|
||||
BUS_DATA_PIN_GROUP(rpc_clk, 2),
|
||||
SH_PFC_PIN_GROUP(rpc_ctrl),
|
||||
SH_PFC_PIN_GROUP(rpc_data),
|
||||
SH_PFC_PIN_GROUP(rpc_reset),
|
||||
|
|
@ -2215,20 +2170,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(tpu_to1),
|
||||
SH_PFC_PIN_GROUP(tpu_to2),
|
||||
SH_PFC_PIN_GROUP(tpu_to3),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 16),
|
||||
SH_PFC_PIN_GROUP(vin0_data18),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 20),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 24),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 20),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 24),
|
||||
SH_PFC_PIN_GROUP(vin0_sync),
|
||||
SH_PFC_PIN_GROUP(vin0_field),
|
||||
SH_PFC_PIN_GROUP(vin0_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin0_clk),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 12),
|
||||
SH_PFC_PIN_GROUP(vin1_sync),
|
||||
SH_PFC_PIN_GROUP(vin1_field),
|
||||
SH_PFC_PIN_GROUP(vin1_clkenb),
|
||||
|
|
@ -2551,17 +2506,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
#define F_(x, y) FN_##y
|
||||
#define FM(x) FN_##x
|
||||
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
|
||||
GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP0_31_22 RESERVED */
|
||||
GP_0_21_FN, GPSR0_21,
|
||||
GP_0_20_FN, GPSR0_20,
|
||||
GP_0_19_FN, GPSR0_19,
|
||||
|
|
@ -2653,22 +2602,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_2_1_FN, GPSR2_1,
|
||||
GP_2_0_FN, GPSR2_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
|
||||
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP3_31_17 RESERVED */
|
||||
GP_3_16_FN, GPSR3_16,
|
||||
GP_3_15_FN, GPSR3_15,
|
||||
GP_3_14_FN, GPSR3_14,
|
||||
|
|
@ -2687,14 +2625,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_3_1_FN, GPSR3_1,
|
||||
GP_3_0_FN, GPSR3_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
|
||||
GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1),
|
||||
GROUP(
|
||||
/* GP4_31_25 RESERVED */
|
||||
GP_4_24_FN, GPSR4_24,
|
||||
GP_4_23_FN, GPSR4_23,
|
||||
GP_4_22_FN, GPSR4_22,
|
||||
|
|
@ -2721,24 +2657,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_4_1_FN, GPSR4_1,
|
||||
GP_4_0_FN, GPSR4_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
|
||||
GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP5_31_15 RESERVED */
|
||||
GP_5_14_FN, GPSR5_14,
|
||||
GP_5_13_FN, GPSR5_13,
|
||||
GP_5_12_FN, GPSR5_12,
|
||||
|
|
@ -2860,10 +2783,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP9_7_4
|
||||
IP9_3_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
|
||||
IP10_31_28
|
||||
IP10_27_24
|
||||
IP10_23_20
|
||||
{ PINMUX_CFG_REG_VAR("IPSR10", 0xe6060228, 32,
|
||||
GROUP(-12, 4, 4, 4, 4, 4),
|
||||
GROUP(
|
||||
/* IP10_31_20 RESERVED */
|
||||
IP10_19_16
|
||||
IP10_15_12
|
||||
IP10_11_8
|
||||
|
|
@ -2876,19 +2799,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
#define F_(x, y) x,
|
||||
#define FM(x) FN_##x,
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
|
||||
GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1),
|
||||
GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, -1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* RESERVED 31, 30, 29, 28 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 27, 26, 25, 24 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 23, 22, 21, 20 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 19, 18, 17, 16 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 15, 14, 13, 12 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 31-12 */
|
||||
MOD_SEL0_11
|
||||
MOD_SEL0_10
|
||||
MOD_SEL0_9
|
||||
|
|
@ -2897,7 +2810,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_6
|
||||
MOD_SEL0_5
|
||||
MOD_SEL0_4
|
||||
0, 0,
|
||||
/* RESERVED 3 */
|
||||
MOD_SEL0_2
|
||||
MOD_SEL0_1
|
||||
MOD_SEL0_0 ))
|
||||
|
|
@ -2922,8 +2835,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
||||
u32 *pocctrl)
|
||||
static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = pin & 0x1f;
|
||||
|
||||
|
|
@ -2947,13 +2859,189 @@ static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations pinmux_ops = {
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
|
||||
[ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */
|
||||
[ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */
|
||||
[ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */
|
||||
[ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */
|
||||
[ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */
|
||||
[ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */
|
||||
[ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */
|
||||
[ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */
|
||||
[ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */
|
||||
[ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */
|
||||
[10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */
|
||||
[11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */
|
||||
[12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */
|
||||
[13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */
|
||||
[14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */
|
||||
[15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */
|
||||
[16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */
|
||||
[17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */
|
||||
[18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */
|
||||
[19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */
|
||||
[20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */
|
||||
[21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */
|
||||
[22] = SH_PFC_PIN_NONE,
|
||||
[23] = SH_PFC_PIN_NONE,
|
||||
[24] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = PIN_PRESETOUT_N, /* PRESETOUT# */
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = PIN_EXTALR, /* EXTALR */
|
||||
[31] = PIN_FSCLKST_N, /* FSCLKST# */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
|
||||
[ 0] = PIN_FSCLKST, /* FSCLKST */
|
||||
[ 1] = SH_PFC_PIN_NONE,
|
||||
[ 2] = RCAR_GP_PIN(1, 0), /* IRQ0 */
|
||||
[ 3] = PIN_DCUTRST_N, /* DCUTRST# */
|
||||
[ 4] = PIN_DCUTCK_LPDCLK, /* DCUTCK_LPDCLK */
|
||||
[ 5] = PIN_DCUTMS, /* DCUTMS */
|
||||
[ 6] = PIN_DCUTDI_LPDI, /* DCUTDI_LPDI */
|
||||
[ 7] = SH_PFC_PIN_NONE,
|
||||
[ 8] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
|
||||
[ 9] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */
|
||||
[10] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */
|
||||
[11] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */
|
||||
[12] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */
|
||||
[13] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */
|
||||
[14] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */
|
||||
[15] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */
|
||||
[16] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */
|
||||
[17] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */
|
||||
[18] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */
|
||||
[19] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */
|
||||
[20] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */
|
||||
[21] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */
|
||||
[22] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */
|
||||
[23] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */
|
||||
[24] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */
|
||||
[25] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
|
||||
[26] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */
|
||||
[27] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */
|
||||
[28] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */
|
||||
[29] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */
|
||||
[30] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */
|
||||
[31] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
|
||||
[ 0] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */
|
||||
[ 1] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */
|
||||
[ 2] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */
|
||||
[ 3] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */
|
||||
[ 4] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */
|
||||
[ 5] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */
|
||||
[ 6] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */
|
||||
[ 7] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */
|
||||
[ 8] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */
|
||||
[ 9] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */
|
||||
[10] = RCAR_GP_PIN(4, 0), /* SCL0 */
|
||||
[11] = RCAR_GP_PIN(4, 1), /* SDA0 */
|
||||
[12] = RCAR_GP_PIN(4, 2), /* SCL1 */
|
||||
[13] = RCAR_GP_PIN(4, 3), /* SDA1 */
|
||||
[14] = RCAR_GP_PIN(4, 4), /* SCL2 */
|
||||
[15] = RCAR_GP_PIN(4, 5), /* SDA2 */
|
||||
[16] = RCAR_GP_PIN(1, 1), /* AVB_RX_CTL */
|
||||
[17] = RCAR_GP_PIN(1, 2), /* AVB_RXC */
|
||||
[18] = RCAR_GP_PIN(1, 3), /* AVB_RD0 */
|
||||
[19] = RCAR_GP_PIN(1, 4), /* AVB_RD1 */
|
||||
[20] = RCAR_GP_PIN(1, 5), /* AVB_RD2 */
|
||||
[21] = RCAR_GP_PIN(1, 6), /* AVB_RD3 */
|
||||
[22] = RCAR_GP_PIN(1, 7), /* AVB_TX_CTL */
|
||||
[23] = RCAR_GP_PIN(1, 8), /* AVB_TXC */
|
||||
[24] = RCAR_GP_PIN(1, 9), /* AVB_TD0 */
|
||||
[25] = RCAR_GP_PIN(1, 10), /* AVB_TD1 */
|
||||
[26] = RCAR_GP_PIN(1, 11), /* AVB_TD2 */
|
||||
[27] = RCAR_GP_PIN(1, 12), /* AVB_TD3 */
|
||||
[28] = RCAR_GP_PIN(1, 13), /* AVB_TXCREFCLK */
|
||||
[29] = RCAR_GP_PIN(1, 14), /* AVB_MDIO */
|
||||
[30] = RCAR_GP_PIN(1, 15), /* AVB_MDC */
|
||||
[31] = RCAR_GP_PIN(1, 16), /* AVB_MAGIC */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
|
||||
[ 0] = RCAR_GP_PIN(1, 17), /* AVB_PHY_INT */
|
||||
[ 1] = RCAR_GP_PIN(1, 18), /* AVB_LINK */
|
||||
[ 2] = RCAR_GP_PIN(1, 19), /* AVB_AVTP_MATCH */
|
||||
[ 3] = RCAR_GP_PIN(1, 20), /* AVTP_CAPTURE */
|
||||
[ 4] = RCAR_GP_PIN(4, 6), /* GETHER_RX_CTL */
|
||||
[ 5] = RCAR_GP_PIN(4, 7), /* GETHER_RXC */
|
||||
[ 6] = RCAR_GP_PIN(4, 8), /* GETHER_RD0 */
|
||||
[ 7] = RCAR_GP_PIN(4, 9), /* GETHER_RD1 */
|
||||
[ 8] = RCAR_GP_PIN(4, 10), /* GETHER_RD2 */
|
||||
[ 9] = RCAR_GP_PIN(4, 11), /* GETHER_RD3 */
|
||||
[10] = RCAR_GP_PIN(4, 12), /* GETHER_TX_CTL */
|
||||
[11] = RCAR_GP_PIN(4, 13), /* GETHER_TXC */
|
||||
[12] = RCAR_GP_PIN(4, 14), /* GETHER_TD0 */
|
||||
[13] = RCAR_GP_PIN(4, 15), /* GETHER_TD1 */
|
||||
[14] = RCAR_GP_PIN(4, 16), /* GETHER_TD2 */
|
||||
[15] = RCAR_GP_PIN(4, 17), /* GETHER_TD3 */
|
||||
[16] = RCAR_GP_PIN(4, 18), /* GETHER_TXCREFCLK */
|
||||
[17] = RCAR_GP_PIN(4, 19), /* GETHER_TXCREFCLK_MEGA */
|
||||
[18] = RCAR_GP_PIN(4, 20), /* GETHER_MDIO_A */
|
||||
[19] = RCAR_GP_PIN(4, 21), /* GETHER_MDC_A */
|
||||
[20] = RCAR_GP_PIN(4, 22), /* GETHER_MAGIC */
|
||||
[21] = RCAR_GP_PIN(4, 23), /* GETHER_PHY_INT_A */
|
||||
[22] = RCAR_GP_PIN(4, 24), /* GETHER_LINK_A */
|
||||
[23] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */
|
||||
[24] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */
|
||||
[25] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */
|
||||
[26] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */
|
||||
[27] = RCAR_GP_PIN(1, 25), /* CAN_CLK_A */
|
||||
[28] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */
|
||||
[29] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */
|
||||
[30] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */
|
||||
[31] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
|
||||
[ 0] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */
|
||||
[ 1] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */
|
||||
[ 2] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */
|
||||
[ 3] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */
|
||||
[ 4] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */
|
||||
[ 5] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */
|
||||
[ 6] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */
|
||||
[ 7] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */
|
||||
[ 8] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */
|
||||
[ 9] = RCAR_GP_PIN(5, 13), /* RPC_WP# */
|
||||
[10] = RCAR_GP_PIN(5, 14), /* RPC_INT# */
|
||||
[11] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */
|
||||
[12] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */
|
||||
[13] = RCAR_GP_PIN(2, 17), /* IRQ4 */
|
||||
[14] = RCAR_GP_PIN(2, 18), /* IRQ5 */
|
||||
[15] = RCAR_GP_PIN(2, 25), /* SCL3 */
|
||||
[16] = RCAR_GP_PIN(2, 26), /* SDA3 */
|
||||
[17] = RCAR_GP_PIN(2, 19), /* MSIOF0_RXD */
|
||||
[18] = RCAR_GP_PIN(2, 20), /* MSIOF0_TXD */
|
||||
[19] = RCAR_GP_PIN(2, 21), /* MSIOF0_SCK */
|
||||
[20] = RCAR_GP_PIN(2, 22), /* MSIOF0_SYNC */
|
||||
[21] = RCAR_GP_PIN(2, 23), /* MSIOF0_SS1 */
|
||||
[22] = RCAR_GP_PIN(2, 24), /* MSIOF0_SS2 */
|
||||
[23] = RCAR_GP_PIN(2, 27), /* FSO_CFE_0# */
|
||||
[24] = RCAR_GP_PIN(2, 28), /* FSO_CFE_1# */
|
||||
[25] = RCAR_GP_PIN(2, 29), /* FSO_TOE# */
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77980_pfc_ops = {
|
||||
.pin_to_pocctrl = r8a77980_pin_to_pocctrl,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a77980_pinmux_info = {
|
||||
.name = "r8a77980_pfc",
|
||||
.ops = &pinmux_ops,
|
||||
.ops = &r8a77980_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
@ -2966,6 +3054,7 @@ const struct sh_pfc_soc_info r8a77980_pinmux_info = {
|
|||
.nr_functions = ARRAY_SIZE(pinmux_functions),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
.ioctrl_regs = pinmux_ioctrl_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
|
|
|
|||
Loading…
Reference in a new issue