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pinctrl: renesas: Synchronize R8A779A0 V3U PFC tables with Linux 6.1.7
Synchronize R-Car R8A779A0 V3U PFC tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
37fb54b6e6
commit
8a9e8ba9ae
1 changed files with 145 additions and 255 deletions
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@ -392,7 +392,6 @@
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#define IP3SR1_19_16 FM(GP1_28) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_23_20 FM(GP1_29) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_27_24 FM(GP1_30) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
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#define IP0SR2_3_0 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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@ -423,11 +422,8 @@
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#define IP2SR2_31_28 FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(EX_WAIT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
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#define IP0SR3_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR3_7_4 FM(CANFD0_TX) FM(FXR_TXDA_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR3_11_8 FM(CANFD0_RX) FM(RXDA_EXTFXR_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR3_15_12 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR3_19_16 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR3_23_20 FM(CANFD2_TX) FM(TPU0TO2) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR3_27_24 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR3_31_28 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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@ -438,8 +434,6 @@
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#define IP1SR3_15_12 FM(CANFD5_TX) F_(0, 0) F_(0, 0) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR3_19_16 FM(CANFD5_RX) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR3_23_20 FM(CANFD6_TX) F_(0, 0) F_(0, 0) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR3_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR3_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
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#define IP0SR4_3_0 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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@ -460,14 +454,10 @@
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#define IP1SR4_27_24 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR4_31_28 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
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#define IP2SR4_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR4_7_4 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR4_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR4_15_12 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR4_19_16 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR4_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR4_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR4_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
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#define IP0SR5_3_0 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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@ -488,14 +478,10 @@
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#define IP1SR5_27_24 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR5_31_28 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
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#define IP2SR5_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR5_7_4 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR5_11_8 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR5_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR5_19_16 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR5_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR5_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP2SR5_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define PINMUX_GPSR \
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\
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@ -540,7 +526,7 @@ FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2
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FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
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FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \
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FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 FM(IP3SR1_27_24) IP3SR1_27_24 \
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FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 FM(IP3SR1_31_28) IP3SR1_31_28 \
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FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \
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\
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FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \
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FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
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@ -551,51 +537,51 @@ FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 FM(IP2SR2_23_20) IP2
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FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 FM(IP2SR2_27_24) IP2SR2_27_24 \
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FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \
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\
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FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 \
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FM(IP1SR3_3_0) IP1SR3_3_0 \
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FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 \
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FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 \
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FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 \
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FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 \
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FM(IP1SR3_15_12) IP1SR3_15_12 \
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FM(IP1SR3_19_16) IP1SR3_19_16 \
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FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 \
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FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 \
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FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 \
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FM(IP0SR3_27_24) IP0SR3_27_24 \
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FM(IP0SR3_31_28) IP0SR3_31_28 \
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\
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FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 \
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FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 \
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FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \
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FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \
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FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \
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FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \
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FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \
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FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \
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FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \
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FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 \
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FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 \
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FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 \
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\
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FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \
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FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 \
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FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \
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FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \
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FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \
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FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \
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FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 FM(IP2SR5_23_20) IP2SR5_23_20 \
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FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 FM(IP2SR5_27_24) IP2SR5_27_24 \
|
||||
FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 FM(IP2SR5_31_28) IP2SR5_31_28
|
||||
FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \
|
||||
FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \
|
||||
FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28
|
||||
|
||||
/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
|
||||
#define MOD_SEL2_14_15 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3)
|
||||
#define MOD_SEL2_12_13 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3)
|
||||
#define MOD_SEL2_10_11 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3)
|
||||
#define MOD_SEL2_8_9 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3)
|
||||
#define MOD_SEL2_6_7 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3)
|
||||
#define MOD_SEL2_4_5 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3)
|
||||
#define MOD_SEL2_2_3 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3)
|
||||
#define MOD_SEL2_15_14 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3)
|
||||
#define MOD_SEL2_13_12 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3)
|
||||
#define MOD_SEL2_11_10 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3)
|
||||
#define MOD_SEL2_9_8 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3)
|
||||
#define MOD_SEL2_7_6 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3)
|
||||
#define MOD_SEL2_5_4 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3)
|
||||
#define MOD_SEL2_3_2 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3)
|
||||
|
||||
#define PINMUX_MOD_SELS \
|
||||
\
|
||||
MOD_SEL2_14_15 \
|
||||
MOD_SEL2_12_13 \
|
||||
MOD_SEL2_10_11 \
|
||||
MOD_SEL2_8_9 \
|
||||
MOD_SEL2_6_7 \
|
||||
MOD_SEL2_4_5 \
|
||||
MOD_SEL2_2_3
|
||||
MOD_SEL2_15_14 \
|
||||
MOD_SEL2_13_12 \
|
||||
MOD_SEL2_11_10 \
|
||||
MOD_SEL2_9_8 \
|
||||
MOD_SEL2_7_6 \
|
||||
MOD_SEL2_5_4 \
|
||||
MOD_SEL2_3_2
|
||||
|
||||
#define PINMUX_PHYS \
|
||||
FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \
|
||||
|
|
@ -632,7 +618,36 @@ enum {
|
|||
};
|
||||
|
||||
static const u16 pinmux_data[] = {
|
||||
/* Using GP_2_[2-15] requires disabling I2C in MOD_SEL2 */
|
||||
#define GP_2_2_FN GP_2_2_FN, FN_SEL_I2C0_0
|
||||
#define GP_2_3_FN GP_2_3_FN, FN_SEL_I2C0_0
|
||||
#define GP_2_4_FN GP_2_4_FN, FN_SEL_I2C1_0
|
||||
#define GP_2_5_FN GP_2_5_FN, FN_SEL_I2C1_0
|
||||
#define GP_2_6_FN GP_2_6_FN, FN_SEL_I2C2_0
|
||||
#define GP_2_7_FN GP_2_7_FN, FN_SEL_I2C2_0
|
||||
#define GP_2_8_FN GP_2_8_FN, FN_SEL_I2C3_0
|
||||
#define GP_2_9_FN GP_2_9_FN, FN_SEL_I2C3_0
|
||||
#define GP_2_10_FN GP_2_10_FN, FN_SEL_I2C4_0
|
||||
#define GP_2_11_FN GP_2_11_FN, FN_SEL_I2C4_0
|
||||
#define GP_2_12_FN GP_2_12_FN, FN_SEL_I2C5_0
|
||||
#define GP_2_13_FN GP_2_13_FN, FN_SEL_I2C5_0
|
||||
#define GP_2_14_FN GP_2_14_FN, FN_SEL_I2C6_0
|
||||
#define GP_2_15_FN GP_2_15_FN, FN_SEL_I2C6_0
|
||||
PINMUX_DATA_GP_ALL(),
|
||||
#undef GP_2_2_FN
|
||||
#undef GP_2_3_FN
|
||||
#undef GP_2_4_FN
|
||||
#undef GP_2_5_FN
|
||||
#undef GP_2_6_FN
|
||||
#undef GP_2_7_FN
|
||||
#undef GP_2_8_FN
|
||||
#undef GP_2_9_FN
|
||||
#undef GP_2_10_FN
|
||||
#undef GP_2_11_FN
|
||||
#undef GP_2_12_FN
|
||||
#undef GP_2_13_FN
|
||||
#undef GP_2_14_FN
|
||||
#undef GP_2_15_FN
|
||||
|
||||
PINMUX_SINGLE(MMC_D7),
|
||||
PINMUX_SINGLE(MMC_D6),
|
||||
|
|
@ -2012,30 +2027,14 @@ static const unsigned int intc_ex_irq5_mux[] = {
|
|||
};
|
||||
|
||||
/* - MMC -------------------------------------------------------------------- */
|
||||
static const unsigned int mmc_data1_pins[] = {
|
||||
/* MMC_SD_D0 */
|
||||
RCAR_GP_PIN(0, 19),
|
||||
};
|
||||
static const unsigned int mmc_data1_mux[] = {
|
||||
MMC_SD_D0_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data4_pins[] = {
|
||||
/* MMC_SD_D[0:3] */
|
||||
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
|
||||
RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
|
||||
};
|
||||
static const unsigned int mmc_data4_mux[] = {
|
||||
MMC_SD_D0_MARK, MMC_SD_D1_MARK,
|
||||
MMC_SD_D2_MARK, MMC_SD_D3_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data8_pins[] = {
|
||||
static const unsigned int mmc_data_pins[] = {
|
||||
/* MMC_SD_D[0:3], MMC_D[4:7] */
|
||||
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
|
||||
RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
|
||||
RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
|
||||
RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27),
|
||||
};
|
||||
static const unsigned int mmc_data8_mux[] = {
|
||||
static const unsigned int mmc_data_mux[] = {
|
||||
MMC_SD_D0_MARK, MMC_SD_D1_MARK,
|
||||
MMC_SD_D2_MARK, MMC_SD_D3_MARK,
|
||||
MMC_D4_MARK, MMC_D5_MARK,
|
||||
|
|
@ -2387,19 +2386,12 @@ static const unsigned int qspi0_ctrl_pins[] = {
|
|||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
static const unsigned int qspi0_data_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
|
||||
RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
static const unsigned int qspi0_data_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK
|
||||
};
|
||||
|
|
@ -2412,19 +2404,12 @@ static const unsigned int qspi1_ctrl_pins[] = {
|
|||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
static const unsigned int qspi1_data_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
|
||||
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
static const unsigned int qspi1_data_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK
|
||||
};
|
||||
|
|
@ -2718,9 +2703,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(intc_ex_irq4),
|
||||
SH_PFC_PIN_GROUP(intc_ex_irq5),
|
||||
|
||||
SH_PFC_PIN_GROUP(mmc_data1),
|
||||
SH_PFC_PIN_GROUP(mmc_data4),
|
||||
SH_PFC_PIN_GROUP(mmc_data8),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(mmc_cd),
|
||||
SH_PFC_PIN_GROUP(mmc_wp),
|
||||
|
|
@ -2770,11 +2755,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(pwm4),
|
||||
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 4),
|
||||
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
SH_PFC_PIN_GROUP(scif0_clk),
|
||||
|
|
@ -3256,14 +3241,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_1_1_FN, GPSR1_1,
|
||||
GP_1_0_FN, GPSR1_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR2", 0xe6050840, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6050840, 32,
|
||||
GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP2_31_25 RESERVED */
|
||||
GP_2_24_FN, GPSR2_24,
|
||||
GP_2_23_FN, GPSR2_23,
|
||||
GP_2_22_FN, GPSR2_22,
|
||||
|
|
@ -3290,22 +3272,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_2_1_FN, GPSR2_1,
|
||||
GP_2_0_FN, GPSR2_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR3", 0xe6058840, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe6058840, 32,
|
||||
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP3_31_17 RESERVED */
|
||||
GP_3_16_FN, GPSR3_16,
|
||||
GP_3_15_FN, GPSR3_15,
|
||||
GP_3_14_FN, GPSR3_14,
|
||||
|
|
@ -3358,18 +3329,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_4_1_FN, GPSR4_1,
|
||||
GP_4_0_FN, GPSR4_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR5", 0xe6060840, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060840, 32,
|
||||
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP5_31_21 RESERVED */
|
||||
GP_5_20_FN, GPSR5_20,
|
||||
GP_5_19_FN, GPSR5_19,
|
||||
GP_5_18_FN, GPSR5_18,
|
||||
|
|
@ -3392,18 +3356,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_5_1_FN, GPSR5_1,
|
||||
GP_5_0_FN, GPSR5_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR6", 0xe6068040, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR6", 0xe6068040, 32,
|
||||
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP6_31_21 RESERVED */
|
||||
GP_6_20_FN, GPSR6_20,
|
||||
GP_6_19_FN, GPSR6_19,
|
||||
GP_6_18_FN, GPSR6_18,
|
||||
|
|
@ -3426,18 +3383,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_6_1_FN, GPSR6_1,
|
||||
GP_6_0_FN, GPSR6_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR7", 0xe6068840, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR7", 0xe6068840, 32,
|
||||
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP7_31_21 RESERVED */
|
||||
GP_7_20_FN, GPSR7_20,
|
||||
GP_7_19_FN, GPSR7_19,
|
||||
GP_7_18_FN, GPSR7_18,
|
||||
|
|
@ -3460,18 +3410,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_7_1_FN, GPSR7_1,
|
||||
GP_7_0_FN, GPSR7_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR8", 0xe6069040, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR8", 0xe6069040, 32,
|
||||
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP8_31_21 RESERVED */
|
||||
GP_8_20_FN, GPSR8_20,
|
||||
GP_8_19_FN, GPSR8_19,
|
||||
GP_8_18_FN, GPSR8_18,
|
||||
|
|
@ -3494,18 +3437,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_8_1_FN, GPSR8_1,
|
||||
GP_8_0_FN, GPSR8_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR9", 0xe6069840, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR9", 0xe6069840, 32,
|
||||
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP9_31_21 RESERVED */
|
||||
GP_9_20_FN, GPSR9_20,
|
||||
GP_9_19_FN, GPSR9_19,
|
||||
GP_9_18_FN, GPSR9_18,
|
||||
|
|
@ -3563,8 +3499,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP2SR1_7_4
|
||||
IP2SR1_3_0))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IP3SR1", 0xe605006c, 32, 4, GROUP(
|
||||
IP3SR1_31_28
|
||||
{ PINMUX_CFG_REG_VAR("IP3SR1", 0xe605006c, 32,
|
||||
GROUP(-4, 4, 4, 4, 4, 4, 4, 4),
|
||||
GROUP(
|
||||
/* IP3SR1_31_28 RESERVED */
|
||||
IP3SR1_27_24
|
||||
IP3SR1_23_20
|
||||
IP3SR1_19_16
|
||||
|
|
@ -3603,19 +3541,21 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP2SR2_7_4
|
||||
IP2SR2_3_0))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IP0SR3", 0xe6058860, 32, 4, GROUP(
|
||||
{ PINMUX_CFG_REG_VAR("IP0SR3", 0xe6058860, 32,
|
||||
GROUP(4, 4, 4, -8, 4, 4, -4),
|
||||
GROUP(
|
||||
IP0SR3_31_28
|
||||
IP0SR3_27_24
|
||||
IP0SR3_23_20
|
||||
IP0SR3_19_16
|
||||
IP0SR3_15_12
|
||||
/* IP0SR3_19_12 RESERVED */
|
||||
IP0SR3_11_8
|
||||
IP0SR3_7_4
|
||||
IP0SR3_3_0))
|
||||
/* IP0SR3_3_0 RESERVED */ ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IP1SR3", 0xe6058864, 32, 4, GROUP(
|
||||
IP1SR3_31_28
|
||||
IP1SR3_27_24
|
||||
{ PINMUX_CFG_REG_VAR("IP1SR3", 0xe6058864, 32,
|
||||
GROUP(-8, 4, 4, 4, 4, 4, 4),
|
||||
GROUP(
|
||||
/* IP1SR3_31_24 RESERVED */
|
||||
IP1SR3_23_20
|
||||
IP1SR3_19_16
|
||||
IP1SR3_15_12
|
||||
|
|
@ -3643,15 +3583,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP1SR4_7_4
|
||||
IP1SR4_3_0))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IP2SR4", 0xe6060068, 32, 4, GROUP(
|
||||
IP2SR4_31_28
|
||||
IP2SR4_27_24
|
||||
IP2SR4_23_20
|
||||
{ PINMUX_CFG_REG_VAR("IP2SR4", 0xe6060068, 32,
|
||||
GROUP(-12, 4, 4, 4, 4, -4),
|
||||
GROUP(
|
||||
/* IP2SR4_31_20 RESERVED */
|
||||
IP2SR4_19_16
|
||||
IP2SR4_15_12
|
||||
IP2SR4_11_8
|
||||
IP2SR4_7_4
|
||||
IP2SR4_3_0))
|
||||
/* IP2SR4_3_0 RESERVED */ ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IP0SR5", 0xe6060860, 32, 4, GROUP(
|
||||
IP0SR5_31_28
|
||||
|
|
@ -3673,15 +3613,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP1SR5_7_4
|
||||
IP1SR5_3_0))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IP2SR5", 0xe6060868, 32, 4, GROUP(
|
||||
IP2SR5_31_28
|
||||
IP2SR5_27_24
|
||||
IP2SR5_23_20
|
||||
{ PINMUX_CFG_REG_VAR("IP2SR5", 0xe6060868, 32,
|
||||
GROUP(-12, 4, 4, 4, 4, -4),
|
||||
GROUP(
|
||||
/* IP2SR5_31_20 RESERVED */
|
||||
IP2SR5_19_16
|
||||
IP2SR5_15_12
|
||||
IP2SR5_11_8
|
||||
IP2SR5_7_4
|
||||
IP2SR5_3_0))
|
||||
/* IP2SR5_3_0 RESERVED */ ))
|
||||
},
|
||||
#undef F_
|
||||
#undef FM
|
||||
|
|
@ -3689,25 +3629,17 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
#define F_(x, y) x,
|
||||
#define FM(x) FN_##x,
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6050900, 32,
|
||||
GROUP(4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 1, 1),
|
||||
GROUP(-16, 2, 2, 2, 2, 2, 2, 2, -2),
|
||||
GROUP(
|
||||
/* RESERVED 31, 30, 29, 28 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 27, 26, 25, 24 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 23, 22, 21, 20 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 19, 18, 17, 16 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
MOD_SEL2_14_15
|
||||
MOD_SEL2_12_13
|
||||
MOD_SEL2_10_11
|
||||
MOD_SEL2_8_9
|
||||
MOD_SEL2_6_7
|
||||
MOD_SEL2_4_5
|
||||
MOD_SEL2_2_3
|
||||
0, 0,
|
||||
0, 0, ))
|
||||
/* RESERVED 31-16 */
|
||||
MOD_SEL2_15_14
|
||||
MOD_SEL2_13_12
|
||||
MOD_SEL2_11_10
|
||||
MOD_SEL2_9_8
|
||||
MOD_SEL2_7_6
|
||||
MOD_SEL2_5_4
|
||||
MOD_SEL2_3_2
|
||||
/* RESERVED 1-0 */ ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
|
@ -3838,7 +3770,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(3, 12), 16, 3 }, /* CANFD5_RX */
|
||||
{ RCAR_GP_PIN(3, 11), 12, 3 }, /* CANFD5_TX */
|
||||
{ RCAR_GP_PIN(3, 10), 8, 3 }, /* CANFD4_RX */
|
||||
{ RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX*/
|
||||
{ RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX */
|
||||
{ RCAR_GP_PIN(3, 8), 0, 3 }, /* CANFD3_RX */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6058888) {
|
||||
|
|
@ -4044,8 +3976,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a779a0_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
||||
u32 *pocctrl)
|
||||
static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = pin & 0x1f;
|
||||
|
||||
|
|
@ -4308,7 +4239,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[11] = RCAR_GP_PIN(6, 11), /* AVB2_TD3 */
|
||||
[12] = RCAR_GP_PIN(6, 12), /* AVB2_TXCREFCLK */
|
||||
[13] = RCAR_GP_PIN(6, 13), /* AVB2_MDIO */
|
||||
[14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC*/
|
||||
[14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC */
|
||||
[15] = RCAR_GP_PIN(6, 15), /* AVB2_MAGIC */
|
||||
[16] = RCAR_GP_PIN(6, 16), /* AVB2_PHY_INT */
|
||||
[17] = RCAR_GP_PIN(6, 17), /* AVB2_LINK */
|
||||
|
|
@ -4432,56 +4363,15 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static unsigned int r8a779a0_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int bit;
|
||||
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
|
||||
if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
}
|
||||
|
||||
static void r8a779a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
u32 enable, updown;
|
||||
unsigned int bit;
|
||||
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
|
||||
if (bias != PIN_CONFIG_BIAS_DISABLE)
|
||||
enable |= BIT(bit);
|
||||
|
||||
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_UP)
|
||||
updown |= BIT(bit);
|
||||
|
||||
sh_pfc_write(pfc, reg->pud, updown);
|
||||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations pinmux_ops = {
|
||||
static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = {
|
||||
.pin_to_pocctrl = r8a779a0_pin_to_pocctrl,
|
||||
.get_bias = r8a779a0_pinmux_get_bias,
|
||||
.set_bias = r8a779a0_pinmux_set_bias,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a779a0_pinmux_info = {
|
||||
.name = "r8a779a0_pfc",
|
||||
.ops = &pinmux_ops,
|
||||
.ops = &r8a779a0_pfc_ops,
|
||||
.unlock_reg = 0x1ff, /* PMMRn mask */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue