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ARM: dts: rmobile: Synchronize DTs with Linux 6.1.7

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Synchronize R-Car device trees with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

The following script has been used for the synchronization:

$ for i in $(cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) ; do
	if [ -e /linux-2.6/arch/arm64/boot/dts/renesas/$i ] ; then
		cp /linux-2.6/arch/arm64/boot/dts/renesas/$i arch/arm/dts/ ;
	elif [ -e /linux-2.6/arch/arm/boot/dts/$i ] ; then
		cp /linux-2.6/arch/arm/boot/dts/$i arch/arm/dts/
	else
		echo "NOT FOUND: $i"
	fi
done
$ git add $( ( cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) | tr " " "\n" | sed 's@^@arch/arm/dts/@g' )

Move the include/dt-bindings/{clk,clock}/versaclock.h header used by
the renesas boards to match Linux 6.1.y as well.

Keep arch/arm/dts/r8a774c0-u-boot.dtsi sdhi3 node as it is now used
by the arch/arm/dts/r8a774c0-cat874.dts board.

Pick s@spi-flash@flash@ change in arch/arm/dts/r8a779a0-falcon-u-boot.dts
from "ARM: dts: Synchronize R-Car V3U DTs with Linux 5.18.3" .

Adjust R8A77990 Ebisu CONFIG_SYS_MMC_ENV_DEV from 2 to 0 to reflect
the card enumeration in ebisu.dtsi /aliases DT node .

Adjust R8A7795 and R8A7796 ULCB CONFIG_SYS_MMC_ENV_DEV from 1 to 0 to
reflect the card enumeration in ulcb.dtsi /aliases DT node .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> # r8a779a0-falcon-u-boot.dts
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> # r8a779a0-falcon-u-boot.dts
This commit is contained in:
Marek Vasut 2023-01-26 21:01:32 +01:00 committed by Marek Vasut
parent 9696b246e6
commit 71d2a5e5ef
62 changed files with 6856 additions and 2390 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

27
arch/arm/dts/beacon-renesom-baseboard.dtsi
View file

@ -5,7 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/clk/versaclock.h>
#include <dt-bindings/clock/versaclock.h>
/ {
backlight_lvds: backlight-lvds {
@ -146,7 +146,7 @@
};
};
reg_audio: regulator_audio {
reg_audio: regulator-audio {
compatible = "regulator-fixed";
regulator-name = "audio-1.8V";
regulator-min-microvolt = <1800000>;
@ -174,7 +174,7 @@
vin-supply = <&reg_lcd>;
};
reg_cam0: regulator_camera {
reg_cam0: regulator-cam0 {
compatible = "regulator-fixed";
regulator-name = "reg_cam0";
regulator-min-microvolt = <1800000>;
@ -183,7 +183,7 @@
enable-active-high;
};
reg_cam1: regulator_camera {
reg_cam1: regulator-cam1 {
compatible = "regulator-fixed";
regulator-name = "reg_cam1";
regulator-min-microvolt = <1800000>;
@ -272,8 +272,14 @@
status = "okay";
};
&du_out_rgb {
remote-endpoint = <&rgb_panel>;
&du {
ports {
port@0 {
du_out_rgb: endpoint {
remote-endpoint = <&rgb_panel>;
};
};
};
};
&ehci0 {
@ -359,11 +365,10 @@
clocks = <&x304_clk>;
clock-names = "xin";
assigned-clocks = <&versaclock6_bb 1>,
<&versaclock6_bb 2>,
<&versaclock6_bb 3>,
<&versaclock6_bb 4>;
assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>;
assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>,
<&versaclock6_bb 3>, <&versaclock6_bb 4>;
assigned-clock-rates = <24000000>, <24000000>, <24000000>,
<24576000>;
OUT1 {
idt,mode = <VC5_CMOS>;

9
arch/arm/dts/beacon-renesom-som.dtsi
View file

@ -4,7 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/versaclock.h>
#include <dt-bindings/clock/versaclock.h>
/ {
memory@48000000 {
@ -20,7 +20,7 @@
clock-output-names = "osc_32k";
};
reg_1p8v: regulator0 {
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
@ -29,7 +29,7 @@
regulator-always-on;
};
reg_3p3v: regulator1 {
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
@ -77,7 +77,7 @@
};
&gpio6 {
usb_hub_reset {
usb-hub-reset-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;
@ -293,7 +293,6 @@
vqmmc-supply = <&reg_1p8v>;
non-removable;
cap-power-off-card;
pm-ignore-notify;
keep-power-in-suspend;
mmc-pwrseq = <&wlan_pwrseq>;
status = "okay";

5
arch/arm/dts/cat875.dtsi
View file

@ -2,7 +2,7 @@
/*
* Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875)
*
* Copyright (C) 2021 Renesas Electronics Corp.
* Copyright (C) 2019 Renesas Electronics Corp.
*/
/ {
@ -18,9 +18,12 @@
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c915",
"ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;

548
arch/arm/dts/condor-common.dtsi Normal file
View file

@ -0,0 +1,548 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Condor board with R-Car V3H
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
serial0 = &scif0;
ethernet0 = &gether;
};
chosen {
stdout-path = "serial0:115200n8";
};
d1_8v: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "D1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
d3_3v: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&d3_3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0 0x48000000 0 0x78000000>;
};
vddq_vin01: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VDDQ_VIN01";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
x1_clk: x1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
};
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
};
&csi40 {
status = "okay";
ports {
port@0 {
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max9286_out0>;
};
};
};
};
&csi41 {
status = "okay";
ports {
port@0 {
csi41_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max9286_out1>;
};
};
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&x1_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&gether {
pinctrl-0 = <&gether_pins>;
pinctrl-names = "default";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
renesas,no-ether-link;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
};
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
io_expander0: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
io_expander1: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&d1_8v>;
dvdd-supply = <&d1_8v>;
pvdd-supply = <&d1_8v>;
bgvdd-supply = <&d1_8v>;
dvdd-3v-supply = <&d3_3v>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
gmsl0: gmsl-deserializer@48 {
compatible = "maxim,max9286";
reg = <0x48>;
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
port@3 {
reg = <3>;
};
port@4 {
reg = <4>;
max9286_out0: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "disabled";
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
status = "disabled";
};
};
};
gmsl1: gmsl-deserializer@4a {
compatible = "maxim,max9286";
reg = <0x4a>;
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
port@3 {
reg = <3>;
};
port@4 {
reg = <4>;
max9286_out1: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi41_in>;
};
};
};
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "disabled";
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
status = "disabled";
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&d3_3v>;
vqmmc-supply = <&vddq_vin01>;
mmc-hs200-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&pciec {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pcie_phy {
status = "okay";
};
&pfc {
canfd0_pins: canfd0 {
groups = "canfd0_data_a";
function = "canfd0";
};
gether_pins: gether {
groups = "gether_mdio_a", "gether_rgmii",
"gether_txcrefclk", "gether_txcrefclk_mega";
function = "gether";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_b";
function = "scif_clk";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert_header_sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};

744
arch/arm/dts/draak.dtsi Normal file
View file

@ -0,0 +1,744 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Draak board
*
* Copyright (C) 2016-2018 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Renesas Draak board";
compatible = "renesas,draak";
aliases {
serial0 = &scif2;
ethernet0 = &avb;
};
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 50000>;
brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
default-brightness-level = <10>;
power-supply = <&reg_12p0v>;
enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
composite-in {
compatible = "composite-video-connector";
port {
composite_con_in: endpoint {
remote-endpoint = <&adv7180_in>;
};
};
};
hdmi-in {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&adv7612_in>;
};
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&keys_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "SW56-1";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "SW56-2";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW56-3";
wakeup-source;
debounce-interval = <20>;
};
key-4 {
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
linux,code = <KEY_4>;
label = "SW56-4";
wakeup-source;
debounce-interval = <20>;
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&reg_3p3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x18000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_12p0v: regulator-12p0v {
compatible = "regulator-fixed";
regulator-name = "D12.0V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
sound_card: sound {
compatible = "audio-graph-card";
dais = <&rsnd_port0 /* ak4613 */
/* HDMI is not yet supported */
>;
};
vga {
compatible = "vga-connector";
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
};
};
};
vga-encoder {
compatible = "adi,adv7123";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7123_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7123_out: endpoint {
remote-endpoint = <&vga_in>;
};
};
};
};
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <74250000>;
};
x19_clk: x19 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
};
&audio_clk_b {
/*
* X11 is connected to VI4_FIELD/SCIF_CLK/AUDIO_CLKB,
* and R-Car Sound uses AUDIO_CLKB.
* Note is that schematic indicates VI4_FIELD conection only
* not AUDIO_CLKB at SoC page.
* And this VI4_FIELD/SCIF_CLK/AUDIO_CLKB is connected to SW60.
* SW60 should be 1-2.
*/
clock-frequency = <22579200>;
};
&avb {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio5>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>;
/*
* TX clock internal delay mode is required for reliable
* 1Gbps communication using the KSZ9031RNX phy present on
* the Draak board, however, TX clock internal delay mode
* isn't supported on R-Car D3(e). Thus, limit speed to
* 100Mbps for reliable communication.
*/
max-speed = <100>;
};
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
status = "okay";
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&x12_clk>;
clock-names = "du.0", "du.1", "dclkin.0";
ports {
port@0 {
du_out_rgb: endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};
&ehci0 {
dr_mode = "host";
status = "okay";
};
&extal_clk {
clock-frequency = <48000000>;
};
&hsusb {
dr_mode = "host";
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
ak4613: codec@10 {
compatible = "asahi-kasei,ak4613";
#sound-dai-cells = <0>;
reg = <0x10>;
clocks = <&rcar_sound 0>; /* audio_clkout */
asahi-kasei,in1-single-end;
asahi-kasei,in2-single-end;
asahi-kasei,out1-single-end;
asahi-kasei,out2-single-end;
asahi-kasei,out3-single-end;
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
port {
ak4613_endpoint: endpoint {
remote-endpoint = <&rsnd_for_ak4613>;
};
};
};
composite-in@20 {
compatible = "adi,adv7180cp";
reg = <0x20>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7180_in: endpoint {
remote-endpoint = <&composite_con_in>;
};
};
port@3 {
reg = <3>;
/*
* The VIN4 video input path is shared between
* CVBS and HDMI inputs through SW[49-53]
* switches.
*
* CVBS is the default selection, link it to
* VIN4 here.
*/
adv7180_out: endpoint {
remote-endpoint = <&vin4_in>;
};
};
};
};
hdmi-encoder@39 {
compatible = "adi,adv7511w";
reg = <0x39>, <0x3f>, <0x3c>, <0x38>;
reg-names = "main", "edid", "cec", "packet";
interrupt-parent = <&gpio1>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
hdmi-decoder@4c {
compatible = "adi,adv7612";
reg = <0x4c>;
default-input = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7612_in: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
port@2 {
reg = <2>;
/*
* The VIN4 video input path is shared between
* CVBS and HDMI inputs through SW[49-53]
* switches.
*
* CVBS is the default selection, leave HDMI
* not connected here.
*/
adv7612_out: endpoint {
pclk-sample = <0>;
hsync-active = <0>;
vsync-active = <0>;
};
};
};
};
cs2000: clk-multiplier@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x19_clk>; /* audio_clkout_1, x19 */
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
&lvds0 {
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x12_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&lvds1 {
/*
* Even though the LVDS1 output is not connected, the encoder must be
* enabled to supply a pixel clock to the DU for the DPAD output when
* LVDS0 is in use.
*/
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x12_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
};
&ohci0 {
dr_mode = "host";
status = "okay";
};
&pfc {
avb0_pins: avb {
groups = "avb0_link", "avb0_mdio", "avb0_mii";
function = "avb0";
};
can0_pins: can0 {
groups = "can0_data_a";
function = "can0";
};
can1_pins: can1 {
groups = "can1_data_a";
function = "can1";
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
keys_pins: keys {
pins = "GP_4_12", "GP_4_13", "GP_4_14", "GP_4_15";
bias-pull-up;
};
pwm0_pins: pwm0 {
groups = "pwm0_c";
function = "pwm0";
};
pwm1_pins: pwm1 {
groups = "pwm1_c";
function = "pwm1";
};
rpc_pins: rpc {
groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
"rpc_int";
function = "rpc";
};
scif2_pins: scif2 {
groups = "scif2_data";
function = "scif2";
};
sdhi2_pins: sd2 {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi34_ctrl", "ssi3_data", "ssi4_data_a";
function = "ssi";
};
sound_clk_pins: sound-clk {
groups = "audio_clk_a", "audio_clk_b",
"audio_clkout", "audio_clkout1";
function = "audio_clk";
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
vin4_pins_cvbs: vin4 {
groups = "vin4_data8", "vin4_sync", "vin4_clk";
function = "vin4";
};
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm1 {
pinctrl-0 = <&pwm1_pins>;
pinctrl-names = "default";
status = "okay";
};
&rcar_sound {
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1 */
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
status = "okay";
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
<&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&cs2000>, <&audio_clk_b>,
<&cpg CPG_CORE R8A77995_CLK_ZA2>;
ports {
rsnd_port0: port {
rsnd_for_ak4613: endpoint {
remote-endpoint = <&ak4613_endpoint>;
dai-format = "left_j";
bitclock-master = <&rsnd_for_ak4613>;
frame-master = <&rsnd_for_ak4613>;
playback = <&ssi3>, <&src5>, <&dvc0>;
capture = <&ssi4>, <&src6>, <&dvc1>;
};
};
};
};
&rpc {
pinctrl-0 = <&rpc_pins>;
pinctrl-names = "default";
/* Left disabled. To be enabled by firmware when unlocked. */
flash@0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
bl2@40000 {
reg = <0x00040000 0x140000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x040000>;
read-only;
};
tee@200000 {
reg = <0x00200000 0x440000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x100000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi2 {
/* used for on-board eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&ssi4 {
shared-pin;
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
renesas,no-otg-pins;
status = "okay";
};
&vin4 {
pinctrl-0 = <&vin4_pins_cvbs>;
pinctrl-names = "default";
status = "okay";
ports {
port {
vin4_in: endpoint {
remote-endpoint = <&adv7180_out>;
};
};
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Ebisu board
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Renesas Ebisu board";
compatible = "renesas,ebisu";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
serial0 = &scif2;
ethernet0 = &avb;
mmc0 = &sdhi3;
mmc1 = &sdhi0;
mmc2 = &sdhi1;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 50000>;
brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
default-brightness-level = <10>;
power-supply = <&reg_12p0v>;
};
cvbs-in {
compatible = "composite-video-connector";
label = "CVBS IN";
port {
cvbs_con: endpoint {
remote-endpoint = <&adv7482_ain7>;
};
};
};
hdmi-in {
compatible = "hdmi-connector";
label = "HDMI IN";
type = "a";
port {
hdmi_in_con: endpoint {
remote-endpoint = <&adv7482_hdmi>;
};
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&keys_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "SW4-1";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "SW4-2";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW4-3";
wakeup-source;
debounce-interval = <20>;
};
key-4 {
gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_4>;
label = "SW4-4";
wakeup-source;
debounce-interval = <20>;
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&reg_3p3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_12p0v: regulator-12p0v {
compatible = "regulator-fixed";
regulator-name = "D12.0V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
rsnd_ak4613: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "rsnd-ak4613";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4613>;
};
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
};
vbus0_usb2: regulator-vbus0-usb2 {
compatible = "regulator-fixed";
regulator-name = "USB20_VBUS_CN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";
regulator-name = "SDHI1 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi1: regulator-vccq-sdhi1 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
vga {
compatible = "vga-connector";
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
};
};
};
vga-encoder {
compatible = "adi,adv7123";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7123_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7123_out: endpoint {
remote-endpoint = <&vga_in>;
};
};
};
};
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
x13_clk: x13 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <74250000>;
};
};
&audio_clk_a {
clock-frequency = <22579200>;
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
/*
* TX clock internal delay mode is required for reliable
* 1Gbps communication using the KSZ9031RNX phy present on
* the Ebisu board, however, TX clock internal delay mode
* isn't supported on R-Car E3(e). Thus, limit speed to
* 100Mbps for reliable communication.
*/
max-speed = <100>;
};
};
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
};
&csi40 {
status = "okay";
ports {
port@0 {
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&adv7482_txa>;
};
};
};
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&x13_clk>;
clock-names = "du.0", "du.1", "dclkin.0";
ports {
port@0 {
du_out_rgb: endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};
&ehci0 {
dr_mode = "otg";
status = "okay";
};
&extal_clk {
clock-frequency = <48000000>;
};
&hsusb {
dr_mode = "otg";
status = "okay";
};
&i2c0 {
status = "okay";
io_expander: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio2>;
interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
};
hdmi-encoder@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
video-receiver@70 {
compatible = "adi,adv7482";
reg = <0x70>;
interrupt-parent = <&gpio0>;
interrupt-names = "intrq1", "intrq2";
interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
<17 IRQ_TYPE_LEVEL_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
adv7482_ain7: endpoint {
remote-endpoint = <&cvbs_con>;
};
};
port@8 {
reg = <8>;
adv7482_hdmi: endpoint {
remote-endpoint = <&hdmi_in_con>;
};
};
port@a {
reg = <10>;
adv7482_txa: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&csi40_in>;
};
};
};
};
};
&i2c3 {
status = "okay";
ak4613: codec@10 {
compatible = "asahi-kasei,ak4613";
#sound-dai-cells = <0>;
reg = <0x10>;
clocks = <&rcar_sound 3>;
asahi-kasei,in1-single-end;
asahi-kasei,in2-single-end;
asahi-kasei,out1-single-end;
asahi-kasei,out2-single-end;
asahi-kasei,out3-single-end;
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
};
cs2000: clk-multiplier@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x12_clk>;
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
};
&i2c_dvfs {
status = "okay";
clock-frequency = <400000>;
pmic: pmic@30 {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "rohm,bd9571mwv";
reg = <0x30>;
interrupt-parent = <&intc_ex>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
rohm,ddr-backup-power = <0x1>;
rohm,rstbmode-level;
};
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
};
};
&lvds0 {
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x13_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&lvds1 {
/*
* Even though the LVDS1 output is not connected, the encoder must be
* enabled to supply a pixel clock to the DU for the DPAD output when
* LVDS0 is in use.
*/
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x13_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
};
&ohci0 {
dr_mode = "otg";
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pciec0 {
status = "okay";
};
&pfc {
avb_pins: avb {
groups = "avb_link", "avb_mii";
function = "avb";
};
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
irq0_pins: irq0 {
groups = "intc_ex_irq0";
function = "intc_ex";
};
keys_pins: keys {
pins = "GP_5_10", "GP_5_11", "GP_5_12", "GP_5_13";
bias-pull-up;
};
pwm3_pins: pwm3 {
groups = "pwm3_b";
function = "pwm3";
};
pwm5_pins: pwm5 {
groups = "pwm5_a";
function = "pwm5";
};
rpc_pins: rpc {
groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
"rpc_int";
function = "rpc";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <3300>;
};
sdhi1_pins_uhs: sd1_uhs {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
function = "sdhi3";
power-source = <1800>;
};
sound_clk_pins: sound_clk {
groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
"audio_clkout_a", "audio_clkout1_a";
function = "audio_clk";
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
};
usb0_pins: usb {
groups = "usb0_b", "usb0_id";
function = "usb0";
};
usb30_pins: usb30 {
groups = "usb30";
function = "usb30";
};
};
&pwm3 {
pinctrl-0 = <&pwm3_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm5 {
pinctrl-0 = <&pwm5_pins>;
pinctrl-names = "default";
status = "okay";
};
&rcar_sound {
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
status = "okay";
/* update <audio_clk_b> to <cs2000> */
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
<&cpg CPG_CORE R8A77990_CLK_ZA2>;
rcar_sound,dai {
dai0 {
playback = <&ssi0>, <&src0>, <&dvc0>;
capture = <&ssi1>, <&src1>, <&dvc1>;
};
};
};
&rpc {
pinctrl-0 = <&rpc_pins>;
pinctrl-names = "default";
/* Left disabled. To be enabled by firmware when unlocked. */
flash@0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
bl2@40000 {
reg = <0x00040000 0x140000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x040000>;
read-only;
};
tee@200000 {
reg = <0x00200000 0x440000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x100000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi3 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi3_pins>;
pinctrl-1 = <&sdhi3_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};
&ssi1 {
shared-pin;
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
vbus-supply = <&vbus0_usb2>;
status = "okay";
};
&usb3_peri0 {
companion = <&xhci0>;
status = "okay";
};
&vin4 {
status = "okay";
};
&vin5 {
status = "okay";
};
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
status = "okay";
};

10
arch/arm/dts/hihope-rev4.dtsi
View file

@ -3,7 +3,7 @@
* Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
* HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
@ -80,7 +80,7 @@
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
status = "okay";
@ -91,7 +91,11 @@
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
/* update <audio_clk_b> to <cs2000> */
/*
* Update <audio_clk_b> to <cs2000>
* Switch SW2404 should be at position 1 so that clock from
* CS2000 is connected to AUDIO_CLKB_A
*/
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,

7
arch/arm/dts/hihope-rzg2-ex.dtsi
View file

@ -2,7 +2,7 @@
/*
* Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
* Copyright (C) 2019 Renesas Electronics Corp.
*/
/ {
@ -19,10 +19,13 @@
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
tx-internal-delay-ps = <2000>;
rx-internal-delay-ps = <1800>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c915",
"ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;

8
arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
View file

@ -14,6 +14,14 @@
compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &iic_pmic;
serial0 = &scif2;
serial1 = &hscif0;
serial2 = &hscif1;

2
arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts
View file

@ -3,7 +3,7 @@
* Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 connected to
* sub board
*
* Copyright (C) 2021 Renesas Electronics Corp.
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774a1-hihope-rzg2m.dts"

2
arch/arm/dts/r8a774a1-hihope-rzg2m.dts
View file

@ -2,7 +2,7 @@
/*
* Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 main board
*
* Copyright (C) 2021 Renesas Electronics Corp.
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;

66
arch/arm/dts/r8a774a1.dtsi
View file

@ -17,17 +17,6 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
};
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
@ -58,7 +47,7 @@
clock-frequency = <0>;
};
cluster0_opp: opp_table0 {
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@ -76,10 +65,11 @@
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
opp-suspend;
};
};
cluster1_opp: opp_table1 {
cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
@ -282,6 +272,7 @@
compatible = "renesas,r8a774a1-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -714,7 +705,7 @@
status = "disabled";
};
i2c_dvfs: i2c@e60b0000 {
iic_pmic: i2c@e60b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a774a1",
@ -1127,6 +1118,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
clock-names = "fck";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
@ -1176,6 +1168,7 @@
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A774A1_CLK_CANFD>,
<&can_clk>;
@ -1696,12 +1689,12 @@
* clkout : #clock-cells = <0>; <&rcar_sound>;
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
*/
compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
@ -2008,7 +2001,7 @@
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dmas = <&audma0 0x71>, <&audma1 0x72>;
dmas = <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx";
};
ssiu41: ssiu-33 {
@ -2274,7 +2267,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 314>;
@ -2286,7 +2280,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 313>;
@ -2298,7 +2293,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 312>;
@ -2310,7 +2306,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 311>;
@ -2326,7 +2323,6 @@
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
clock-names = "rpc";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
@ -2573,6 +2569,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -2628,6 +2628,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -2723,8 +2727,6 @@
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
@ -2761,8 +2763,6 @@
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
@ -2774,7 +2774,7 @@
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -2789,7 +2789,7 @@
};
};
sensor_thermal2: sensor-thermal2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@ -2804,7 +2804,7 @@
};
};
sensor_thermal3: sensor-thermal3 {
sensor3_thermal: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;

2
arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
View file

@ -11,7 +11,7 @@
/ {
model = "Beacon Embedded Works RZ/G2N Development Kit";
compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1";
compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1";
aliases {
serial0 = &scif2;

42
arch/arm/dts/r8a774b1.dtsi
View file

@ -47,7 +47,7 @@
clock-frequency = <0>;
};
cluster0_opp: opp_table0 {
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@ -156,6 +156,7 @@
compatible = "renesas,r8a774b1-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -588,7 +589,7 @@
status = "disabled";
};
i2c_dvfs: i2c@e60b0000 {
iic_pmic: i2c@e60b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a774b1",
@ -1001,6 +1002,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
clock-names = "fck";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
@ -1050,6 +1052,7 @@
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A774B1_CLK_CANFD>,
<&can_clk>;
@ -1570,7 +1573,7 @@
* clkout : #clock-cells = <0>; <&rcar_sound>;
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
*/
compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3";
compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
@ -1882,7 +1885,7 @@
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dmas = <&audma0 0x71>, <&audma1 0x72>;
dmas = <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx";
};
ssiu41: ssiu-33 {
@ -2132,7 +2135,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774B1_CLK_SD0H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 314>;
@ -2144,7 +2148,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774B1_CLK_SD1H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 313>;
@ -2156,7 +2161,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774B1_CLK_SD2H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 312>;
@ -2168,7 +2174,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774B1_CLK_SD3H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 311>;
@ -2184,7 +2191,6 @@
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
clock-names = "rpc";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
@ -2419,6 +2425,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -2474,6 +2484,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -2569,8 +2583,6 @@
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
@ -2607,8 +2619,6 @@
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
@ -2620,7 +2630,7 @@
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -2635,7 +2645,7 @@
};
};
sensor_thermal2: sensor-thermal2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@ -2650,7 +2660,7 @@
};
};
sensor_thermal3: sensor-thermal3 {
sensor3_thermal: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;

10
arch/arm/dts/r8a774c0-cat874.dts
View file

@ -2,7 +2,7 @@
/*
* Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
*
* Copyright (C) 2021 Renesas Electronics Corp.
* Copyright (C) 2019 Renesas Electronics Corp.
*/
/dts-v1/;
@ -17,6 +17,8 @@
aliases {
serial0 = &scif2;
serial1 = &hscif2;
mmc0 = &sdhi0;
mmc1 = &sdhi3;
};
chosen {
@ -170,7 +172,7 @@
ports {
port@0 {
endpoint {
du_out_rgb: endpoint {
remote-endpoint = <&tda19988_in>;
};
};
@ -351,7 +353,7 @@
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
@ -365,7 +367,7 @@
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src0 &dvc0>;
playback = <&ssi0>, <&src0>, <&dvc0>;
};
};
};

2
arch/arm/dts/r8a774c0-ek874.dts
View file

@ -2,7 +2,7 @@
/*
* Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874)
*
* Copyright (C) 2021 Renesas Electronics Corp.
* Copyright (C) 2019 Renesas Electronics Corp.
*/
#include "r8a774c0-cat874.dts"

1
arch/arm/dts/r8a774c0-u-boot.dtsi
View file

@ -35,7 +35,6 @@
/delete-node/ &rcar_sound;
/delete-node/ &audma0;
/delete-node/ &sdhi1;
/delete-node/ &sdhi3;
/delete-node/ &vspb0;
/delete-node/ &vspd0;
/delete-node/ &vspd1;

66
arch/arm/dts/r8a774c0.dtsi
View file

@ -2,7 +2,7 @@
/*
* Device Tree Source for the RZ/G2E (R8A774C0) SoC
*
* Copyright (C) 2020 Renesas Electronics Corp.
* Copyright (C) 2018-2019 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
@ -44,7 +44,7 @@
clock-frequency = <0>;
};
cluster1_opp: opp_table10 {
cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
opp-800000000 {
@ -145,6 +145,7 @@
compatible = "renesas,r8a774c0-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -574,11 +575,13 @@
status = "disabled";
};
i2c_dvfs: i2c@e60b0000 {
iic_pmic: i2c@e60b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a774c0";
reg = <0 0xe60b0000 0 0x15>;
compatible = "renesas,iic-r8a774c0",
"renesas,rcar-gen3-iic",
"renesas,rmobile-iic";
reg = <0 0xe60b0000 0 0x425>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 926>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
@ -957,6 +960,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
clock-names = "fck";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
@ -1005,6 +1009,7 @@
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A774C0_CLK_CANFD>,
<&can_clk>;
@ -1276,7 +1281,7 @@
vin4csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin4>;
remote-endpoint = <&csi40vin4>;
};
};
};
@ -1304,7 +1309,7 @@
vin5csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin5>;
remote-endpoint = <&csi40vin5>;
};
};
};
@ -1325,11 +1330,11 @@
*/
compatible = "renesas,rcar_sound-r8a774c0",
"renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
@ -1623,7 +1628,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 314>;
@ -1635,7 +1641,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 313>;
@ -1647,13 +1654,30 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 311>;
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a774c0-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x4000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@ -1806,6 +1830,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -1843,8 +1871,6 @@
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
@ -1886,8 +1912,6 @@
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
@ -1913,8 +1937,6 @@
port@1 {
reg = <1>;
lvds1_out: endpoint {
};
};
};
};
@ -1929,7 +1951,7 @@
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&thermal 0>;
thermal-sensors = <&thermal>;
sustainable-power = <717>;
cooling-maps {

2
arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
View file

@ -11,7 +11,7 @@
/ {
model = "Beacon Embedded Works RZ/G2H Development Kit";
compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1";
compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1";
aliases {
serial0 = &scif2;

43
arch/arm/dts/r8a774e1.dtsi
View file

@ -47,7 +47,7 @@
clock-frequency = <0>;
};
cluster0_opp: opp_table0 {
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@ -69,7 +69,7 @@
};
};
cluster1_opp: opp_table1 {
cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
@ -769,7 +769,7 @@
status = "disabled";
};
i2c_dvfs: i2c@e60b0000 {
iic_pmic: i2c@e60b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a774e1",
@ -1230,6 +1230,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
@ -1279,6 +1280,7 @@
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A774E1_CLK_CANFD>,
<&can_clk>;
@ -1783,7 +1785,7 @@
* clkout : #clock-cells = <0>; <&rcar_sound>;
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
*/
compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3";
compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
@ -2042,7 +2044,7 @@
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dmas = <&audma0 0x71>, <&audma1 0x72>;
dmas = <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx";
};
ssiu41: ssiu-33 {
@ -2361,7 +2363,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774E1_CLK_SD0H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 314>;
@ -2374,7 +2377,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774E1_CLK_SD1H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 313>;
@ -2387,7 +2391,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774E1_CLK_SD2H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 312>;
@ -2400,7 +2405,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774E1_CLK_SD3H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 311>;
@ -2417,7 +2423,6 @@
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
clock-names = "rpc";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
@ -2709,6 +2714,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -2764,6 +2773,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -2844,8 +2857,6 @@
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
@ -2882,8 +2893,6 @@
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
@ -2895,7 +2904,7 @@
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -2910,7 +2919,7 @@
};
};
sensor_thermal2: sensor-thermal2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@ -2925,7 +2934,7 @@
};
};
sensor_thermal3: sensor-thermal3 {
sensor3_thermal: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;

27
arch/arm/dts/r8a7790-lager.dts
View file

@ -53,6 +53,9 @@
i2c11 = &i2cexio1;
i2c12 = &i2chdmi;
i2c13 = &i2cpwr;
mmc0 = &mmcif1;
mmc1 = &sdhi0;
mmc2 = &sdhi2;
};
chosen {
@ -78,6 +81,9 @@
keyboard {
compatible = "gpio-keys";
pinctrl-0 = <&keyboard_pins>;
pinctrl-names = "default";
one {
linux,code = <KEY_1>;
label = "SW2-1";
@ -343,7 +349,6 @@
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin1>;
port {
adv7180: endpoint {
@ -364,8 +369,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
@ -439,7 +442,7 @@
compatible = "dlg,da9063-rtc";
};
wdt {
watchdog {
compatible = "dlg,da9063-watchdog";
};
};
@ -659,10 +662,15 @@
groups = "audio_clk_a";
function = "audio_clk";
};
keyboard_pins: keyboard {
pins = "GP_1_14", "GP_1_24", "GP_1_26", "GP_1_28";
bias-pull-up;
};
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
@ -670,10 +678,13 @@
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
};
};
@ -910,7 +921,7 @@
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
@ -920,8 +931,8 @@
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src2 &dvc0>;
capture = <&ssi1 &src3 &dvc1>;
playback = <&ssi0>, <&src2>, <&dvc0>;
capture = <&ssi1>, <&src3>, <&dvc1>;
};
};
};

11
arch/arm/dts/r8a7790-stout.dts
View file

@ -191,7 +191,7 @@
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
@ -199,10 +199,13 @@
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
};
};
@ -296,8 +299,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
@ -322,7 +323,7 @@
&iic3 {
pinctrl-names = "default";
pinctrl-0 = <&iic3_pins &pmic_irq_pins>;
pinctrl-0 = <&iic3_pins>, <&pmic_irq_pins>;
status = "okay";
pmic@58 {
@ -340,7 +341,7 @@
compatible = "dlg,da9063-rtc";
};
wdt {
watchdog {
compatible = "dlg,da9063-watchdog";
};
};

45
arch/arm/dts/r8a7790.dtsi
View file

@ -69,7 +69,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@ -78,6 +77,7 @@
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@ -99,6 +99,7 @@
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@ -120,6 +121,7 @@
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@ -141,6 +143,7 @@
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@ -162,6 +165,7 @@
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
@ -173,6 +177,7 @@
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
@ -184,6 +189,7 @@
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
@ -195,6 +201,7 @@
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
@ -267,6 +274,7 @@
compatible = "renesas,r8a7790-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -363,7 +371,7 @@
resets = <&cpg 907>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7790";
reg = <0 0xe6060000 0 0x250>;
};
@ -381,13 +389,13 @@
apmu@e6151000 {
compatible = "renesas,r8a7790-apmu", "renesas,apmu";
reg = <0 0xe6151000 0 0x188>;
cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
apmu@e6152000 {
compatible = "renesas,r8a7790-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
rst: reset-controller@e6160000 {
@ -427,7 +435,7 @@
#thermal-sensor-cells = <0>;
};
ipmmu_sy0: mmu@e6280000 {
ipmmu_sy0: iommu@e6280000 {
compatible = "renesas,ipmmu-r8a7790",
"renesas,ipmmu-vmsa";
reg = <0 0xe6280000 0 0x1000>;
@ -437,7 +445,7 @@
status = "disabled";
};
ipmmu_sy1: mmu@e6290000 {
ipmmu_sy1: iommu@e6290000 {
compatible = "renesas,ipmmu-r8a7790",
"renesas,ipmmu-vmsa";
reg = <0 0xe6290000 0 0x1000>;
@ -446,7 +454,7 @@
status = "disabled";
};
ipmmu_ds: mmu@e6740000 {
ipmmu_ds: iommu@e6740000 {
compatible = "renesas,ipmmu-r8a7790",
"renesas,ipmmu-vmsa";
reg = <0 0xe6740000 0 0x1000>;
@ -456,7 +464,7 @@
status = "disabled";
};
ipmmu_mp: mmu@ec680000 {
ipmmu_mp: iommu@ec680000 {
compatible = "renesas,ipmmu-r8a7790",
"renesas,ipmmu-vmsa";
reg = <0 0xec680000 0 0x1000>;
@ -465,7 +473,7 @@
status = "disabled";
};
ipmmu_mx: mmu@fe951000 {
ipmmu_mx: iommu@fe951000 {
compatible = "renesas,ipmmu-r8a7790",
"renesas,ipmmu-vmsa";
reg = <0 0xfe951000 0 0x1000>;
@ -475,7 +483,7 @@
status = "disabled";
};
ipmmu_rt: mmu@ffc80000 {
ipmmu_rt: iommu@ffc80000 {
compatible = "renesas,ipmmu-r8a7790",
"renesas,ipmmu-vmsa";
reg = <0 0xffc80000 0 0x1000>;
@ -646,7 +654,7 @@
status = "disabled";
};
usbphy: usb-phy@e6590100 {
usbphy: usb-phy-controller@e6590100 {
compatible = "renesas,usb-phy-r8a7790",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
@ -658,11 +666,11 @@
resets = <&cpg 704>;
status = "disabled";
usb0: usb-channel@0 {
usb0: usb-phy@0 {
reg = <0>;
#phy-cells = <1>;
};
usb2: usb-channel@2 {
usb2: usb-phy@2 {
reg = <2>;
#phy-cells = <1>;
};
@ -768,6 +776,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
clock-names = "fck";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
@ -1467,7 +1476,7 @@
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@ -1482,7 +1491,7 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee120000 0 0x328>;
@ -1497,7 +1506,7 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@ -1512,7 +1521,7 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
@ -1719,6 +1728,8 @@
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>;
clock-names = "du.0", "du.1", "du.2";
resets = <&cpg 724>;
reset-names = "du.0";
status = "disabled";
ports {

27
arch/arm/dts/r8a7791-koelsch.dts
View file

@ -53,6 +53,9 @@
i2c12 = &i2cexio1;
i2c13 = &i2chdmi;
i2c14 = &i2cexio4;
mmc0 = &sdhi0;
mmc1 = &sdhi1;
mmc2 = &sdhi2;
};
chosen {
@ -78,6 +81,9 @@
keyboard {
compatible = "gpio-keys";
pinctrl-0 = <&keyboard_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
@ -366,7 +372,6 @@
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin1>;
port {
adv7180: endpoint {
@ -387,8 +392,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
@ -618,10 +621,15 @@
groups = "audio_clk_a";
function = "audio_clk";
};
keyboard_pins: keyboard {
pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3";
bias-pull-up;
};
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
@ -629,10 +637,13 @@
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
};
};
@ -794,7 +805,7 @@
compatible = "dlg,da9063-rtc";
};
wdt {
watchdog {
compatible = "dlg,da9063-watchdog";
};
};
@ -880,7 +891,7 @@
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
@ -890,8 +901,8 @@
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src2 &dvc0>;
capture = <&ssi1 &src3 &dvc1>;
playback = <&ssi0>, <&src2>, <&dvc0>;
capture = <&ssi1>, <&src3>, <&dvc1>;
};
};
};

14
arch/arm/dts/r8a7791-porter.dts
View file

@ -28,6 +28,8 @@
serial0 = &scif0;
i2c9 = &gpioi2c2;
i2c10 = &i2chdmi;
mmc0 = &sdhi0;
mmc1 = &sdhi2;
};
chosen {
@ -162,7 +164,6 @@
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {
@ -181,8 +182,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
@ -295,7 +294,7 @@
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
@ -303,10 +302,13 @@
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
};
};
@ -388,7 +390,7 @@
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
wdt {
watchdog {
compatible = "dlg,da9063-watchdog";
};
};
@ -496,7 +498,7 @@
};
&rcar_sound {
pinctrl-0 = <&ssi_pins &audio_clk_pins>;
pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>;
pinctrl-names = "default";
status = "okay";

121
arch/arm/dts/r8a7791.dtsi
View file

@ -68,7 +68,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@ -77,6 +76,7 @@
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
@ -97,6 +97,7 @@
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
@ -160,6 +161,7 @@
compatible = "renesas,r8a7791-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -286,11 +288,22 @@
resets = <&cpg 904>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7791";
reg = <0 0xe6060000 0 0x250>;
};
tpu: pwm@e60f0000 {
compatible = "renesas,tpu-r8a7791", "renesas,tpu";
reg = <0 0xe60f0000 0 0x148>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 304>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 304>;
#pwm-cells = <3>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7791-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@ -304,7 +317,7 @@
apmu@e6152000 {
compatible = "renesas,r8a7791-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
cpus = <&cpu0>, <&cpu1>;
};
rst: reset-controller@e6160000 {
@ -350,7 +363,7 @@
#thermal-sensor-cells = <0>;
};
ipmmu_sy0: mmu@e6280000 {
ipmmu_sy0: iommu@e6280000 {
compatible = "renesas,ipmmu-r8a7791",
"renesas,ipmmu-vmsa";
reg = <0 0xe6280000 0 0x1000>;
@ -360,7 +373,7 @@
status = "disabled";
};
ipmmu_sy1: mmu@e6290000 {
ipmmu_sy1: iommu@e6290000 {
compatible = "renesas,ipmmu-r8a7791",
"renesas,ipmmu-vmsa";
reg = <0 0xe6290000 0 0x1000>;
@ -369,7 +382,7 @@
status = "disabled";
};
ipmmu_ds: mmu@e6740000 {
ipmmu_ds: iommu@e6740000 {
compatible = "renesas,ipmmu-r8a7791",
"renesas,ipmmu-vmsa";
reg = <0 0xe6740000 0 0x1000>;
@ -379,7 +392,7 @@
status = "disabled";
};
ipmmu_mp: mmu@ec680000 {
ipmmu_mp: iommu@ec680000 {
compatible = "renesas,ipmmu-r8a7791",
"renesas,ipmmu-vmsa";
reg = <0 0xec680000 0 0x1000>;
@ -388,7 +401,7 @@
status = "disabled";
};
ipmmu_mx: mmu@fe951000 {
ipmmu_mx: iommu@fe951000 {
compatible = "renesas,ipmmu-r8a7791",
"renesas,ipmmu-vmsa";
reg = <0 0xfe951000 0 0x1000>;
@ -398,7 +411,7 @@
status = "disabled";
};
ipmmu_rt: mmu@ffc80000 {
ipmmu_rt: iommu@ffc80000 {
compatible = "renesas,ipmmu-r8a7791",
"renesas,ipmmu-vmsa";
reg = <0 0xffc80000 0 0x1000>;
@ -407,7 +420,7 @@
status = "disabled";
};
ipmmu_gp: mmu@e62a0000 {
ipmmu_gp: iommu@e62a0000 {
compatible = "renesas,ipmmu-r8a7791",
"renesas,ipmmu-vmsa";
reg = <0 0xe62a0000 0 0x1000>;
@ -595,7 +608,7 @@
status = "disabled";
};
usbphy: usb-phy@e6590100 {
usbphy: usb-phy-controller@e6590100 {
compatible = "renesas,usb-phy-r8a7791",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
@ -607,11 +620,11 @@
resets = <&cpg 704>;
status = "disabled";
usb0: usb-channel@0 {
usb0: usb-phy@0 {
reg = <0>;
#phy-cells = <1>;
};
usb2: usb-channel@2 {
usb2: usb-phy@2 {
reg = <2>;
#phy-cells = <1>;
};
@ -717,6 +730,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
clock-names = "fck";
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
@ -1067,6 +1081,76 @@
status = "disabled";
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm1: pwm@e6e31000 {
compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
reg = <0 0xe6e31000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm2: pwm@e6e32000 {
compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
reg = <0 0xe6e32000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm3: pwm@e6e33000 {
compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
reg = <0 0xe6e33000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm4: pwm@e6e34000 {
compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
reg = <0 0xe6e34000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm5: pwm@e6e35000 {
compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
reg = <0 0xe6e35000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
pwm6: pwm@e6e36000 {
compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
reg = <0 0xe6e36000 0 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
status = "disabled";
};
adc: adc@e6e54000 {
compatible = "renesas,r8a7791-gyroadc",
"renesas,rcar-gyroadc";
@ -1482,7 +1566,7 @@
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7791",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@ -1497,7 +1581,7 @@
status = "disabled";
};
sdhi1: sd@ee140000 {
sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7791",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@ -1512,7 +1596,7 @@
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7791",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
@ -1681,9 +1765,10 @@
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
resets = <&cpg 724>;
reset-names = "du.0";
status = "disabled";
ports {

14
arch/arm/dts/r8a7792-blanche.dts
View file

@ -112,6 +112,9 @@
keyboard {
compatible = "gpio-keys";
pinctrl-0 = <&keyboard_pins>;
pinctrl-names = "default";
key-1 {
linux,code = <KEY_1>;
label = "SW2-1";
@ -235,6 +238,11 @@
function = "du1";
};
keyboard_pins: keyboard {
pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_02";
bias-pull-up;
};
pmic_irq_pins: pmicirq {
groups = "intc_irq2";
function = "intc";
@ -289,8 +297,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
@ -329,14 +335,14 @@
compatible = "dlg,da9063-rtc";
};
wdt {
watchdog {
compatible = "dlg,da9063-watchdog";
};
};
};
&du {
pinctrl-0 = <&du0_pins &du1_pins>;
pinctrl-0 = <&du0_pins>, <&du1_pins>;
pinctrl-names = "default";
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>;

16
arch/arm/dts/r8a7792.dtsi
View file

@ -45,7 +45,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@ -54,6 +53,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
};
@ -64,6 +64,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
};
@ -110,6 +111,7 @@
compatible = "renesas,r8a7792-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -296,7 +298,7 @@
resets = <&cpg 913>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7792";
reg = <0 0xe6060000 0 0x144>;
};
@ -314,7 +316,7 @@
apmu@e6152000 {
compatible = "renesas,r8a7792-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
cpus = <&cpu0>, <&cpu1>;
};
rst: reset-controller@e6160000 {
@ -537,6 +539,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
clock-names = "fck";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
@ -780,7 +783,7 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7792",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@ -852,9 +855,10 @@
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
resets = <&cpg 724>;
reset-names = "du.0";
status = "disabled";
ports {

33
arch/arm/dts/r8a7793-gose.dts
View file

@ -49,6 +49,9 @@
i2c10 = &gpioi2c4;
i2c11 = &i2chdmi;
i2c12 = &i2cexio4;
mmc0 = &sdhi0;
mmc1 = &sdhi1;
mmc2 = &sdhi2;
};
chosen {
@ -61,9 +64,12 @@
reg = <0 0x40000000 0 0x40000000>;
};
gpio-keys {
keyboard {
compatible = "gpio-keys";
pinctrl-0 = <&keyboard_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
@ -334,9 +340,8 @@
composite-in@20 {
compatible = "adi,adv7180cp";
reg = <0x20>;
remote = <&vin1>;
port {
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -366,8 +371,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
@ -396,7 +399,7 @@
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
default-input = <0>;
port {
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -567,6 +570,11 @@
function = "audio_clk";
};
keyboard_pins: keyboard {
pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3";
bias-pull-up;
};
vin0_pins: vin0 {
groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
function = "vin0";
@ -579,7 +587,7 @@
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
@ -587,10 +595,13 @@
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
};
};
@ -729,7 +740,7 @@
compatible = "dlg,da9063-rtc";
};
wdt {
watchdog {
compatible = "dlg,da9063-watchdog";
};
};
@ -753,7 +764,7 @@
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
@ -763,8 +774,8 @@
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src2 &dvc0>;
capture = <&ssi1 &src3 &dvc1>;
playback = <&ssi0>, <&src2>, <&dvc0>;
capture = <&ssi1>, <&src3>, <&dvc1>;
};
};
};

33
arch/arm/dts/r8a7793.dtsi
View file

@ -60,7 +60,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@ -69,6 +68,7 @@
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
enable-method = "renesas,apmu";
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
@ -89,6 +89,7 @@
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
enable-method = "renesas,apmu";
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
@ -145,6 +146,7 @@
compatible = "renesas,r8a7793-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -271,7 +273,7 @@
resets = <&cpg 904>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7793";
reg = <0 0xe6060000 0 0x250>;
};
@ -290,7 +292,7 @@
apmu@e6152000 {
compatible = "renesas,r8a7793-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
cpus = <&cpu0>, <&cpu1>;
};
rst: reset-controller@e6160000 {
@ -336,7 +338,7 @@
#thermal-sensor-cells = <0>;
};
ipmmu_sy0: mmu@e6280000 {
ipmmu_sy0: iommu@e6280000 {
compatible = "renesas,ipmmu-r8a7793",
"renesas,ipmmu-vmsa";
reg = <0 0xe6280000 0 0x1000>;
@ -346,7 +348,7 @@
status = "disabled";
};
ipmmu_sy1: mmu@e6290000 {
ipmmu_sy1: iommu@e6290000 {
compatible = "renesas,ipmmu-r8a7793",
"renesas,ipmmu-vmsa";
reg = <0 0xe6290000 0 0x1000>;
@ -355,7 +357,7 @@
status = "disabled";
};
ipmmu_ds: mmu@e6740000 {
ipmmu_ds: iommu@e6740000 {
compatible = "renesas,ipmmu-r8a7793",
"renesas,ipmmu-vmsa";
reg = <0 0xe6740000 0 0x1000>;
@ -365,7 +367,7 @@
status = "disabled";
};
ipmmu_mp: mmu@ec680000 {
ipmmu_mp: iommu@ec680000 {
compatible = "renesas,ipmmu-r8a7793",
"renesas,ipmmu-vmsa";
reg = <0 0xec680000 0 0x1000>;
@ -374,7 +376,7 @@
status = "disabled";
};
ipmmu_mx: mmu@fe951000 {
ipmmu_mx: iommu@fe951000 {
compatible = "renesas,ipmmu-r8a7793",
"renesas,ipmmu-vmsa";
reg = <0 0xfe951000 0 0x1000>;
@ -384,7 +386,7 @@
status = "disabled";
};
ipmmu_rt: mmu@ffc80000 {
ipmmu_rt: iommu@ffc80000 {
compatible = "renesas,ipmmu-r8a7793",
"renesas,ipmmu-vmsa";
reg = <0 0xffc80000 0 0x1000>;
@ -393,7 +395,7 @@
status = "disabled";
};
ipmmu_gp: mmu@e62a0000 {
ipmmu_gp: iommu@e62a0000 {
compatible = "renesas,ipmmu-r8a7793",
"renesas,ipmmu-vmsa";
reg = <0 0xe62a0000 0 0x1000>;
@ -1227,7 +1229,7 @@
dma-channels = <13>;
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7793",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@ -1242,7 +1244,7 @@
status = "disabled";
};
sdhi1: sd@ee140000 {
sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7793",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@ -1257,7 +1259,7 @@
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7793",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
@ -1341,9 +1343,10 @@
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
resets = <&cpg 724>;
reset-names = "du.0";
status = "disabled";
ports {

53
arch/arm/dts/r8a7794-alt.dts
View file

@ -8,6 +8,7 @@
/dts-v1/;
#include "r8a7794.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Alt";
@ -19,6 +20,9 @@
i2c10 = &gpioi2c4;
i2c11 = &i2chdmi;
i2c12 = &i2cexio4;
mmc0 = &mmcif0;
mmc1 = &sdhi0;
mmc2 = &sdhi1;
};
chosen {
@ -91,6 +95,42 @@
#size-cells = <1>;
};
keyboard {
compatible = "gpio-keys";
pinctrl-0 = <&keyboard_pins>;
pinctrl-names = "default";
one {
linux,code = <KEY_1>;
label = "SW2-1";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
};
two {
linux,code = <KEY_2>;
label = "SW2-2";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
};
three {
linux,code = <KEY_3>;
label = "SW2-3";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
};
four {
linux,code = <KEY_4>;
label = "SW2-4";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
};
};
vga-encoder {
compatible = "adi,adv7123";
@ -167,7 +207,6 @@
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {
@ -317,6 +356,11 @@
groups = "usb1";
function = "usb1";
};
keyboard_pins: keyboard {
pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12";
bias-pull-up;
};
};
&cmt0 {
@ -331,7 +375,7 @@
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
@ -339,10 +383,13 @@
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
};
};
@ -416,7 +463,7 @@
compatible = "dlg,da9063-rtc";
};
wdt {
watchdog {
compatible = "dlg,da9063-watchdog";
};
};

26
arch/arm/dts/r8a7794-silk.dts
View file

@ -31,6 +31,8 @@
serial0 = &scif2;
i2c9 = &gpioi2c1;
i2c10 = &i2chdmi;
mmc0 = &mmcif0;
mmc1 = &sdhi1;
};
chosen {
@ -43,9 +45,12 @@
reg = <0 0x40000000 0 0x40000000>;
};
gpio-keys {
keyboard {
compatible = "gpio-keys";
pinctrl-0 = <&keyboard_pins>;
pinctrl-names = "default";
key-3 {
gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
@ -236,7 +241,6 @@
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {
@ -255,8 +259,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
@ -359,6 +361,11 @@
function = "du1";
};
keyboard_pins: keyboard {
pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12";
bias-pull-up;
};
ssi_pins: sound {
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
@ -382,7 +389,7 @@
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-0 = <&ether_pins>, <&phy1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
@ -390,10 +397,13 @@
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
};
};
@ -423,7 +433,7 @@
compatible = "dlg,da9063-rtc";
};
wdt {
watchdog {
compatible = "dlg,da9063-watchdog";
};
};
@ -520,7 +530,7 @@
};
&du {
pinctrl-0 = <&du0_pins &du1_pins>;
pinctrl-0 = <&du0_pins>, <&du1_pins>;
pinctrl-names = "default";
status = "okay";
@ -543,7 +553,7 @@
};
&rcar_sound {
pinctrl-0 = <&ssi_pins &audio_clk_pins>;
pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>;
pinctrl-names = "default";
status = "okay";

35
arch/arm/dts/r8a7794.dtsi
View file

@ -62,7 +62,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@ -71,6 +70,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
};
@ -81,6 +81,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
};
@ -127,6 +128,7 @@
compatible = "renesas,r8a7794-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -238,7 +240,7 @@
resets = <&cpg 905>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7794";
reg = <0 0xe6060000 0 0x11c>;
};
@ -256,7 +258,7 @@
apmu@e6151000 {
compatible = "renesas,r8a7794-apmu", "renesas,apmu";
reg = <0 0xe6151000 0 0x188>;
cpus = <&cpu0 &cpu1>;
cpus = <&cpu0>, <&cpu1>;
};
rst: reset-controller@e6160000 {
@ -290,7 +292,7 @@
resets = <&cpg 407>;
};
ipmmu_sy0: mmu@e6280000 {
ipmmu_sy0: iommu@e6280000 {
compatible = "renesas,ipmmu-r8a7794",
"renesas,ipmmu-vmsa";
reg = <0 0xe6280000 0 0x1000>;
@ -300,7 +302,7 @@
status = "disabled";
};
ipmmu_sy1: mmu@e6290000 {
ipmmu_sy1: iommu@e6290000 {
compatible = "renesas,ipmmu-r8a7794",
"renesas,ipmmu-vmsa";
reg = <0 0xe6290000 0 0x1000>;
@ -309,7 +311,7 @@
status = "disabled";
};
ipmmu_ds: mmu@e6740000 {
ipmmu_ds: iommu@e6740000 {
compatible = "renesas,ipmmu-r8a7794",
"renesas,ipmmu-vmsa";
reg = <0 0xe6740000 0 0x1000>;
@ -319,7 +321,7 @@
status = "disabled";
};
ipmmu_mp: mmu@ec680000 {
ipmmu_mp: iommu@ec680000 {
compatible = "renesas,ipmmu-r8a7794",
"renesas,ipmmu-vmsa";
reg = <0 0xec680000 0 0x1000>;
@ -328,7 +330,7 @@
status = "disabled";
};
ipmmu_mx: mmu@fe951000 {
ipmmu_mx: iommu@fe951000 {
compatible = "renesas,ipmmu-r8a7794",
"renesas,ipmmu-vmsa";
reg = <0 0xfe951000 0 0x1000>;
@ -338,7 +340,7 @@
status = "disabled";
};
ipmmu_gp: mmu@e62a0000 {
ipmmu_gp: iommu@e62a0000 {
compatible = "renesas,ipmmu-r8a7794",
"renesas,ipmmu-vmsa";
reg = <0 0xe62a0000 0 0x1000>;
@ -504,7 +506,7 @@
status = "disabled";
};
usbphy: usb-phy@e6590100 {
usbphy: usb-phy-controller@e6590100 {
compatible = "renesas,usb-phy-r8a7794",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
@ -516,11 +518,11 @@
resets = <&cpg 704>;
status = "disabled";
usb0: usb-channel@0 {
usb0: usb-phy@0 {
reg = <0>;
#phy-cells = <1>;
};
usb2: usb-channel@2 {
usb2: usb-phy@2 {
reg = <2>;
#phy-cells = <1>;
};
@ -598,6 +600,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
clock-names = "fck";
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
@ -1232,7 +1235,7 @@
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7794",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@ -1247,7 +1250,7 @@
status = "disabled";
};
sdhi1: sd@ee140000 {
sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7794",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@ -1262,7 +1265,7 @@
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7794",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
@ -1356,6 +1359,8 @@
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
resets = <&cpg 724>;
reset-names = "du.0";
status = "disabled";
ports {

108
arch/arm/dts/r8a77950-salvator-x.dts
View file

@ -47,111 +47,3 @@
clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
&ehci2 {
status = "okay";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&hdmi1 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi1_out: endpoint {
remote-endpoint = <&hdmi1_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi1_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint2>;
};
};
};
};
&hdmi1_con {
remote-endpoint = <&rcar_dw_hdmi1_out>;
};
&ohci2 {
status = "okay";
};
&pfc {
usb2_pins: usb2 {
groups = "usb2";
function = "usb2";
};
};
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
rsnd_port2: port@2 {
reg = <2>;
rsnd_endpoint2: endpoint {
remote-endpoint = <&dw_hdmi1_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint2>;
frame-master = <&rsnd_endpoint2>;
playback = <&ssi3>;
};
};
};
};
&sata {
status = "okay";
};
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1 /* HDMI0 */
&rsnd_port2>; /* HDMI1 */
};
&usb2_phy2 {
pinctrl-0 = <&usb2_pins>;
pinctrl-names = "default";
status = "okay";
};

2
arch/arm/dts/r8a77950-ulcb.dts
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
* Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board with R-Car H3 ES1.x
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.

27
arch/arm/dts/r8a77950.dtsi
View file

@ -7,6 +7,8 @@
#include "r8a77951.dtsi"
#undef SOC_HAS_USB2_CH3
&audma0 {
iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>,
<&ipmmu_mp1 2>, <&ipmmu_mp1 3>,
@ -29,8 +31,13 @@
<&ipmmu_mp1 30>, <&ipmmu_mp1 31>;
};
&cluster0_opp {
/delete-node/ opp-1600000000;
/delete-node/ opp-1700000000;
};
&du {
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>;
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>;
};
&fcpvb1 {
@ -77,7 +84,7 @@
/delete-node/ dma-controller@e6460000;
/delete-node/ dma-controller@e6470000;
ipmmu_mp1: mmu@ec680000 {
ipmmu_mp1: iommu@ec680000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xec680000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 5>;
@ -85,7 +92,7 @@
#iommu-cells = <1>;
};
ipmmu_sy: mmu@e7730000 {
ipmmu_sy: iommu@e7730000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xe7730000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>;
@ -93,11 +100,11 @@
#iommu-cells = <1>;
};
/delete-node/ mmu@fd950000;
/delete-node/ mmu@fd960000;
/delete-node/ mmu@fd970000;
/delete-node/ mmu@febe0000;
/delete-node/ mmu@fe980000;
/delete-node/ iommu@fd950000;
/delete-node/ iommu@fd960000;
/delete-node/ iommu@fd970000;
/delete-node/ iommu@febe0000;
/delete-node/ iommu@fe980000;
xhci1: usb@ee040000 {
compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
@ -187,6 +194,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;

259
arch/arm/dts/r8a77951.dtsi
View file

@ -11,22 +11,16 @@
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
#define SOC_HAS_HDMI1
#define SOC_HAS_SATA
#define SOC_HAS_USB2_CH2
#define SOC_HAS_USB2_CH3
/ {
compatible = "renesas,r8a7795";
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
};
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
@ -57,7 +51,7 @@
clock-frequency = <0>;
};
cluster0_opp: opp_table0 {
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@ -91,7 +85,7 @@
};
};
cluster1_opp: opp_table1 {
cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
@ -364,6 +358,7 @@
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -490,7 +485,7 @@
resets = <&cpg 905>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7795";
reg = <0 0xe6060000 0 0x50c>;
};
@ -616,6 +611,71 @@
resets = <&cpg 407>;
};
tmu0: timer@e61e0000 {
compatible = "renesas,tmu-r8a7795", "renesas,tmu";
reg = <0 0xe61e0000 0 0x30>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 125>;
status = "disabled";
};
tmu1: timer@e6fc0000 {
compatible = "renesas,tmu-r8a7795", "renesas,tmu";
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 124>;
status = "disabled";
};
tmu2: timer@e6fd0000 {
compatible = "renesas,tmu-r8a7795", "renesas,tmu";
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 123>;
status = "disabled";
};
tmu3: timer@e6fe0000 {
compatible = "renesas,tmu-r8a7795", "renesas,tmu";
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 122>;
status = "disabled";
};
tmu4: timer@ffc00000 {
compatible = "renesas,tmu-r8a7795", "renesas,tmu";
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 121>;
status = "disabled";
};
i2c0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
@ -1073,7 +1133,7 @@
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
};
ipmmu_ds0: mmu@e6740000 {
ipmmu_ds0: iommu@e6740000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xe6740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
@ -1081,7 +1141,7 @@
#iommu-cells = <1>;
};
ipmmu_ds1: mmu@e7740000 {
ipmmu_ds1: iommu@e7740000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
@ -1089,7 +1149,7 @@
#iommu-cells = <1>;
};
ipmmu_hc: mmu@e6570000 {
ipmmu_hc: iommu@e6570000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xe6570000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 2>;
@ -1097,7 +1157,7 @@
#iommu-cells = <1>;
};
ipmmu_ir: mmu@ff8b0000 {
ipmmu_ir: iommu@ff8b0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xff8b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 3>;
@ -1105,7 +1165,7 @@
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 {
ipmmu_mm: iommu@e67b0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
@ -1114,7 +1174,7 @@
#iommu-cells = <1>;
};
ipmmu_mp0: mmu@ec670000 {
ipmmu_mp0: iommu@ec670000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xec670000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
@ -1122,7 +1182,7 @@
#iommu-cells = <1>;
};
ipmmu_pv0: mmu@fd800000 {
ipmmu_pv0: iommu@fd800000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfd800000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 6>;
@ -1130,7 +1190,7 @@
#iommu-cells = <1>;
};
ipmmu_pv1: mmu@fd950000 {
ipmmu_pv1: iommu@fd950000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfd950000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 7>;
@ -1138,7 +1198,7 @@
#iommu-cells = <1>;
};
ipmmu_pv2: mmu@fd960000 {
ipmmu_pv2: iommu@fd960000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfd960000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>;
@ -1146,7 +1206,7 @@
#iommu-cells = <1>;
};
ipmmu_pv3: mmu@fd970000 {
ipmmu_pv3: iommu@fd970000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfd970000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 9>;
@ -1154,7 +1214,7 @@
#iommu-cells = <1>;
};
ipmmu_rt: mmu@ffc80000 {
ipmmu_rt: iommu@ffc80000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 10>;
@ -1162,7 +1222,7 @@
#iommu-cells = <1>;
};
ipmmu_vc0: mmu@fe6b0000 {
ipmmu_vc0: iommu@fe6b0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
@ -1170,7 +1230,7 @@
#iommu-cells = <1>;
};
ipmmu_vc1: mmu@fe6f0000 {
ipmmu_vc1: iommu@fe6f0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfe6f0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 13>;
@ -1178,7 +1238,7 @@
#iommu-cells = <1>;
};
ipmmu_vi0: mmu@febd0000 {
ipmmu_vi0: iommu@febd0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 14>;
@ -1186,7 +1246,7 @@
#iommu-cells = <1>;
};
ipmmu_vi1: mmu@febe0000 {
ipmmu_vi1: iommu@febe0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfebe0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 15>;
@ -1194,7 +1254,7 @@
#iommu-cells = <1>;
};
ipmmu_vp0: mmu@fe990000 {
ipmmu_vp0: iommu@fe990000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfe990000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 16>;
@ -1202,7 +1262,7 @@
#iommu-cells = <1>;
};
ipmmu_vp1: mmu@fe980000 {
ipmmu_vp1: iommu@fe980000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfe980000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 17>;
@ -1247,9 +1307,12 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
@ -1294,6 +1357,7 @@
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A7795_CLK_CANFD>,
<&can_clk>;
@ -1945,12 +2009,12 @@
* clkout : #clock-cells = <0>; <&rcar_sound>;
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
*/
compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
@ -2204,7 +2268,7 @@
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dmas = <&audma0 0x71>, <&audma1 0x72>;
dmas = <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx";
};
ssiu41: ssiu-33 {
@ -2339,6 +2403,18 @@
};
};
mlp: mlp@ec520000 {
compatible = "renesas,r8a7795-mlp",
"renesas,rcar-gen3-mlp";
reg = <0 0xec520000 0 0x800>;
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 802>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 802>;
status = "disabled";
};
audma0: dma-controller@ec700000 {
compatible = "renesas,dmac-r8a7795",
"renesas,rcar-dmac";
@ -2590,12 +2666,13 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 314>;
@ -2603,12 +2680,13 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7795_CLK_SD1H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 313>;
@ -2616,12 +2694,13 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 312>;
@ -2629,12 +2708,13 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7795_CLK_SD3H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 311>;
@ -2642,6 +2722,22 @@
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a7795-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x04000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
sata: sata@ee300000 {
compatible = "renesas,sata-r8a7795",
"renesas,rcar-gen3-sata";
@ -2725,6 +2821,44 @@
status = "disabled";
};
pciec0_ep: pcie-ep@fe000000 {
compatible = "renesas,r8a7795-pcie-ep",
"renesas,rcar-gen3-pcie-ep";
reg = <0x0 0xfe000000 0 0x80000>,
<0x0 0xfe100000 0 0x100000>,
<0x0 0xfe200000 0 0x200000>,
<0x0 0x30000000 0 0x8000000>,
<0x0 0x38000000 0 0x8000000>;
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 319>;
clock-names = "pcie";
resets = <&cpg 319>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
status = "disabled";
};
pciec1_ep: pcie-ep@ee800000 {
compatible = "renesas,r8a7795-pcie-ep",
"renesas,rcar-gen3-pcie-ep";
reg = <0x0 0xee800000 0 0x80000>,
<0x0 0xee900000 0 0x100000>,
<0x0 0xeea00000 0 0x200000>,
<0x0 0xc0000000 0 0x8000000>,
<0x0 0xc8000000 0 0x8000000>;
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 318>;
clock-names = "pcie";
resets = <&cpg 318>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
status = "disabled";
};
imr-lx4@fe860000 {
compatible = "renesas,r8a7795-imr-lx4",
"renesas,imr-lx4";
@ -2992,6 +3126,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -3047,6 +3185,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -3086,6 +3228,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -3177,14 +3323,15 @@
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>;
clock-names = "du.0", "du.1", "du.2", "du.3";
resets = <&cpg 724>, <&cpg 722>;
reset-names = "du.0", "du.2";
renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>,
<&vspd0 1>;
status = "disabled";
@ -3194,8 +3341,6 @@
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
@ -3238,8 +3383,6 @@
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
@ -3251,7 +3394,7 @@
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -3266,7 +3409,7 @@
};
};
sensor_thermal2: sensor-thermal2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@ -3281,7 +3424,7 @@
};
};
sensor_thermal3: sensor-thermal3 {
sensor3_thermal: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;

46
arch/arm/dts/r8a77960-salvator-x.dts
View file

@ -35,49 +35,3 @@
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};
};
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1>; /* HDMI0 */
};

2
arch/arm/dts/r8a77960-ulcb.dts
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board
* Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board with R-Car M3-W
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.

212
arch/arm/dts/r8a77960.dtsi
View file

@ -16,17 +16,6 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
};
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
@ -57,24 +46,25 @@
clock-frequency = <0>;
};
cluster0_opp: opp_table0 {
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <820000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <820000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
@ -96,7 +86,7 @@
};
};
cluster1_opp: opp_table1 {
cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
@ -333,6 +323,7 @@
compatible = "renesas,r8a7796-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -459,7 +450,7 @@
resets = <&cpg 905>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7796";
reg = <0 0xe6060000 0 0x50c>;
};
@ -585,6 +576,71 @@
resets = <&cpg 407>;
};
tmu0: timer@e61e0000 {
compatible = "renesas,tmu-r8a7796", "renesas,tmu";
reg = <0 0xe61e0000 0 0x30>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 125>;
status = "disabled";
};
tmu1: timer@e6fc0000 {
compatible = "renesas,tmu-r8a7796", "renesas,tmu";
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 124>;
status = "disabled";
};
tmu2: timer@e6fd0000 {
compatible = "renesas,tmu-r8a7796", "renesas,tmu";
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 123>;
status = "disabled";
};
tmu3: timer@e6fe0000 {
compatible = "renesas,tmu-r8a7796", "renesas,tmu";
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 122>;
status = "disabled";
};
tmu4: timer@ffc00000 {
compatible = "renesas,tmu-r8a7796", "renesas,tmu";
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 121>;
status = "disabled";
};
i2c0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
@ -862,6 +918,15 @@
status = "disabled";
};
arm_cc630p: crypto@e6601000 {
compatible = "arm,cryptocell-630p-ree";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xe6601000 0 0x1000>;
clocks = <&cpg CPG_MOD 229>;
resets = <&cpg 229>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7796",
"renesas,rcar-dmac";
@ -988,7 +1053,7 @@
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
};
ipmmu_ds0: mmu@e6740000 {
ipmmu_ds0: iommu@e6740000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xe6740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
@ -996,7 +1061,7 @@
#iommu-cells = <1>;
};
ipmmu_ds1: mmu@e7740000 {
ipmmu_ds1: iommu@e7740000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
@ -1004,7 +1069,7 @@
#iommu-cells = <1>;
};
ipmmu_hc: mmu@e6570000 {
ipmmu_hc: iommu@e6570000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xe6570000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 2>;
@ -1012,7 +1077,7 @@
#iommu-cells = <1>;
};
ipmmu_ir: mmu@ff8b0000 {
ipmmu_ir: iommu@ff8b0000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xff8b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 3>;
@ -1020,7 +1085,7 @@
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 {
ipmmu_mm: iommu@e67b0000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
@ -1029,7 +1094,7 @@
#iommu-cells = <1>;
};
ipmmu_mp: mmu@ec670000 {
ipmmu_mp: iommu@ec670000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xec670000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
@ -1037,7 +1102,7 @@
#iommu-cells = <1>;
};
ipmmu_pv0: mmu@fd800000 {
ipmmu_pv0: iommu@fd800000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xfd800000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 5>;
@ -1045,7 +1110,7 @@
#iommu-cells = <1>;
};
ipmmu_pv1: mmu@fd950000 {
ipmmu_pv1: iommu@fd950000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xfd950000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 6>;
@ -1053,7 +1118,7 @@
#iommu-cells = <1>;
};
ipmmu_rt: mmu@ffc80000 {
ipmmu_rt: iommu@ffc80000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 7>;
@ -1061,7 +1126,7 @@
#iommu-cells = <1>;
};
ipmmu_vc0: mmu@fe6b0000 {
ipmmu_vc0: iommu@fe6b0000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>;
@ -1069,7 +1134,7 @@
#iommu-cells = <1>;
};
ipmmu_vi0: mmu@febd0000 {
ipmmu_vi0: iommu@febd0000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 9>;
@ -1114,9 +1179,12 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
@ -1161,6 +1229,7 @@
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A7796_CLK_CANFD>,
<&can_clk>;
@ -1812,12 +1881,12 @@
* clkout : #clock-cells = <0>; <&rcar_sound>;
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
*/
compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
@ -2124,7 +2193,7 @@
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dmas = <&audma0 0x71>, <&audma1 0x72>;
dmas = <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx";
};
ssiu41: ssiu-33 {
@ -2206,6 +2275,18 @@
};
};
mlp: mlp@ec520000 {
compatible = "renesas,r8a7796-mlp",
"renesas,rcar-gen3-mlp";
reg = <0 0xec520000 0 0x800>;
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 802>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 802>;
status = "disabled";
};
audma0: dma-controller@ec700000 {
compatible = "renesas,dmac-r8a7796",
"renesas,rcar-dmac";
@ -2385,12 +2466,13 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7796_CLK_SD0H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 314>;
@ -2398,12 +2480,13 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7796_CLK_SD1H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 313>;
@ -2411,12 +2494,13 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7796_CLK_SD2H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 312>;
@ -2424,12 +2508,13 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7796_CLK_SD3H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 311>;
@ -2437,6 +2522,22 @@
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a7796-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x04000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@ -2685,6 +2786,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -2740,6 +2845,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -2818,13 +2927,14 @@
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>;
clock-names = "du.0", "du.1", "du.2";
resets = <&cpg 724>, <&cpg 722>;
reset-names = "du.0", "du.2";
renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
status = "disabled";
@ -2834,8 +2944,6 @@
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
@ -2872,8 +2980,6 @@
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
@ -2885,7 +2991,7 @@
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -2900,7 +3006,7 @@
};
};
sensor_thermal2: sensor-thermal2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@ -2915,7 +3021,7 @@
};
};
sensor_thermal3: sensor-thermal3 {
sensor3_thermal: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;

45
arch/arm/dts/r8a77965-salvator-x.dts
View file

@ -30,48 +30,3 @@
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&rcar_sound {
ports {
rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};
};
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1>; /* HDMI0 */
};

2
arch/arm/dts/r8a77965-ulcb.dts
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board
* Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board with R-Car M3-N
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.

338
arch/arm/dts/r8a77965.dtsi
View file

@ -14,22 +14,13 @@
#define CPG_AUDIO_CLK_I R8A77965_CLK_S0D4
#define SOC_HAS_SATA
/ {
compatible = "renesas,r8a77965";
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
};
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
@ -60,7 +51,7 @@
clock-frequency = <0>;
};
cluster0_opp: opp_table0 {
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@ -111,6 +102,7 @@
power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
#cooling-cells = <2>;
dynamic-power-coefficient = <854>;
clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
@ -124,6 +116,7 @@
power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
};
@ -134,6 +127,19 @@
cache-unified;
cache-level = <2>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <400>;
exit-latency-us = <500>;
min-residency-us = <4000>;
};
};
};
extal_clk: extal {
@ -188,6 +194,7 @@
compatible = "renesas,r8a77965-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -314,7 +321,7 @@
resets = <&cpg 905>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a77965";
reg = <0 0xe6060000 0 0x50c>;
};
@ -440,6 +447,71 @@
resets = <&cpg 407>;
};
tmu0: timer@e61e0000 {
compatible = "renesas,tmu-r8a77965", "renesas,tmu";
reg = <0 0xe61e0000 0 0x30>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 125>;
status = "disabled";
};
tmu1: timer@e6fc0000 {
compatible = "renesas,tmu-r8a77965", "renesas,tmu";
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 124>;
status = "disabled";
};
tmu2: timer@e6fd0000 {
compatible = "renesas,tmu-r8a77965", "renesas,tmu";
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 123>;
status = "disabled";
};
tmu3: timer@e6fe0000 {
compatible = "renesas,tmu-r8a77965", "renesas,tmu";
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 122>;
status = "disabled";
};
tmu4: timer@ffc00000 {
compatible = "renesas,tmu-r8a77965", "renesas,tmu";
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 121>;
status = "disabled";
};
i2c0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
@ -717,6 +789,15 @@
status = "disabled";
};
arm_cc630p: crypto@e6601000 {
compatible = "arm,cryptocell-630p-ree";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xe6601000 0 0x1000>;
clocks = <&cpg CPG_MOD 229>;
resets = <&cpg 229>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a77965",
"renesas,rcar-dmac";
@ -843,7 +924,7 @@
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
};
ipmmu_ds0: mmu@e6740000 {
ipmmu_ds0: iommu@e6740000 {
compatible = "renesas,ipmmu-r8a77965";
reg = <0 0xe6740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
@ -851,7 +932,7 @@
#iommu-cells = <1>;
};
ipmmu_ds1: mmu@e7740000 {
ipmmu_ds1: iommu@e7740000 {
compatible = "renesas,ipmmu-r8a77965";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
@ -859,7 +940,7 @@
#iommu-cells = <1>;
};
ipmmu_hc: mmu@e6570000 {
ipmmu_hc: iommu@e6570000 {
compatible = "renesas,ipmmu-r8a77965";
reg = <0 0xe6570000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 2>;
@ -867,7 +948,7 @@
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 {
ipmmu_mm: iommu@e67b0000 {
compatible = "renesas,ipmmu-r8a77965";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
@ -876,7 +957,7 @@
#iommu-cells = <1>;
};
ipmmu_mp: mmu@ec670000 {
ipmmu_mp: iommu@ec670000 {
compatible = "renesas,ipmmu-r8a77965";
reg = <0 0xec670000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
@ -884,7 +965,7 @@
#iommu-cells = <1>;
};
ipmmu_pv0: mmu@fd800000 {
ipmmu_pv0: iommu@fd800000 {
compatible = "renesas,ipmmu-r8a77965";
reg = <0 0xfd800000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 6>;
@ -892,7 +973,7 @@
#iommu-cells = <1>;
};
ipmmu_rt: mmu@ffc80000 {
ipmmu_rt: iommu@ffc80000 {
compatible = "renesas,ipmmu-r8a77965";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 10>;
@ -900,7 +981,7 @@
#iommu-cells = <1>;
};
ipmmu_vc0: mmu@fe6b0000 {
ipmmu_vc0: iommu@fe6b0000 {
compatible = "renesas,ipmmu-r8a77965";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
@ -908,7 +989,7 @@
#iommu-cells = <1>;
};
ipmmu_vi0: mmu@febd0000 {
ipmmu_vi0: iommu@febd0000 {
compatible = "renesas,ipmmu-r8a77965";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 14>;
@ -916,7 +997,7 @@
#iommu-cells = <1>;
};
ipmmu_vp0: mmu@fe990000 {
ipmmu_vp0: iommu@fe990000 {
compatible = "renesas,ipmmu-r8a77965";
reg = <0 0xfe990000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 16>;
@ -961,9 +1042,12 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
@ -1008,6 +1092,7 @@
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77965_CLK_CANFD>,
<&can_clk>;
@ -1526,6 +1611,126 @@
};
};
drif00: rif@e6f40000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f40000 0 0x84>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 515>;
clock-names = "fck";
dmas = <&dmac1 0x20>, <&dmac2 0x20>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 515>;
renesas,bonding = <&drif01>;
status = "disabled";
};
drif01: rif@e6f50000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f50000 0 0x84>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>;
clock-names = "fck";
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 514>;
renesas,bonding = <&drif00>;
status = "disabled";
};
drif10: rif@e6f60000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f60000 0 0x84>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 513>;
clock-names = "fck";
dmas = <&dmac1 0x24>, <&dmac2 0x24>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 513>;
renesas,bonding = <&drif11>;
status = "disabled";
};
drif11: rif@e6f70000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f70000 0 0x84>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 512>;
clock-names = "fck";
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 512>;
renesas,bonding = <&drif10>;
status = "disabled";
};
drif20: rif@e6f80000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f80000 0 0x84>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 511>;
clock-names = "fck";
dmas = <&dmac1 0x28>, <&dmac2 0x28>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 511>;
renesas,bonding = <&drif21>;
status = "disabled";
};
drif21: rif@e6f90000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f90000 0 0x84>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 510>;
clock-names = "fck";
dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 510>;
renesas,bonding = <&drif20>;
status = "disabled";
};
drif30: rif@e6fa0000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6fa0000 0 0x84>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 509>;
clock-names = "fck";
dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 509>;
renesas,bonding = <&drif31>;
status = "disabled";
};
drif31: rif@e6fb0000 {
compatible = "renesas,r8a77965-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6fb0000 0 0x84>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 508>;
clock-names = "fck";
dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 508>;
renesas,bonding = <&drif30>;
status = "disabled";
};
rcar_sound: sound@ec500000 {
/*
* #sound-dai-cells is required
@ -1539,12 +1744,12 @@
* clkout : #clock-cells = <0>; <&rcar_sound>;
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
*/
compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
@ -1798,7 +2003,7 @@
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dmas = <&audma0 0x71>, <&audma1 0x72>;
dmas = <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx";
};
ssiu41: ssiu-33 {
@ -1933,6 +2138,18 @@
};
};
mlp: mlp@ec520000 {
compatible = "renesas,r8a77965-mlp",
"renesas,rcar-gen3-mlp";
reg = <0 0xec520000 0 0x800>;
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 802>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 802>;
status = "disabled";
};
audma0: dma-controller@ec700000 {
compatible = "renesas,dmac-r8a77965",
"renesas,rcar-dmac";
@ -2096,12 +2313,13 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a77965",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77965_CLK_SD0H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 314>;
@ -2109,12 +2327,13 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a77965",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77965_CLK_SD1H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 313>;
@ -2122,12 +2341,13 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a77965",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77965_CLK_SD2H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 312>;
@ -2135,12 +2355,13 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a77965",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77965_CLK_SD3H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 311>;
@ -2148,6 +2369,22 @@
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a77965-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x04000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
sata: sata@ee300000 {
compatible = "renesas,sata-r8a77965",
"renesas,rcar-gen3-sata";
@ -2364,6 +2601,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -2419,6 +2660,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -2494,13 +2739,14 @@
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>;
clock-names = "du.0", "du.1", "du.3";
resets = <&cpg 724>, <&cpg 722>;
reset-names = "du.0", "du.3";
renesas,cmms = <&cmm0>, <&cmm1>, <&cmm3>;
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
status = "disabled";
@ -2510,8 +2756,6 @@
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
@ -2548,8 +2792,6 @@
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
@ -2561,7 +2803,7 @@
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -2576,7 +2818,7 @@
};
};
sensor_thermal2: sensor-thermal2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@ -2591,7 +2833,7 @@
};
};
sensor_thermal3: sensor-thermal3 {
sensor3_thermal: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;

193
arch/arm/dts/r8a77970-eagle.dts
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Eagle board
* Device Tree Source for the Eagle board with R-Car V3M
*
* Copyright (C) 2016-2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
@ -8,12 +8,18 @@
/dts-v1/;
#include "r8a77970.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas Eagle board based on r8a77970";
compatible = "renesas,eagle", "renesas,r8a77970";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
serial0 = &scif0;
ethernet0 = &avb;
};
@ -73,6 +79,12 @@
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
x1_clk: x1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
};
&avb {
@ -81,14 +93,18 @@
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
rx-internal-delay-ps = <1800>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
};
@ -102,7 +118,23 @@
};
};
&csi40 {
status = "okay";
ports {
port@0 {
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max9286_out0>;
};
};
};
};
&du {
clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
@ -137,8 +169,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
@ -161,6 +191,89 @@
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
gmsl0: gmsl-deserializer@48 {
compatible = "maxim,max9286";
reg = <0x48>;
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
port@3 {
reg = <3>;
};
port@4 {
reg = <4>;
max9286_out0: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "disabled";
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
status = "disabled";
};
};
};
};
&lvds0 {
status = "okay";
@ -189,12 +302,84 @@
function = "i2c0";
};
i2c3_pins: i2c3 {
groups = "i2c3_a";
function = "i2c3";
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert_header_sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";

53
arch/arm/dts/r8a77970.dtsi
View file

@ -16,14 +16,6 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
@ -108,6 +100,7 @@
compatible = "renesas,r8a77970-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -204,7 +197,7 @@
resets = <&cpg 907>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a77970";
reg = <0 0xe6060000 0 0x504>;
};
@ -556,6 +549,7 @@
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77970_CLK_CANFD>,
<&can_clk>;
@ -612,9 +606,12 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
iommus = <&ipmmu_rt 3>;
#address-cells = <1>;
#size-cells = <0>;
@ -985,7 +982,7 @@
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
};
ipmmu_ds1: mmu@e7740000 {
ipmmu_ds1: iommu@e7740000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
@ -993,7 +990,7 @@
#iommu-cells = <1>;
};
ipmmu_ir: mmu@ff8b0000 {
ipmmu_ir: iommu@ff8b0000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xff8b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 3>;
@ -1001,7 +998,7 @@
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 {
ipmmu_mm: iommu@e67b0000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
@ -1010,7 +1007,7 @@
#iommu-cells = <1>;
};
ipmmu_rt: mmu@ffc80000 {
ipmmu_rt: iommu@ffc80000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 7>;
@ -1018,7 +1015,7 @@
#iommu-cells = <1>;
};
ipmmu_vi0: mmu@febd0000 {
ipmmu_vi0: iommu@febd0000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 9>;
@ -1039,6 +1036,22 @@
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a77970-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x4000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@ -1087,6 +1100,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -1121,7 +1138,9 @@
clock-names = "du.0";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 724>;
vsps = <&vspd0 0>;
reset-names = "du.0";
renesas,vsps = <&vspd0 0>;
status = "disabled";
ports {
@ -1130,8 +1149,6 @@
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
@ -1164,8 +1181,6 @@
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};

274
arch/arm/dts/r8a77980-condor.dts
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Condor board
* Device Tree Source for the Condor board with R-Car V3H
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
@ -8,279 +8,9 @@
/dts-v1/;
#include "r8a77980.dtsi"
#include "condor-common.dtsi"
/ {
model = "Renesas Condor board based on r8a77980";
compatible = "renesas,condor", "renesas,r8a77980";
aliases {
serial0 = &scif0;
ethernet0 = &gether;
};
chosen {
stdout-path = "serial0:115200n8";
};
d1_8v: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "D1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
d3_3v: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&d3_3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0 0x48000000 0 0x78000000>;
};
vddq_vin01: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VDDQ_VIN01";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
x1_clk: x1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
};
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&x1_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&gether {
pinctrl-0 = <&gether_pins>;
pinctrl-names = "default";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
renesas,no-ether-link;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
};
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
io_expander0: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
io_expander1: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&d1_8v>;
dvdd-supply = <&d1_8v>;
pvdd-supply = <&d1_8v>;
bgvdd-supply = <&d1_8v>;
dvdd-3v-supply = <&d3_3v>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&d3_3v>;
vqmmc-supply = <&vddq_vin01>;
mmc-hs200-1_8v;
bus-width = <8>;
non-removable;
status = "okay";
};
&pciec {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pcie_phy {
status = "okay";
};
&pfc {
canfd0_pins: canfd0 {
groups = "canfd0_data_a";
function = "canfd0";
};
gether_pins: gether {
groups = "gether_mdio_a", "gether_rgmii",
"gether_txcrefclk", "gether_txcrefclk_mega";
function = "gether";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_b";
function = "scif_clk";
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};

92
arch/arm/dts/r8a77980.dtsi
View file

@ -16,15 +16,6 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
@ -138,6 +129,7 @@
compatible = "renesas,r8a77980-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -234,7 +226,7 @@
resets = <&cpg 907>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a77980";
reg = <0 0xe6060000 0 0x50c>;
};
@ -608,6 +600,7 @@
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77980_CLK_CANFD>,
<&can_clk>;
@ -664,9 +657,12 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
clock-names = "fck";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <2000>;
iommus = <&ipmmu_ds1 33>;
#address-cells = <1>;
#size-cells = <0>;
@ -990,8 +986,8 @@
reg = <1>;
vin4csi41: endpoint@2 {
reg = <2>;
vin4csi41: endpoint@3 {
reg = <3>;
remote-endpoint = <&csi41vin4>;
};
};
@ -1018,8 +1014,8 @@
reg = <1>;
vin5csi41: endpoint@2 {
reg = <2>;
vin5csi41: endpoint@3 {
reg = <3>;
remote-endpoint = <&csi41vin5>;
};
};
@ -1046,8 +1042,8 @@
reg = <1>;
vin6csi41: endpoint@2 {
reg = <2>;
vin6csi41: endpoint@3 {
reg = <3>;
remote-endpoint = <&csi41vin6>;
};
};
@ -1074,8 +1070,8 @@
reg = <1>;
vin7csi41: endpoint@2 {
reg = <2>;
vin7csi41: endpoint@3 {
reg = <3>;
remote-endpoint = <&csi41vin7>;
};
};
@ -1266,7 +1262,7 @@
status = "disabled";
};
ipmmu_ds1: mmu@e7740000 {
ipmmu_ds1: iommu@e7740000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
@ -1274,7 +1270,7 @@
#iommu-cells = <1>;
};
ipmmu_ir: mmu@ff8b0000 {
ipmmu_ir: iommu@ff8b0000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xff8b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 3>;
@ -1282,7 +1278,7 @@
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 {
ipmmu_mm: iommu@e67b0000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
@ -1291,7 +1287,7 @@
#iommu-cells = <1>;
};
ipmmu_rt: mmu@ffc80000 {
ipmmu_rt: iommu@ffc80000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 10>;
@ -1299,7 +1295,7 @@
#iommu-cells = <1>;
};
ipmmu_vc0: mmu@fe990000 {
ipmmu_vc0: iommu@fe990000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xfe990000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
@ -1307,7 +1303,7 @@
#iommu-cells = <1>;
};
ipmmu_vi0: mmu@febd0000 {
ipmmu_vi0: iommu@febd0000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 14>;
@ -1315,16 +1311,18 @@
#iommu-cells = <1>;
};
ipmmu_vip0: mmu@e7b00000 {
ipmmu_vip0: iommu@e7b00000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xe7b00000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vip1: mmu@e7960000 {
ipmmu_vip1: iommu@e7960000 {
compatible = "renesas,ipmmu-r8a77980";
reg = <0 0xe7960000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 11>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@ -1334,7 +1332,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77980_CLK_SD0H>;
clock-names = "core", "clkh";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 314>;
max-frequency = <200000000>;
@ -1342,6 +1341,22 @@
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a77980-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x4000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@ -1418,6 +1433,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -1457,6 +1476,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -1484,15 +1507,16 @@
};
du: display@feb00000 {
compatible = "renesas,du-r8a77980",
"renesas,du-r8a77970";
compatible = "renesas,du-r8a77980";
reg = <0 0xfeb00000 0 0x80000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>;
clock-names = "du.0";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 724>;
vsps = <&vspd0 0>;
reset-names = "du.0";
renesas,vsps = <&vspd0 0>;
status = "disabled";
ports {
@ -1501,8 +1525,6 @@
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
@ -1536,8 +1558,6 @@
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
@ -1549,7 +1569,7 @@
};
thermal-zones {
thermal-sensor-1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -1568,7 +1588,7 @@
};
};
thermal-sensor-2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;

743
arch/arm/dts/r8a77990-ebisu.dts
View file

@ -1,754 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the ebisu board
* Device Tree Source for the Ebisu board with R-Car E3
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77990.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include "ebisu.dtsi"
/ {
model = "Renesas Ebisu board based on r8a77990";
compatible = "renesas,ebisu", "renesas,r8a77990";
aliases {
serial0 = &scif2;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 50000>;
brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
default-brightness-level = <10>;
power-supply = <&reg_12p0v>;
};
cvbs-in {
compatible = "composite-video-connector";
label = "CVBS IN";
port {
cvbs_con: endpoint {
remote-endpoint = <&adv7482_ain7>;
};
};
};
hdmi-in {
compatible = "hdmi-connector";
label = "HDMI IN";
type = "a";
port {
hdmi_in_con: endpoint {
remote-endpoint = <&adv7482_hdmi>;
};
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&reg_3p3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_12p0v: regulator2 {
compatible = "regulator-fixed";
regulator-name = "D12.0V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
rsnd_ak4613: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "rsnd-ak4613";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4613>;
};
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
};
vbus0_usb2: regulator-vbus0-usb2 {
compatible = "regulator-fixed";
regulator-name = "USB20_VBUS_CN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";
regulator-name = "SDHI1 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi1: regulator-vccq-sdhi1 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
vga {
compatible = "vga-connector";
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
};
};
};
vga-encoder {
compatible = "adi,adv7123";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7123_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7123_out: endpoint {
remote-endpoint = <&vga_in>;
};
};
};
};
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
x13_clk: x13 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <74250000>;
};
};
&audio_clk_a {
clock-frequency = <22579200>;
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
/*
* TX clock internal delay mode is required for reliable
* 1Gbps communication using the KSZ9031RNX phy present on
* the Ebisu board, however, TX clock internal delay mode
* isn't supported on r8a77990. Thus, limit speed to
* 100Mbps for reliable communication.
*/
max-speed = <100>;
};
};
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
};
&csi40 {
status = "okay";
ports {
port@0 {
reg = <0>;
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&adv7482_txa>;
};
};
};
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&x13_clk>;
clock-names = "du.0", "du.1", "dclkin.0";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};
&ehci0 {
dr_mode = "otg";
status = "okay";
};
&extal_clk {
clock-frequency = <48000000>;
};
&hsusb {
dr_mode = "otg";
status = "okay";
};
&i2c0 {
status = "okay";
io_expander: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio2>;
interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
};
hdmi-encoder@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
video-receiver@70 {
compatible = "adi,adv7482";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&gpio0>;
interrupt-names = "intrq1", "intrq2";
interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
<17 IRQ_TYPE_LEVEL_LOW>;
port@7 {
reg = <7>;
adv7482_ain7: endpoint {
remote-endpoint = <&cvbs_con>;
};
};
port@8 {
reg = <8>;
adv7482_hdmi: endpoint {
remote-endpoint = <&hdmi_in_con>;
};
};
port@a {
reg = <10>;
adv7482_txa: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&csi40_in>;
};
};
};
};
&i2c3 {
status = "okay";
ak4613: codec@10 {
compatible = "asahi-kasei,ak4613";
#sound-dai-cells = <0>;
reg = <0x10>;
clocks = <&rcar_sound 3>;
asahi-kasei,in1-single-end;
asahi-kasei,in2-single-end;
asahi-kasei,out1-single-end;
asahi-kasei,out2-single-end;
asahi-kasei,out3-single-end;
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
};
cs2000: clk-multiplier@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x12_clk>;
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
};
&i2c_dvfs {
status = "okay";
clock-frequency = <400000>;
pmic: pmic@30 {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "rohm,bd9571mwv";
reg = <0x30>;
interrupt-parent = <&intc_ex>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
rohm,ddr-backup-power = <0x1>;
rohm,rstbmode-level;
};
};
&lvds0 {
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x13_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&lvds1 {
/*
* Even though the LVDS1 output is not connected, the encoder must be
* enabled to supply a pixel clock to the DU for the DPAD output when
* LVDS0 is in use.
*/
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x13_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
};
&ohci0 {
dr_mode = "otg";
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pciec0 {
status = "okay";
};
&pfc {
avb_pins: avb {
mux {
groups = "avb_link", "avb_mii";
function = "avb";
};
};
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
irq0_pins: irq0 {
groups = "intc_ex_irq0";
function = "intc_ex";
};
pwm3_pins: pwm3 {
groups = "pwm3_b";
function = "pwm3";
};
pwm5_pins: pwm5 {
groups = "pwm5_a";
function = "pwm5";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <3300>;
};
sdhi1_pins_uhs: sd1_uhs {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
function = "sdhi3";
power-source = <1800>;
};
sound_clk_pins: sound_clk {
groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
"audio_clkout_a", "audio_clkout1_a";
function = "audio_clk";
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
};
usb0_pins: usb {
groups = "usb0_b", "usb0_id";
function = "usb0";
};
usb30_pins: usb30 {
groups = "usb30";
function = "usb30";
};
};
&pwm3 {
pinctrl-0 = <&pwm3_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm5 {
pinctrl-0 = <&pwm5_pins>;
pinctrl-names = "default";
status = "okay";
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
status = "okay";
/* update <audio_clk_b> to <cs2000> */
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
<&cpg CPG_CORE R8A77990_CLK_ZA2>;
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src0 &dvc0>;
capture = <&ssi1 &src1 &dvc1>;
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi3 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi3_pins>;
pinctrl-1 = <&sdhi3_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
non-removable;
status = "okay";
};
&ssi1 {
shared-pin;
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
vbus-supply = <&vbus0_usb2>;
status = "okay";
};
&usb3_peri0 {
companion = <&xhci0>;
status = "okay";
};
&vin4 {
status = "okay";
};
&vin5 {
status = "okay";
};
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
status = "okay";
};

335
arch/arm/dts/r8a77990.dtsi
View file

@ -14,17 +14,6 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
};
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
@ -55,7 +44,7 @@
clock-frequency = <0>;
};
cluster1_opp: opp_table10 {
cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
opp-800000000 {
@ -88,6 +77,7 @@
power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
dynamic-power-coefficient = <277>;
clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
@ -100,6 +90,7 @@
power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
@ -110,6 +101,19 @@
cache-unified;
cache-level = <2>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <700>;
exit-latency-us = <700>;
min-residency-us = <5000>;
};
};
};
extal_clk: extal {
@ -156,6 +160,7 @@
compatible = "renesas,r8a77990-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -267,7 +272,7 @@
resets = <&cpg 906>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a77990";
reg = <0 0xe6060000 0 0x508>;
};
@ -275,8 +280,10 @@
i2c_dvfs: i2c@e60b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a77990";
reg = <0 0xe60b0000 0 0x15>;
compatible = "renesas,iic-r8a77990",
"renesas,rcar-gen3-iic",
"renesas,rmobile-iic";
reg = <0 0xe60b0000 0 0x425>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 926>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
@ -405,6 +412,71 @@
resets = <&cpg 407>;
};
tmu0: timer@e61e0000 {
compatible = "renesas,tmu-r8a77990", "renesas,tmu";
reg = <0 0xe61e0000 0 0x30>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 125>;
status = "disabled";
};
tmu1: timer@e6fc0000 {
compatible = "renesas,tmu-r8a77990", "renesas,tmu";
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 124>;
status = "disabled";
};
tmu2: timer@e6fd0000 {
compatible = "renesas,tmu-r8a77990", "renesas,tmu";
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 123>;
status = "disabled";
};
tmu3: timer@e6fe0000 {
compatible = "renesas,tmu-r8a77990", "renesas,tmu";
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 122>;
status = "disabled";
};
tmu4: timer@ffc00000 {
compatible = "renesas,tmu-r8a77990", "renesas,tmu";
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 121>;
status = "disabled";
};
i2c0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
@ -667,6 +739,15 @@
dma-channels = <2>;
};
arm_cc630p: crypto@e6601000 {
compatible = "arm,cryptocell-630p-ree";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xe6601000 0 0x1000>;
clocks = <&cpg CPG_MOD 229>;
resets = <&cpg 229>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a77990",
"renesas,rcar-dmac";
@ -793,7 +874,7 @@
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
};
ipmmu_ds0: mmu@e6740000 {
ipmmu_ds0: iommu@e6740000 {
compatible = "renesas,ipmmu-r8a77990";
reg = <0 0xe6740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
@ -801,7 +882,7 @@
#iommu-cells = <1>;
};
ipmmu_ds1: mmu@e7740000 {
ipmmu_ds1: iommu@e7740000 {
compatible = "renesas,ipmmu-r8a77990";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
@ -809,7 +890,7 @@
#iommu-cells = <1>;
};
ipmmu_hc: mmu@e6570000 {
ipmmu_hc: iommu@e6570000 {
compatible = "renesas,ipmmu-r8a77990";
reg = <0 0xe6570000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 2>;
@ -817,7 +898,7 @@
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 {
ipmmu_mm: iommu@e67b0000 {
compatible = "renesas,ipmmu-r8a77990";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
@ -826,7 +907,7 @@
#iommu-cells = <1>;
};
ipmmu_mp: mmu@ec670000 {
ipmmu_mp: iommu@ec670000 {
compatible = "renesas,ipmmu-r8a77990";
reg = <0 0xec670000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
@ -834,7 +915,7 @@
#iommu-cells = <1>;
};
ipmmu_pv0: mmu@fd800000 {
ipmmu_pv0: iommu@fd800000 {
compatible = "renesas,ipmmu-r8a77990";
reg = <0 0xfd800000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 6>;
@ -842,7 +923,7 @@
#iommu-cells = <1>;
};
ipmmu_rt: mmu@ffc80000 {
ipmmu_rt: iommu@ffc80000 {
compatible = "renesas,ipmmu-r8a77990";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 10>;
@ -850,7 +931,7 @@
#iommu-cells = <1>;
};
ipmmu_vc0: mmu@fe6b0000 {
ipmmu_vc0: iommu@fe6b0000 {
compatible = "renesas,ipmmu-r8a77990";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
@ -858,7 +939,7 @@
#iommu-cells = <1>;
};
ipmmu_vi0: mmu@febd0000 {
ipmmu_vi0: iommu@febd0000 {
compatible = "renesas,ipmmu-r8a77990";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 14>;
@ -866,7 +947,7 @@
#iommu-cells = <1>;
};
ipmmu_vp0: mmu@fe990000 {
ipmmu_vp0: iommu@fe990000 {
compatible = "renesas,ipmmu-r8a77990";
reg = <0 0xfe990000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 16>;
@ -911,9 +992,11 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
@ -958,6 +1041,7 @@
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77990_CLK_CANFD>,
<&can_clk>;
@ -1168,9 +1252,8 @@
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 210>;
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx", "tx", "rx";
dmas = <&dmac0 0x43>, <&dmac0 0x42>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 210>;
#address-cells = <1>;
@ -1230,7 +1313,7 @@
vin4csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin4>;
remote-endpoint = <&csi40vin4>;
};
};
};
@ -1258,12 +1341,132 @@
vin5csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin5>;
remote-endpoint = <&csi40vin5>;
};
};
};
};
drif00: rif@e6f40000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f40000 0 0x84>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 515>;
clock-names = "fck";
dmas = <&dmac1 0x20>, <&dmac2 0x20>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 515>;
renesas,bonding = <&drif01>;
status = "disabled";
};
drif01: rif@e6f50000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f50000 0 0x84>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>;
clock-names = "fck";
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 514>;
renesas,bonding = <&drif00>;
status = "disabled";
};
drif10: rif@e6f60000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f60000 0 0x84>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 513>;
clock-names = "fck";
dmas = <&dmac1 0x24>, <&dmac2 0x24>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 513>;
renesas,bonding = <&drif11>;
status = "disabled";
};
drif11: rif@e6f70000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f70000 0 0x84>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 512>;
clock-names = "fck";
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 512>;
renesas,bonding = <&drif10>;
status = "disabled";
};
drif20: rif@e6f80000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f80000 0 0x84>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 511>;
clock-names = "fck";
dmas = <&dmac0 0x28>;
dma-names = "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 511>;
renesas,bonding = <&drif21>;
status = "disabled";
};
drif21: rif@e6f90000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f90000 0 0x84>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 510>;
clock-names = "fck";
dmas = <&dmac0 0x2a>;
dma-names = "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 510>;
renesas,bonding = <&drif20>;
status = "disabled";
};
drif30: rif@e6fa0000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6fa0000 0 0x84>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 509>;
clock-names = "fck";
dmas = <&dmac0 0x2c>;
dma-names = "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 509>;
renesas,bonding = <&drif31>;
status = "disabled";
};
drif31: rif@e6fb0000 {
compatible = "renesas,r8a77990-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6fb0000 0 0x84>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 508>;
clock-names = "fck";
dmas = <&dmac0 0x2e>;
dma-names = "rx";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 508>;
renesas,bonding = <&drif30>;
status = "disabled";
};
rcar_sound: sound@ec500000 {
/*
* #sound-dai-cells is required
@ -1277,12 +1480,12 @@
* clkout : #clock-cells = <0>; <&rcar_sound>;
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
*/
compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
@ -1470,6 +1673,18 @@
};
};
mlp: mlp@ec520000 {
compatible = "renesas,r8a77990-mlp",
"renesas,rcar-gen3-mlp";
reg = <0 0xec520000 0 0x800>;
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 802>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 802>;
status = "disabled";
};
audma0: dma-controller@ec700000 {
compatible = "renesas,dmac-r8a77990",
"renesas,rcar-dmac";
@ -1571,12 +1786,13 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a77990",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77990_CLK_SD0H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 314>;
@ -1584,12 +1800,13 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a77990",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77990_CLK_SD1H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 313>;
@ -1597,12 +1814,13 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a77990",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77990_CLK_SD3H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 311>;
@ -1610,6 +1828,22 @@
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a77990-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x04000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@ -1761,6 +1995,10 @@
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
@ -1784,14 +2022,13 @@
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
resets = <&cpg 724>;
reset-names = "du.0";
renesas,cmms = <&cmm0>, <&cmm1>;
vsps = <&vspd0 0>, <&vspd1 0>;
renesas,vsps = <&vspd0 0>, <&vspd1 0>;
status = "disabled";
@ -1801,8 +2038,6 @@
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
@ -1844,8 +2079,6 @@
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
@ -1871,8 +2104,6 @@
port@1 {
reg = <1>;
lvds1_out: endpoint {
};
};
};
};
@ -1887,7 +2118,7 @@
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&thermal 0>;
thermal-sensors = <&thermal>;
sustainable-power = <717>;
cooling-maps {

516
arch/arm/dts/r8a77995-draak.dts
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Draak board
* Device Tree Source for the Draak board with R-Car D3
*
* Copyright (C) 2016-2018 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba
@ -8,521 +8,9 @@
/dts-v1/;
#include "r8a77995.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include "draak.dtsi"
/ {
model = "Renesas Draak board based on r8a77995";
compatible = "renesas,draak", "renesas,r8a77995";
aliases {
serial0 = &scif2;
ethernet0 = &avb;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 50000>;
brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
default-brightness-level = <10>;
power-supply = <&reg_12p0v>;
enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
composite-in {
compatible = "composite-video-connector";
port {
composite_con_in: endpoint {
remote-endpoint = <&adv7180_in>;
};
};
};
hdmi-in {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&adv7612_in>;
};
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&reg_3p3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x18000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_12p0v: regulator-12p0v {
compatible = "regulator-fixed";
regulator-name = "D12.0V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
vga {
compatible = "vga-connector";
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
};
};
};
vga-encoder {
compatible = "adi,adv7123";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7123_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7123_out: endpoint {
remote-endpoint = <&vga_in>;
};
};
};
};
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <74250000>;
};
};
&avb {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio5>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
/*
* TX clock internal delay mode is required for reliable
* 1Gbps communication using the KSZ9031RNX phy present on
* the Draak board, however, TX clock internal delay mode
* isn't supported on r8a77995. Thus, limit speed to
* 100Mbps for reliable communication.
*/
max-speed = <100>;
};
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
status = "okay";
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&x12_clk>;
clock-names = "du.0", "du.1", "dclkin.0";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};
&ehci0 {
dr_mode = "host";
status = "okay";
};
&extal_clk {
clock-frequency = <48000000>;
};
&hsusb {
dr_mode = "host";
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
composite-in@20 {
compatible = "adi,adv7180cp";
reg = <0x20>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7180_in: endpoint {
remote-endpoint = <&composite_con_in>;
};
};
port@3 {
reg = <3>;
/*
* The VIN4 video input path is shared between
* CVBS and HDMI inputs through SW[49-53]
* switches.
*
* CVBS is the default selection, link it to
* VIN4 here.
*/
adv7180_out: endpoint {
remote-endpoint = <&vin4_in>;
};
};
};
};
hdmi-encoder@39 {
compatible = "adi,adv7511w";
reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
reg-names = "main", "edid", "packet", "cec";
interrupt-parent = <&gpio1>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
/* Depends on LVDS */
max-clock = <135000000>;
min-vrefresh = <50>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
hdmi-decoder@4c {
compatible = "adi,adv7612";
reg = <0x4c>;
default-input = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7612_in: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
port@2 {
reg = <2>;
/*
* The VIN4 video input path is shared between
* CVBS and HDMI inputs through SW[49-53]
* switches.
*
* CVBS is the default selection, leave HDMI
* not connected here.
*/
adv7612_out: endpoint {
pclk-sample = <0>;
hsync-active = <0>;
vsync-active = <0>;
};
};
};
};
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
&lvds0 {
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x12_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&lvds1 {
/*
* Even though the LVDS1 output is not connected, the encoder must be
* enabled to supply a pixel clock to the DU for the DPAD output when
* LVDS0 is in use.
*/
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x12_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
};
&ohci0 {
dr_mode = "host";
status = "okay";
};
&pfc {
avb0_pins: avb {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_mii";
function = "avb0";
};
};
can0_pins: can0 {
groups = "can0_data_a";
function = "can0";
};
can1_pins: can1 {
groups = "can1_data_a";
function = "can1";
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
pwm0_pins: pwm0 {
groups = "pwm0_c";
function = "pwm0";
};
pwm1_pins: pwm1 {
groups = "pwm1_c";
function = "pwm1";
};
scif2_pins: scif2 {
groups = "scif2_data";
function = "scif2";
};
sdhi2_pins: sd2 {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
vin4_pins_cvbs: vin4 {
groups = "vin4_data8", "vin4_sync", "vin4_clk";
function = "vin4";
};
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm1 {
pinctrl-0 = <&pwm1_pins>;
pinctrl-names = "default";
status = "okay";
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi2 {
/* used for on-board eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
status = "okay";
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
renesas,no-otg-pins;
status = "okay";
};
&vin4 {
pinctrl-0 = <&vin4_pins_cvbs>;
pinctrl-names = "default";
status = "okay";
ports {
port {
vin4_in: endpoint {
remote-endpoint = <&adv7180_out>;
};
};
};
};

372
arch/arm/dts/r8a77995.dtsi
View file

@ -15,6 +15,23 @@
#address-cells = <2>;
#size-cells = <2>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
* Boards that provide audio clocks should override them.
*/
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
@ -77,6 +94,7 @@
compatible = "renesas,r8a77995-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@ -188,11 +206,81 @@
resets = <&cpg 906>;
};
pfc: pin-controller@e6060000 {
pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a77995";
reg = <0 0xe6060000 0 0x508>;
};
cmt0: timer@e60f0000 {
compatible = "renesas,r8a77995-cmt0",
"renesas,rcar-gen3-cmt0";
reg = <0 0xe60f0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 303>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 303>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,r8a77995-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 302>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 302>;
status = "disabled";
};
cmt2: timer@e6140000 {
compatible = "renesas,r8a77995-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6140000 0 0x1004>;
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 301>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 301>;
status = "disabled";
};
cmt3: timer@e6148000 {
compatible = "renesas,r8a77995-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6148000 0 0x1004>;
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 300>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 300>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77995-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@ -242,6 +330,71 @@
resets = <&cpg 407>;
};
tmu0: timer@e61e0000 {
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
reg = <0 0xe61e0000 0 0x30>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 125>;
status = "disabled";
};
tmu1: timer@e6fc0000 {
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 124>;
status = "disabled";
};
tmu2: timer@e6fd0000 {
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 123>;
status = "disabled";
};
tmu3: timer@e6fe0000 {
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 122>;
status = "disabled";
};
tmu4: timer@ffc00000 {
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 121>;
status = "disabled";
};
i2c0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
@ -389,12 +542,22 @@
dma-channels = <2>;
};
arm_cc630p: crypto@e6601000 {
compatible = "arm,cryptocell-630p-ree";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xe6601000 0 0x1000>;
clocks = <&cpg CPG_MOD 229>;
resets = <&cpg 229>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
};
canfd: can@e66c0000 {
compatible = "renesas,r8a77995-canfd",
"renesas,rcar-gen3-canfd";
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
<&can_clk>;
@ -498,7 +661,7 @@
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
};
ipmmu_ds0: mmu@e6740000 {
ipmmu_ds0: iommu@e6740000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xe6740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
@ -506,7 +669,7 @@
#iommu-cells = <1>;
};
ipmmu_ds1: mmu@e7740000 {
ipmmu_ds1: iommu@e7740000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
@ -514,7 +677,7 @@
#iommu-cells = <1>;
};
ipmmu_hc: mmu@e6570000 {
ipmmu_hc: iommu@e6570000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xe6570000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 2>;
@ -522,7 +685,7 @@
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 {
ipmmu_mm: iommu@e67b0000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
@ -531,7 +694,7 @@
#iommu-cells = <1>;
};
ipmmu_mp: mmu@ec670000 {
ipmmu_mp: iommu@ec670000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xec670000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
@ -539,7 +702,7 @@
#iommu-cells = <1>;
};
ipmmu_pv0: mmu@fd800000 {
ipmmu_pv0: iommu@fd800000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xfd800000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 6>;
@ -547,7 +710,7 @@
#iommu-cells = <1>;
};
ipmmu_rt: mmu@ffc80000 {
ipmmu_rt: iommu@ffc80000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 10>;
@ -555,7 +718,7 @@
#iommu-cells = <1>;
};
ipmmu_vc0: mmu@fe6b0000 {
ipmmu_vc0: iommu@fe6b0000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
@ -563,7 +726,7 @@
#iommu-cells = <1>;
};
ipmmu_vi0: mmu@febd0000 {
ipmmu_vi0: iommu@febd0000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 14>;
@ -571,7 +734,7 @@
#iommu-cells = <1>;
};
ipmmu_vp0: mmu@fe990000 {
ipmmu_vp0: iommu@fe990000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xfe990000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 16>;
@ -616,9 +779,11 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
rx-internal-delay-ps = <1800>;
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
@ -870,6 +1035,159 @@
status = "disabled";
};
rcar_sound: sound@ec500000 {
/*
* #sound-dai-cells is required
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
*/
/*
* #clock-cells is required for audio_clkout0/1/2/3
*
* clkout : #clock-cells = <0>; <&rcar_sound>;
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
*/
compatible = "renesas,rcar_sound-r8a77995", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
<&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&cpg CPG_CORE R8A77995_CLK_ZA2>;
clock-names = "ssi-all",
"ssi.4", "ssi.3",
"src.6", "src.5",
"mix.1", "mix.0",
"ctu.1", "ctu.0",
"dvc.0", "dvc.1",
"clk_a", "clk_b", "clk_i";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 1005>,
<&cpg 1011>, <&cpg 1012>;
reset-names = "ssi-all",
"ssi.4", "ssi.3";
status = "disabled";
rcar_sound,ctu {
ctu00: ctu-0 { };
ctu01: ctu-1 { };
ctu02: ctu-2 { };
ctu03: ctu-3 { };
ctu10: ctu-4 { };
ctu11: ctu-5 { };
ctu12: ctu-6 { };
ctu13: ctu-7 { };
};
rcar_sound,dvc {
dvc0: dvc-0 {
dmas = <&audma0 0xbc>;
dma-names = "tx";
};
dvc1: dvc-1 {
dmas = <&audma0 0xbe>;
dma-names = "tx";
};
};
rcar_sound,mix {
mix0: mix-0 { };
mix1: mix-1 { };
};
rcar_sound,src {
src5: src-5 {
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8f>, <&audma0 0xb2>;
dma-names = "rx", "tx";
};
src6: src-6 {
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x91>, <&audma0 0xb4>;
dma-names = "rx", "tx";
};
};
rcar_sound,ssi {
ssi3: ssi-3 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x07>, <&audma0 0x08>,
<&audma0 0x6f>, <&audma0 0x70>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi4: ssi-4 {
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x09>, <&audma0 0x0a>,
<&audma0 0x71>, <&audma0 0x72>;
dma-names = "rx", "tx", "rxu", "txu";
};
};
};
mlp: mlp@ec520000 {
compatible = "renesas,r8a77995-mlp",
"renesas,rcar-gen3-mlp";
reg = <0 0xec520000 0 0x800>;
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 802>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 802>;
status = "disabled";
};
audma0: dma-controller@ec700000 {
compatible = "renesas,dmac-r8a77995",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 502>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 502>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
<&ipmmu_mp 2>, <&ipmmu_mp 3>,
<&ipmmu_mp 4>, <&ipmmu_mp 5>,
<&ipmmu_mp 6>, <&ipmmu_mp 7>,
<&ipmmu_mp 8>, <&ipmmu_mp 9>,
<&ipmmu_mp 10>, <&ipmmu_mp 11>,
<&ipmmu_mp 12>, <&ipmmu_mp 13>,
<&ipmmu_mp 14>, <&ipmmu_mp 15>;
};
ohci0: usb@ee080000 {
compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>;
@ -907,12 +1225,13 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a77995",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77995_CLK_SD0H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 312>;
@ -920,6 +1239,22 @@
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a77995-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x04000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@ -1017,14 +1352,13 @@
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
resets = <&cpg 724>;
reset-names = "du.0";
renesas,cmms = <&cmm0>, <&cmm1>;
vsps = <&vspd0 0>, <&vspd1 0>;
renesas,vsps = <&vspd0 0>, <&vspd1 0>;
status = "disabled";
@ -1034,8 +1368,6 @@
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
@ -1077,8 +1409,6 @@
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
@ -1104,8 +1434,6 @@
port@1 {
reg = <1>;
lvds1_out: endpoint {
};
};
};
};

233
arch/arm/dts/r8a779a0-falcon-cpu.dtsi
View file

@ -6,12 +6,84 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "r8a779a0.dtsi"
/ {
model = "Renesas Falcon CPU board";
compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
serial0 = &scif0;
};
chosen {
stdout-path = "serial0:115200n8";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&keys_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio6 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "SW47";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio6 19 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "SW48";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio6 20 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW49";
wakeup-source;
debounce-interval = <20>;
};
};
leds {
compatible = "gpio-leds";
led-1 {
gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
};
led-2 {
gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
};
led-3 {
gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <3>;
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
@ -33,6 +105,27 @@
reg = <0x7 0x00000000 0x0 0x80000000>;
};
mini-dp-con {
compatible = "dp-connector";
label = "CN5";
type = "mini";
port {
mini_dp_con_in: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
reg_1p2v: regulator-1p2v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
@ -50,24 +143,31 @@
regulator-boot-on;
regulator-always-on;
};
sn65dsi86_refclk: clk-x6 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
};
};
&avb0 {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
tx-internal-delay-ps = <2000>;
&dsi0 {
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
ports {
port@1 {
dsi0_out: endpoint {
remote-endpoint = <&sn65dsi86_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
&du {
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
@ -82,6 +182,13 @@
status = "okay";
clock-frequency = <400000>;
eeprom@50 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "cpu-board";
reg = <0x50>;
pagesize = <8>;
};
};
&i2c1 {
@ -90,6 +197,44 @@
status = "okay";
clock-frequency = <400000>;
bridge@2c {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "ti,sn65dsi86";
reg = <0x2c>;
clocks = <&sn65dsi86_refclk>;
clock-names = "refclk";
interrupt-parent = <&intc_ex>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
vccio-supply = <&reg_1p8v>;
vpll-supply = <&reg_1p8v>;
vcca-supply = <&reg_1p2v>;
vcc-supply = <&reg_1p2v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sn65dsi86_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
sn65dsi86_out: endpoint {
remote-endpoint = <&mini_dp_con_in>;
};
};
};
};
};
&i2c6 {
@ -121,24 +266,6 @@
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb0_pins: avb0 {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
function = "avb0";
};
pins_mdio {
groups = "avb0_mdio";
drive-strength = <21>;
};
pins_mii {
groups = "avb0_rgmii";
drive-strength = <21>;
};
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
@ -154,12 +281,27 @@
function = "i2c6";
};
irq0_pins: irq0 {
groups = "intc_ex_irq0";
function = "intc_ex";
};
keys_pins: keys {
pins = "GP_6_18", "GP_6_19", "GP_6_20";
bias-pull-up;
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data", "scif0_ctrl";
function = "scif0";
@ -171,6 +313,39 @@
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot@0 {
reg = <0x0 0xcc0000>;
read-only;
};
user@cc0000 {
reg = <0xcc0000 0x3340000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";

265
arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi Normal file
View file

@ -0,0 +1,265 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Falcon CSI/DSI sub-board
*
* Copyright (C) 2021 Glider bv
*/
&csi40 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max96712_out0>;
};
};
};
};
&csi42 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi42_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max96712_out1>;
};
};
};
};
&csi43 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi43_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max96712_out2>;
};
};
};
};
&i2c0 {
pca9654_a: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
pca9654_b: gpio@22 {
compatible = "onnn,pca9654";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
pca9654_c: gpio@23 {
compatible = "onnn,pca9654";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "csi-dsi-sub-board-id";
reg = <0x52>;
pagesize = <8>;
};
};
&i2c1 {
gmsl0: gmsl-deserializer@49 {
compatible = "maxim,max96712";
reg = <0x49>;
enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
max96712_out0: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
};
gmsl1: gmsl-deserializer@4b {
compatible = "maxim,max96712";
reg = <0x4b>;
enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
max96712_out1: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
lane-polarities = <0 0 0 0 1>;
remote-endpoint = <&csi42_in>;
};
};
};
};
gmsl2: gmsl-deserializer@6b {
compatible = "maxim,max96712";
reg = <0x6b>;
enable-gpios = <&pca9654_c 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
max96712_out2: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
lane-polarities = <0 0 0 0 1>;
remote-endpoint = <&csi43_in>;
};
};
};
};
};
&isp0 {
status = "okay";
};
&isp2 {
status = "okay";
};
&isp3 {
status = "okay";
};
&vin00 {
status = "okay";
};
&vin01 {
status = "okay";
};
&vin02 {
status = "okay";
};
&vin03 {
status = "okay";
};
&vin04 {
status = "okay";
};
&vin05 {
status = "okay";
};
&vin06 {
status = "okay";
};
&vin07 {
status = "okay";
};
&vin16 {
status = "okay";
};
&vin17 {
status = "okay";
};
&vin18 {
status = "okay";
};
&vin19 {
status = "okay";
};
&vin20 {
status = "okay";
};
&vin21 {
status = "okay";
};
&vin22 {
status = "okay";
};
&vin23 {
status = "okay";
};
&vin24 {
status = "okay";
};
&vin25 {
status = "okay";
};
&vin26 {
status = "okay";
};
&vin27 {
status = "okay";
};
&vin28 {
status = "okay";
};
&vin29 {
status = "okay";
};
&vin30 {
status = "okay";
};
&vin31 {
status = "okay";
};

15
arch/arm/dts/r8a779a0-falcon-ethernet.dtsi Normal file
View file

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Falcon Ethernet sub-board
*
* Copyright (C) 2021 Glider bv
*/
&i2c0 {
eeprom@53 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "ethernet-sub-board-id";
reg = <0x53>;
pagesize = <8>;
};
};

2
arch/arm/dts/r8a779a0-falcon-u-boot.dts
View file

@ -21,7 +21,7 @@
spi-max-frequency = <50000000>;
status = "okay";
spi-flash@0 {
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;

80
arch/arm/dts/r8a779a0-falcon.dts
View file

@ -1,12 +1,14 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Falcon CPU and BreakOut boards
* Device Tree Source for the Falcon CPU and BreakOut boards with R-Car V3U
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a779a0-falcon-cpu.dtsi"
#include "r8a779a0-falcon-csi-dsi.dtsi"
#include "r8a779a0-falcon-ethernet.dtsi"
/ {
model = "Renesas Falcon CPU and Breakout boards based on r8a779a0";
@ -14,15 +16,77 @@
aliases {
ethernet0 = &avb0;
serial0 = &scif0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&rwdt {
timeout-sec = <60>;
&avb0 {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
};
};
&canfd {
pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
channel1 {
status = "okay";
};
};
&i2c0 {
eeprom@51 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "breakout-board";
reg = <0x51>;
pagesize = <8>;
};
};
&pfc {
avb0_pins: avb0 {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
"avb0_txcrefclk";
function = "avb0";
};
pins_mdio {
groups = "avb0_mdio";
drive-strength = <21>;
};
pins_mii {
groups = "avb0_rgmii";
drive-strength = <21>;
};
};
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";
};
canfd1_pins: canfd1 {
groups = "canfd1_data";
function = "canfd1";
};
};

2001
arch/arm/dts/r8a779a0.dtsi
View file

File diff suppressed because it is too large Load diff

105
arch/arm/dts/ulcb.dtsi
View file

@ -21,8 +21,18 @@
model = "Renesas R-Car Gen3 ULCB board";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
serial0 = &scif2;
ethernet0 = &avb;
mmc0 = &sdhi2;
mmc1 = &sdhi0;
};
chosen {
@ -46,6 +56,7 @@
port {
hdmi0_con: endpoint {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
};
};
@ -73,7 +84,7 @@
};
};
reg_1p8v: regulator0 {
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
@ -82,7 +93,7 @@
regulator-always-on;
};
reg_3p3v: regulator1 {
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
@ -92,11 +103,11 @@
};
sound_card: sound {
compatible = "audio-graph-card";
compatible = "audio-graph-card2";
label = "rcar-sound";
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1 /* HDMI0 */
links = <&rsnd_port0 /* ak4613 */
&rsnd_port1 /* HDMI0 */
>;
};
@ -136,6 +147,10 @@
};
};
&a57_0 {
cpu-supply = <&dvfs>;
};
&audio_clk_a {
clock-frequency = <22579200>;
};
@ -144,10 +159,12 @@
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
@ -191,10 +208,6 @@
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
@ -365,7 +378,7 @@
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
@ -403,30 +416,73 @@
reg = <0>;
rsnd_for_ak4613: endpoint {
remote-endpoint = <&ak4613_endpoint>;
dai-format = "left_j";
bitclock-master = <&rsnd_for_ak4613>;
frame-master = <&rsnd_for_ak4613>;
playback = <&ssi0 &src0 &dvc0>;
capture = <&ssi1 &src1 &dvc1>;
bitclock-master;
frame-master;
playback = <&ssi0>, <&src0>, <&dvc0>;
capture = <&ssi1>, <&src1>, <&dvc1>;
};
};
rsnd_port1: port@1 {
reg = <1>;
rsnd_for_hdmi: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_for_hdmi>;
frame-master = <&rsnd_for_hdmi>;
bitclock-master;
frame-master;
playback = <&ssi2>;
};
};
};
};
&rpc {
/* Left disabled. To be enabled by firmware when unlocked. */
flash@0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
bl2@40000 {
reg = <0x00040000 0x140000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x040000>;
read-only;
};
tee@200000 {
reg = <0x00200000 0x440000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x100000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
@ -468,7 +524,10 @@
bus-width = <8>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
no-sd;
no-sdio;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};

2
configs/r8a77990_ebisu_defconfig
View file

@ -56,7 +56,7 @@ CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-ex
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_SYS_MMC_ENV_DEV=0
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_VERSION_VARIABLE=y
CONFIG_REGMAP=y

2
configs/rcar3_ulcb_defconfig
View file

@ -58,7 +58,7 @@ CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-ex
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SYS_MMC_ENV_DEV=0
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_VERSION_VARIABLE=y
CONFIG_REGMAP=y

2
drivers/clk/clk_versaclock.c
View file

@ -17,7 +17,7 @@
#include <linux/kernel.h>
#include <linux/math64.h>
#include <dt-bindings/clk/versaclock.h>
#include <dt-bindings/clock/versaclock.h>
/* VersaClock5 registers */
#define VC5_OTP_CONTROL 0x00

0
include/dt-bindings/clk/versaclock.h → include/dt-bindings/clock/versaclock.h
View file