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https://github.com/AsahiLinux/u-boot
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clk: renesas: Synchronize R8A779A0 V3U clock tables with Linux 6.1.7
Synchronize R-Car R8A779A0 V3U clock tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Rename CLK_TYPE_R8A779A0_ to CLK_TYPE_GEN4_ to match the new clock tables. Add CLK_TYPE_GEN4_SD, CLK_TYPE_GEN4_RPC and CLK_TYPE_GEN4_RPCD2 macros and handling into Gen3 CPG core. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
4fc053f1e2
commit
733da621d5
3 changed files with 77 additions and 31 deletions
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@ -253,23 +253,23 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
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return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
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CPG_PLL4CR, 0, 0, "PLL4");
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case CLK_TYPE_R8A779A0_MAIN:
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case CLK_TYPE_GEN4_MAIN:
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return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
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0, 1, pll_config->extal_div,
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"V3U_MAIN");
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case CLK_TYPE_R8A779A0_PLL1:
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case CLK_TYPE_GEN4_PLL1:
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return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
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0, pll_config->pll1_mult,
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pll_config->pll1_div,
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"V3U_PLL1");
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case CLK_TYPE_R8A779A0_PLL2X_3X:
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case CLK_TYPE_GEN4_PLL2X_3X:
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return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
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core->offset, 0, 0,
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"V3U_PLL2X_3X");
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case CLK_TYPE_R8A779A0_PLL5:
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case CLK_TYPE_GEN4_PLL5:
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return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
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0, pll_config->pll5_mult,
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pll_config->pll5_div,
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@ -290,11 +290,13 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
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return rate;
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case CLK_TYPE_GEN3_SDH: /* Fixed factor 1:1 */
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fallthrough;
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case CLK_TYPE_GEN4_SDH: /* Fixed factor 1:1 */
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return gen3_clk_get_rate64(&parent);
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case CLK_TYPE_GEN3_SD: /* FIXME */
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fallthrough;
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case CLK_TYPE_R8A779A0_SD:
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case CLK_TYPE_GEN4_SD:
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value = readl(priv->base + core->offset);
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value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
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@ -315,6 +317,8 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
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case CLK_TYPE_GEN3_RPC:
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case CLK_TYPE_GEN3_RPCD2:
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case CLK_TYPE_GEN4_RPC:
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case CLK_TYPE_GEN4_RPCD2:
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rate = gen3_clk_get_rate64(&parent);
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value = readl(priv->base + core->offset);
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@ -53,29 +53,18 @@ enum clk_ids {
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};
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#define DEF_PLL(_name, _id, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
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.offset = _offset)
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#define DEF_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset)
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#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
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DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \
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(_parent0) << 16 | (_parent1), \
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.div = (_div0) << 16 | (_div1), .offset = _md)
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#define DEF_OSC(_name, _id, _parent, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div)
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static const struct cpg_core_clk r8a779a0_core_clks[] = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("extalr", CLK_EXTALR),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
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DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
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DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
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DEF_PLL(".pll20", CLK_PLL20, 0x0834),
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DEF_PLL(".pll21", CLK_PLL21, 0x0838),
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DEF_PLL(".pll30", CLK_PLL30, 0x083c),
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@ -91,9 +80,14 @@ static const struct cpg_core_clk r8a779a0_core_clks[] = {
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DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1),
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DEF_RATE(".oco", CLK_OCO, 32768),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
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/* Core Clock Outputs */
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DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0),
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DEF_GEN4_Z("z1", R8A779A0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL21, 2, 8),
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DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1),
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DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1),
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DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1),
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@ -107,7 +101,6 @@ static const struct cpg_core_clk r8a779a0_core_clks[] = {
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DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1),
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DEF_FIXED("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 1, 1),
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DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1),
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DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1),
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DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1),
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@ -116,15 +109,22 @@ static const struct cpg_core_clk r8a779a0_core_clks[] = {
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DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1),
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DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
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DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1),
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DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1),
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DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870),
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DEF_GEN4_SDH("sd0h", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870),
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DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870),
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DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
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R8A779A0_CLK_RPC),
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DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
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DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
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DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
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DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884),
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DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
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DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
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DEF_GEN4_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
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DEF_GEN4_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
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};
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static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
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@ -134,10 +134,14 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
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DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2),
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DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2),
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DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2),
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DEF_MOD("canfd0", 328, R8A779A0_CLK_CANFD),
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DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
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DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
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DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
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DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0),
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DEF_MOD("du", 411, R8A779A0_CLK_S3D1),
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DEF_MOD("dsi0", 415, R8A779A0_CLK_DSI),
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DEF_MOD("dsi1", 416, R8A779A0_CLK_DSI),
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DEF_MOD("fcpvd0", 508, R8A779A0_CLK_S3D1),
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DEF_MOD("fcpvd1", 509, R8A779A0_CLK_S3D1),
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DEF_MOD("hscif0", 514, R8A779A0_CLK_S1D2),
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@ -151,12 +155,17 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
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DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4),
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DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4),
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DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4),
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DEF_MOD("ispcs0", 612, R8A779A0_CLK_S1D1),
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DEF_MOD("ispcs1", 613, R8A779A0_CLK_S1D1),
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DEF_MOD("ispcs2", 614, R8A779A0_CLK_S1D1),
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DEF_MOD("ispcs3", 615, R8A779A0_CLK_S1D1),
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DEF_MOD("msi0", 618, R8A779A0_CLK_MSO),
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DEF_MOD("msi1", 619, R8A779A0_CLK_MSO),
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DEF_MOD("msi2", 620, R8A779A0_CLK_MSO),
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DEF_MOD("msi3", 621, R8A779A0_CLK_MSO),
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DEF_MOD("msi4", 622, R8A779A0_CLK_MSO),
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DEF_MOD("msi5", 623, R8A779A0_CLK_MSO),
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DEF_MOD("rpc-if", 629, R8A779A0_CLK_RPCD2),
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DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8),
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DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8),
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DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8),
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@ -164,6 +173,12 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
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DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0),
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DEF_MOD("sydm1", 709, R8A779A0_CLK_S1D2),
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DEF_MOD("sydm2", 710, R8A779A0_CLK_S1D2),
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DEF_MOD("tmu0", 713, R8A779A0_CLK_CL16MCK),
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DEF_MOD("tmu1", 714, R8A779A0_CLK_S1D4),
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DEF_MOD("tmu2", 715, R8A779A0_CLK_S1D4),
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DEF_MOD("tmu3", 716, R8A779A0_CLK_S1D4),
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DEF_MOD("tmu4", 717, R8A779A0_CLK_S1D4),
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DEF_MOD("tpu0", 718, R8A779A0_CLK_S1D8),
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DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1),
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DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1),
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DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1),
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@ -199,10 +214,15 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
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DEF_MOD("vspd0", 830, R8A779A0_CLK_S3D1),
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DEF_MOD("vspd1", 831, R8A779A0_CLK_S3D1),
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DEF_MOD("rwdt", 907, R8A779A0_CLK_R),
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DEF_MOD("cmt0", 910, R8A779A0_CLK_R),
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DEF_MOD("cmt1", 911, R8A779A0_CLK_R),
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DEF_MOD("cmt2", 912, R8A779A0_CLK_R),
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DEF_MOD("cmt3", 913, R8A779A0_CLK_R),
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DEF_MOD("pfc0", 915, R8A779A0_CLK_CP),
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DEF_MOD("pfc1", 916, R8A779A0_CLK_CP),
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DEF_MOD("pfc2", 917, R8A779A0_CLK_CP),
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DEF_MOD("pfc3", 918, R8A779A0_CLK_CP),
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DEF_MOD("tsc", 919, R8A779A0_CLK_CL16MCK),
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DEF_MOD("vspx0", 1028, R8A779A0_CLK_S1D1),
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DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1),
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DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1),
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@ -30,13 +30,18 @@ enum rcar_gen3_clk_types {
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CLK_TYPE_GEN3_RPC,
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CLK_TYPE_GEN3_RPCD2,
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CLK_TYPE_R8A779A0_MAIN,
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CLK_TYPE_R8A779A0_PLL1,
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CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */
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CLK_TYPE_R8A779A0_PLL5,
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CLK_TYPE_R8A779A0_SD,
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CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */
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CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */
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CLK_TYPE_GEN4_MAIN,
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CLK_TYPE_GEN4_PLL1,
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CLK_TYPE_GEN4_PLL2X_3X, /* PLL[23][01] */
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CLK_TYPE_GEN4_PLL5,
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CLK_TYPE_GEN4_SDH,
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CLK_TYPE_GEN4_SD,
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CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */
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CLK_TYPE_GEN4_Z,
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CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */
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CLK_TYPE_GEN4_RPCSRC,
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CLK_TYPE_GEN4_RPC,
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CLK_TYPE_GEN4_RPCD2,
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/* SoC specific definitions start here */
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CLK_TYPE_GEN3_SOC_BASE,
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@ -79,6 +84,23 @@ enum rcar_gen3_clk_types {
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
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(_parent0) << 16 | (_parent1), .div = 8)
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#define DEF_GEN4_SDH(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
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#define DEF_GEN4_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
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#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
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(_parent0) << 16 | (_parent1), \
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.div = (_div0) << 16 | (_div1), .offset = _md)
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#define DEF_GEN4_OSC(_name, _id, _parent, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
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#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \
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DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
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struct rcar_gen3_cpg_pll_config {
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u8 extal_div;
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u8 pll1_mult;
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