Now that DM_ETH is enabled by default, there is no point in keeping the
non-DM_ETH code which initialized the ethernet interfaces.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The LX2160ARDB board has support for DM_ETH probed devices, which means
that we do not need to manually create an MDIO controller, register it,
create PHYs on it etc.
In order to cleanup the board file a bit, just remove this code entirely.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The Odroid Go Ultra has 2 chained PMICs RK818 and RK818, and needs
an adjustment on the BUCK and LDO values.
Add the initial regulators values in -u-boot.dtsi & run the initial
regulator setup in a new odroid-go-ultra board.
Proper OTG and BOOST regulators are still missing to have USB-A
host properly working.
Link: https://lore.kernel.org/r/20230210-u-boot-odroid-go-ultra-pmics-setup-v1-1-1f16d62b76af@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
There are missing Kconfig dependencies in the code which is using
firmware interface.
The commit 71efd45a5f ("arm64: zynqmp: Change firmware dependency")
add option to also disable ZYNQMP_FIRMWARE. But not all Kconfig
dependencies were properly described and also sdhci and gem drivers
didn't protect the code properly.
So, add the missing ZYNQMP_FIRMWARE dependencies.
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230201095553.11219-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
The conditions in this code do not align when doing an SPL build with
split config. Use __maybe_unused to avoid needing to be so explicit.
Of course a better solution would be to refactor all of this to avoid
using #ifdef.
Signed-off-by: Simon Glass <sjg@chromium.org>
This causes a build failure on mx6cuboxi with split config, since CMD_SATA
shows up as enabled in SPl (because there is no SPL_CMD_SATA).
The condition is wrong anyway, so change it to use SATA instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_PG_WCOM_UBOOT_UPDATE_SUPPORTED defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
RK3588 has two memory gaps when using 16 GiB DRAM size:
[0x3fc000000 , 0x3fc500000]
and
[0x3fff00000 , 0x3ffffffff]
If the kernel is agnostic to these gaps, accessing the area causes
a SError panic.
Hence, add reserved memory areas in kernel's DTB before booting.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
ROCK 5B is a Rockchip RK3588 based SBC (Single Board Computer) by Radxa.
There are tree variants depending on the DRAM size : 4G, 8G and 16G.
Specification:
Rockchip Rk3588 SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
MIPI CSI 2 multiple lanes connector
eMMC module connector
uSD slot (up to 128GB)
2x USB 2.0, 2x USB 3.0
2x HDMI output, 1x HDMI input
Ethernet port
40-pin IO header including UART, SPI, I2C and 5V DC power in
USB PD over USB Type-C
Size: 85mm x 54mm
Kernel commits:
a1d3281450ab ("arm64: dts: rockchip: Add rock-5b board")
6fb13f888f2a ("arm64: dts: rockchip: Update sdhci alias for rock-5b")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RK3588 from Edgeble AI.
General features:
- Rockchip RK3588
- up to 32GB LPDDR4x
- up to 128GB eMMC
- 2x MIPI CSI2 FPC
On module WiFi6/BT5 is available in the following Neu6 variants.
Neural Compute Module 6(Neu6) IO board is an industrial form factor
ready-to-use IO board from Edgeble AI.
IO board offers plenty of peripherals and connectivity options and
this patch enables basic eMMC and UART which is enough to successfully
boot Linux.
Neu6 needs to mount on top of this IO board in order to create a
complete Edgeble Neural Compute Module 6(Neu6) IO platform.
Boot log for the record,
DDR Version V1.08 20220617
LPDDR4X, 2112MHz
channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
Manufacturer ID:0x6
CH0 RX Vref:31.7%, TX Vref:21.8%,21.8%
CH1 RX Vref:30.7%, TX Vref:22.8%,23.8%
CH2 RX Vref:30.7%, TX Vref:22.8%,22.8%
CH3 RX Vref:30.7%, TX Vref:21.8%,21.8%
change to F1: 528MHz
change to F2: 1068MHz
change to F3: 1560MHz
change to F0: 2112MHz
out
U-Boot SPL 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530)
Trying to boot from MMC1
INFO: Preloader serial: 2
NOTICE: BL31: v2.3():v2.3-391-g856309329:derrick.huang
NOTICE: BL31: Built : 14:15:50, Jul 18 2022
INFO: ext 32k is not valid
INFO: GICv3 without legacy support detected.
INFO: ARM GICv3 driver initialized in EL3
INFO: system boots from cpu-hwid-0
INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
INFO: BL31: Initialising Exception Handling Framework
INFO: BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
ERROR: Error initializing runtime service opteed_fast
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0xa00000
INFO: SPSR = 0x3c9
U-Boot 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530)
Model: Edgeble Neu6A IO Board
DRAM: 7.5 GiB (effective 3.7 GiB)
Core: 71 devices, 15 uclasses, devicetree: separate
MMC: mmc@fe2c0000: 0
Loading Environment from nowhere... OK
In: serial@feb50000
Out: serial@feb50000
Err: serial@feb50000
Model: Edgeble Neu6A IO Board
Net: No ethernet found.
Hit any key to stop autoboot: 0
=>
Add support for Edgeble Neu6 Model A IO Board.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Update the MAINTAINERS file to include the devicetree for the
rk3568-evb1-v10 board.
Also update Rockchip board docs to include information on building
RK3568 based devices.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Radxa Compute Module 3(CM3) IO board an application board from Radxa
and is compatible with Raspberry Pi CM4 IO form factor.
Radxa CM3 needs to mount on top of this IO board in order to create
complete Radxa CM3 IO board platform.
Add support for Radxa CM3 IO Board defconfig and -u-boot.dtsi
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The board should be RV1126-NEU2 instead RV1126-ECM0.
Fix the wrong name.
Fixes: b8f1ca9540 ("board: rockchip: Add Edgeble Neu2 IO Board")
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add Radxa ROCK 3 Model A support. sync rk3308-rock-pi-s.dts from
Linux 6.2.0-rc7.
ROCK Pi S is RK3308 based SBC from radxa.com. ROCK Pi S has a,
- 256MB/512MB DDR3 RAM
- SD, NAND flash (optional on board 1/2/4/8Gb)
- 100MB ethernet, PoE (optional)
- Onboard 802.11 b/g/n wifi + Bluetooth 4.0 Module
- USB2.0 Type-A HOST x1
- USB3.0 Type-C OTG x1
- 26-pin expansion header
- USB Type-C DC 5V Power Supply
Linux commit commit for the same,
<2e04c25b1320> ("arm64: dts: rockchip: add ROCK Pi S DTS support")
Signed-off-by: Akash Gajjar <gajjar04akash@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add Radxa ROCK 3 Model A support. sync rk3568-rock-3a.dts from Linux 6.2.0-rc7
Board Specifications
- Rockchip RK3568
- 2/4/8GB LPDDR4 3200MT/s
- eMMC socket, SD card slot
- GbE LAN
- PCIe 3.0/2.0
- M.2 Connector
- 3.5mm Audio jack with mic
- HDMI 2.0, MIPI DSI/CSI
- USB 3.0 Host/OTG, USB 2.0 Host
- 40-pin GPIO expansion ports
- USB Type C PD 2.0, 9V/2A, 12V/2A, 15V/2A, 20V/2A
Refer Linux commit <22a442e6586c>
("arm64: dts: rockchip: add basic dts for the radxa rock3 model a")
Signed-off-by: Akash Gajjar <gajjar04akash@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Configure PMIC voltages for early stages using updated
early i2c write.
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
Move the environment to an easily editable text file in the boot
partition
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
The L2-cache is not enabled currently, the enbale_caches() will call
the v5l2_enable() callback to enable it in SPL.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Synology DS116 is a NAS based on Marvell Armada 385 SoC.
Board Specification:
- Marvel MV88F6820 Dual Core at 1.8GHz
- 1 GiB DDR3 RAM
- 8MB Macronix mx25l6405d SPI flash
- I2C
- 2x USB 3.0
- 1x GBE LAN port (PHY: Marvell 88E1510)
- 1x SATA (6 Gbps)
- 3x LED
- PIC16F1829 (connected to uart1)
- GPIO fan
- serial console
Note that this patch depends on the add-support for Thecus N2350 patch:
https://patchwork.ozlabs.org/project/uboot/patch/20230201231306.7010-1-mibodhi@gmail.com/
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Currently, only the 1st SATA port is powered up (by GPIO1 12).
Add GPIO1 13 in board initialization to power up the 2nd SATA port.
Note that this patch depends on the initial add-support patch:
https://patchwork.ozlabs.org/project/uboot/patch/20230201231306.7010-1-mibodhi@gmail.com/
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
- A fix for a long standing bug that has been exposed by commit
50128aeb0f ("cyclic: get rid of cyclic_init()") preventing 8xx boards
from booting since u-boot 2023.01
- A GPIO driver for powerpc 8xx chip
- Fixup for powerpc 8xx SPI driver
- A new powerpc 8xx board
- The two devices having that board.
This adds support for the MIAE and VGoIP devices.
Those devices have the same CPU board that the MCR3000_2G board.
The devices are very modular, they are provided with
interchangeable front and back panels.
Linux kernel is shipped with a device tree which contains all
possible setups, and U-boot eliminates unrelated nodes based on
detected hardware.
This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
This adds a new board from CS GROUP. The board is called
MCR3000_2G, and has a CPU board called CMPC885.
That CPU board is shared with another equipment that will
be added in a later patch.
That board stores Ethernet MAC addresses in an EEPROM which
is accessed using SPI bus.
This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
e1-wan device-tree node doesn't exist. Remove related update
to avoid following warning at startup:
Loading Device Tree to 007fa000, end 007ff951 ... OK
Unable to update property /localbus/e1-wan:data-rate, err=FDT_ERR_NOTFOUND
Unable to update property /localbus/e1-wan:channel-phase, err=FDT_ERR_NOTFOUND
Unable to update property /localbus/e1-wan:rising-edge-sync-pulse, err=FDT_ERR_NOTFOUND
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
Both U-boot and Linux kernel have grown over the last releases
and don't fit anymore in the 2M EPROM of the board.
So, rework the setup to allow storing the Linux kernel image
on the UBIFS NAND Flash.
Also add support to FIT images as this is what the Linux kernel
look like nowadays.
Also increase CFG_SYS_BOOTMAPSZ to 32Mbytes and define
CONFIG_SYS_BOOTM_LEN with the same value, otherwise it defaults
to 8M which is not sufficient anymore with nowadays Linux kernels.
And set the netmask to 255.255.255.0 as a class C address is used.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
We can move all of the environment changes to come
from CONFIG_EXTRA_ENV_TEXT.
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
This converts 4 usages of this option to the non-SPL form, since there is
no SPL_FEC_MXC defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_FASTBOOT defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_WATCHDOG_AUTOSTART defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_TEN64_CONTROLLER defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_TARGET_PG_WCOM_SELI8 defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_TARGET_PG_WCOM_EXPU1 defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_TARGET_LX2160ARDB defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_SYS_MEM_RSVD_FOR_MMU defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_SL28_SPL_LOADS_OPTEE_BL32 defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_SL28CPLD defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_SIFIVE_OTP defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_RESV_RAM defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_PG_WCOM_UBOOT_UPDATE defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_PG_WCOM_UBOOT_BOOTPACKAGE defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_MICROBLAZE defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_FSL_MC_ENET defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_FSL_CAAM defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_FDT_SIMPLEFB defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 4 usages of this option to the non-SPL form, since there is
no SPL_ENV_VARS_UBOOT_RUNTIME_CONFIG defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_ENV_IS_IN_UBI defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 13 usages of this option to the non-SPL form, since there is
no SPL_EFI_HAVE_CAPSULE_SUPPORT defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_DWC_ETH_QOS defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_DTB_RESELECT defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_CMD_STM32PROG defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_CMD_STBOARD defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_CMD_FRU defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_BNXT_ETH defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_ARCH_ZYNQ defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
as Tom suggested get rid of CFG_EXTRA_ENV_SETTINGS and
enable CONFIG_ENV_SOURCE_FILE and use text file
board/socrates/socrates.env
which contains the default environment. While at it,
cleanup the default Environment.
Signed-off-by: Heiko Schocher <hs@denx.de>
Suggested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This option as well as CONFIG_TARGET_P1022DS and CONFIG_TARGET_P5020DS
are not defined anywhere. Drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is not used since CONFIG_SYS_FPGA_COMMON is not defined anywhere.
Drop the code and the Makefile rule.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is not used since this commit:
ed7fe2bee1 ppc: Remove xpedite boards
Drop the driver and Kconfig option.
Signed-off-by: Simon Glass <sjg@chromium.org>
convert socrates board to use MPC85XX_HAVE_RESET_VECTOR and
disable CONFIG_OF_BOARD and use common u-boot.dtsi for
creating u-boot-dtb.bin.
Signed-off-by: Heiko Schocher <hs@denx.de>
There are no differences for the different 832x targets we have in
the header defined with SYS_CONFIG_NAME. So we can join the five
headers to a single file.
Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
Next step to get rid of the header files in icnlude/configs. Move
most of the defines to km83xx.c directly. Some remaining defines
which should go to Kconfig are moved to km-mpc83xx.h for now.
Also remove some unused defines and move one define to powerpc.env
as we only need it there.
Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
Set splash screen related env variables. Default splash source is
set to mmc where user is expected to keep bmp in compressed format
with name ti.gz on first partition of mmc.
Splash file will be uncompressed to DDR at address 0x82000000 and
splash position is set to middle of screen.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Use .env file for setting board related environment variables,
in place of am62x_evm.h file. Except for BOOTENV settings, as
config_distro_boot.env file doesn't exist.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Splash screen function needs splash source information
to load image and display it, splash_location provides
the necessary info, Set default_splash_location to MMC
at partition 1:1. Probe DSS for splash screen display.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Convert to DM_SERIAL and drop the iomux board file
level init as it's handled as part of the DM serial
layer instead.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
This moves over the PMIC power init to DM and the associated i2c and
regulator bits.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Add MV88E61XX DSA support:
- update dt to provide internal MDIO bus and port handles.
U-Boot requires a more restrictive subset of the dt bindings
required by Linux for the sake of simplifying code
- update defconfig to remove old driver and enable new one
- replace mv88e61xx_hw_reset weak override with board_phy_config support
for register configuration that is outside the scope of the DSA driver
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Original OpenSBI (without FW_PIC) will relocate itself
from 0x1000000 to 0x0. After OpenSBI added FW_PIC codes,
it will not relocate any more and always run at 0x1000000.
Hence, it may overlap with Kernel memory region. So it is
necessary to change OpenSBI address from 0x1000000 to 0x0.
More details can refer to commit cb052d7712
("riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+")
Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
As explained in the text at the bottom of the page
https://source.codeaurora.org/external/qoriq/qoriq-components/rcw:
"QUIC repositories on this site will not receive any updates after
March 31, 2022, and will be deleted on March 31, 2023."
Point to the NXP RCW github repo instead.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
In some situations the GSC firmware where the EEPROM containing the
model and DRAM configuration may not be ready by the time the SoC
is ready to talk to it over I2C.
Instead of a hard delay, poll the I2C lines to wait until they are
released to avoid the I2C drivers 'Arbitation lost' error message.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
As explained in the text at the bottom of the page
https://source.codeaurora.org/external/imx/imx-atf:
"QUIC repositories on this site will not receive any updates after
March 31, 2022, and will be deleted on March 31, 2023."
Point to the NXP ATF github repo instead.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Oliver Graute <oliver.graute@kococonnector.com>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
All Apalis iMX8 variants have 2nd RGMII on SoC, so add the address
for 2nd ethernet.
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Add the board detection mechanism to be able to support
the 2GB variant.
Based on the code from TechNexion U-Boot downstream tree.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Add the board support for the i.MX8MM Cloos PHG board.
This board uses a imx8mm-tqma8mqml SoM from TQ-Group.
imx8mm-phg.dts and imx8mm-tqma8mqml.dtsi are taken
directly from Linux 6.2-rc3.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Pull common.c into common subdirectory of the board file,
since this code can be reused by other Data Modul SBCs.
Drop the include of lpddr4_timing.h, which is unneeded.
Signed-off-by: Marek Vasut <marex@denx.de>
The icache is enabled in common architecture code since commit:
2fa763baa1 ("ARM: imx: Enable instruction cache early on on i.MX8M")
Drop the board side duplicate code.
Signed-off-by: Marek Vasut <marex@denx.de>
The PCA9450 reset configuration can now be performed by the PCA9450 PMIC
driver itself, remove the hard-coded variant from board code and let the
PMIC driver perform this task using one-liner:
```
$ sed -i '/set WDOG_B_CFG to cold reset/,+2 d' $(git grep -l PCA9450_RESET_CTRL.*0xA1 board/)
```
Venice and i.MX93 EVK required slight manual fix up.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Remove a duplicate of weak board_phy_config() implementation
in drivers/net/phy/phy.c.
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Display build info with information about the version of SCFW, SECO and
TF-A (ATF).
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
U-Boot typically tears down the display controller before handing
control over to Linux. On LCD displays disabling pixel clock leads to a
fading out effect with vertical/horizontal lines. Make sure to disable
back light GPIO Apalis BKL1 before booting Linux.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Implement PCB version and SoC variant handling which automatically loads
the correct device tree for the Linux kernel.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Add the board_init_f API for SPL and run the platform-required SoC
initialization.
Add the functionality for board name-based DTB selection from FIT
within SPL. This will make it easier to utilise one defconfig for
both the EVM and the SK.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Update the board_fit_config_name_match() to choose the right dtb
based on the board name read from EEPROM.
Also restrict multpile EEPROM reads by verifying if EEPROM is already
read
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
J721S2 EVM has EEPROM populated at 0x50. AM68 SK has EEPROM populated at
next address 0x51 in order to be compatible with RPi. So start looking
for TI specific EEPROM at 0x50, if not found look for EEPROM at 0x51.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Update setup_board_eeprom_env() to choose the right board name
for am68-sk.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
makefile:
- Add multi_dtb_fit dependency
clk:
- Handle error cases
microblaze:
- Disable falcon mode and cleanup code around
xilinx:
- Enable regular expression matching in board_fit_config_name_match()
- Fix FRU handling for 0xC1 format
- Fix Xilinx legacy format eeprom parsing
zynqmp:
- Some DT updates/cleanups
- Fix IDcode for xck24
- Remove empty mini config files
- Add support for k24
versal:
- Remove empty mini config files
versal_net:
- Setup timer when runs in EL3
- Build u-boot.elf for mini configurations
zynq-gem:
- Add support for new compatible strings
- Remove support for Avnet Ultrazedev SOM
- Handle SGMII with PCS phy
spi:
- Add support for gigadevice parts
misc:
- Remove CONFIG_TARGET_VENUS ifdef
- Add missing headers to remove sparse warnings
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Merge tag 'xilinx-for-v2023.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx chnages for v2023.04-rc1
makefile:
- Add multi_dtb_fit dependency
clk:
- Handle error cases
microblaze:
- Disable falcon mode and cleanup code around
xilinx:
- Enable regular expression matching in board_fit_config_name_match()
- Fix FRU handling for 0xC1 format
- Fix Xilinx legacy format eeprom parsing
zynqmp:
- Some DT updates/cleanups
- Fix IDcode for xck24
- Remove empty mini config files
- Add support for k24
versal:
- Remove empty mini config files
versal_net:
- Setup timer when runs in EL3
- Build u-boot.elf for mini configurations
zynq-gem:
- Add support for new compatible strings
- Remove support for Avnet Ultrazedev SOM
- Handle SGMII with PCS phy
spi:
- Add support for gigadevice parts
misc:
- Remove CONFIG_TARGET_VENUS ifdef
- Add missing headers to remove sparse warnings
FRU data is not displayed properly in case of 0xc1 fields.
The 0xC1 can be used in two cases.
1. Char record type 8-bit ASCII + Latin 1 with length of 1.
(For example board revision 'A')
2. C1h (type/length byte encoded to indicate no more info fields).
which can follow by 00h to fill all remaining unused space
Hence removed the check end-of-the field c1 to allow c1 fields.
"ASCII+LATIN1" is defined as the printable characters from the
first set of 256 characters of Unicode 6.2 (U+0000h through U+00FFh,
inclusive) expressed as an eight-bit value. (Unicode follows ISO/IEC
8859-1 in the layout of printable characters up to U+00FFh).
So, print only printable chars and limit range from 0x20 ' ' to 0x7e '-'
which will be also indication if 0xc1 behaves as record with one char or
end of record.
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4198d73de600627872c80a5b07e5068502c589d7.1674648379.git.michal.simek@amd.com
When eeprom has random content printing random chars can stuck U-Boot.
That's why update legacy eeprom format decoding algorithm to copy only
maximum amount of chars allocated for fields.
And also print them directly from desc structure.
Previous algorithm was printing strings first directly from eeprom content
and then copy them to desc structure.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/42065fcbb1a10581f9f4f091d64b43c01fe595c6.1674573561.git.michal.simek@amd.com
Prototype is missing for board_get_usable_ram_top, which is pointed by
below sparse warning. Include init.h header file to fix this.
warning: no previous prototype for 'board_get_usable_ram_top'
[-Wmissing-prototypes].
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230120053617.32463-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
SOM itself from PS point of view is using the same configuration as K26
that's why reuse that files and only change compatible strings.
The reason for creating own set of files is just in case when versions
start to diverge because of HW change, supply chain issue, etc.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/61f877ec0b480c5bd368a1211fc73ff7465016bd.1674043915.git.michal.simek@amd.com
At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks. Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Remove some CONFIG symbols and related comments, etc, that are unused
within the code itself at this point.
Signed-off-by: Tom Rini <trini@konsulko.com>
The event framework is just that, a framework. Enabling it by itself
does nothing, so we shouldn't ask the user about it. Reword (and correct
typos) around this the option and help text. This also applies to
DM_EVENT and EVENT_DYNAMIC. Only EVENT_DEBUG and CMD_EVENT should be
visible to the user to select, when EVENT is selected.
With this, it's time to address the larger problems. When functionality
uses events, typically via EVENT_SPY, the appropriate framework then
must be select'd and NOT imply'd. As the functionality will cease to
work (and so, platforms will fail to boot) this is non-optional and
where select is appropriate. Audit the current users of EVENT_SPY to
have a more fine-grained approach to select'ing the framework where
used. Also ensure the current users of event_register and also select
EVENT_DYNAMIC.
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reported-by: Oliver Graute <Oliver.Graute@kococonnector.com>
Reported-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Fixes: 7fe32b3442 ("event: Convert arch_cpu_init_dm() to use events")
Fixes: 42fdcebf85 ("event: Convert misc_init_f() to use events")
Fixes: c5ef202557 ("dm: fix DM_EVENT dependencies")
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Board name in FIT image can use U-Boot regular expressions SLRE to instruct
U-Boot to handle all revisions for certain board.
For example when name (description property) is saying "zynqmp-zcu104-revA"
only description with this name is selected.
When zynqmp-zcu104.* is described then all board revisions will be handled
by this fragment.
Xilinx normally have some board revisions which are SW compatible to each
other. That's why make sense to define board name with revisions first
follow by generic description with '.*' at the end like this:
config_1 {
description = "zynqmp-zcu104-rev[AB]";
fdt = "zynqmp-zcu104-revA";
};
config_2 {
description = "zynqmp-zcu104.*";
fdt = "zynqmp-zcu104-revC";
};
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d67683a3c5d0435a5070e622f7a9a38e19c64cf5.1672994329.git.michal.simek@amd.com
Add support for starting timer by setting up time stamp generator
registers. This is done only for EL3 i.e. mini U-Boot case.
For other cases, it will be done TF-A.
Add COUNTER_FREQUENCY and IOU_SWITCH_DIVISOR0 to Kconfig so that they
can be tuned as required.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fcd8b0dc4b45a11f5e753afff42f84738ac813da.1673336645.git.michal.simek@amd.com
The Pinephone Pro is another device by PINE64. It's closely related
to the Pinebook Pro of which this initial support is derived from.
Specification:
- A variant of the Rockchip RK3399
- A 6 inch 720*1440 DSI display
- Front and rear cameras
- Type-C interface with alt mode display (DP 1.2) and PD charging
- 4GB LPDDR4 RAM
- 128GB eMMC
- mSD card slot
- An AP6255 module for 802.11ac WiFi and Bluetooth 5
- Quectel EG25-G 4G/LTE modem
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Neural Compute Module 2(Neu2) IO board is an industrial form factor
IO board from Edgeble AI.
General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion
Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
We have common ddr types in rockchip or in general. So use
the common ddr type names instead of per Rockchip SoC to
avoid confusion.
The respective ddr type names will use on the associated
ddr SoC driver as these drivers are built per SoC at a time.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
When OP-TEE is used, the SMC for BSEC management are not available and
the STM32MP BSEC pseudo TA must be used (it is mandatory for STM32MP13
and it is a new feature for STM32MP15x).
The BSEC driver try to open a session to this PTA BSEC at probe
and use it for OTP read or write access to fuse or to shadow.
This patch also adapts the commands stm32key and stboard to handle
the BSEC_LOCK_PERM lock value instead of 1.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Before this was named just evm, which doesn't match the naming
of the other TI board file directory and makes it look like a
common directory for evms. Name this omap3evm.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Derald Woods <woods.technical@gmail.com>
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Merge tag 'u-boot-at91-2023.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2023.04 cycle:
This feature set includes the new DM-based NAND flash driver (old non-DM
driver is still kept for backwards compatibility), and the move to DM
NAND flash driver for sam9x60ek board. Feature set also includes
devicetree alignment for sama7g5 with Linux, devicetree alignment on USB
with Linux for all boards (sama5, sam9x60), chip id for sama7g5, minor
configs and tweaks.
Set blue led on at boot time in order to highlight that u-boot is loaded.
This is done for all sam9x60 based boards which contain an RGB led.
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
EEPROM detection logic in ti_i2c_eeprom_get() involves figuring out
whether addressing is 1-byte or 2-byte. There are currently different
behaviours seen across boards as documented in commit bf6376642f
("board: ti: common: board_detect: Fix EEPROM read quirk"). Adding to
the list, we see that there are 2-byte EEPROMs that read properly
with 1-byte addressing with no offset.
For ti_i2c_eeprom_am6_get where eeprom parse operation is dynamic, the
earlier commit d2ab2a2baf ("board: ti: common: board_detect: Fix
EEPROM read quirk for AM6 style data") tried to resolve this by running
ti_i2c_eeprom_get() twice. However this commit along with its former
commit fails on J7 platforms where EEPROM successfully return back the
header on 1-byte addressing and continues to do so until an offset is
introduced. So the second read incorrectly determines the EEPROM as
1-byte addressing.
A more generic solution is introduced here to solve
this issue: 1-byte read without offset and 1-byte read with offset. If
both passes, it follows 1-byte addressing else we proceed with 2-byte
addressing check.
Tested on J721E, J7200, DRA7xx, AM64x
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Fixes: d2ab2a2baf (board: ti: common: board_detect: Fix EEPROM read quirk for AM6 style data)
Fixes: bf6376642f (board: ti: common: board_detect: Fix EEPROM read quirk)
Tested-By: Matwey V. Kornilov <matwey.kornilov@gmail.com>
At this point in the conversion there should be no need to have logic to
disable some symbol during the SPL build as all symbols should have an
SPL counterpart.
The main real changes done here are that we now must make proper use of
CONFIG_IS_ENABLED(DM_SERIAL) rather than many of the odd tricks we
developed prior to CONFIG_IS_ENABLED() being available.
Signed-off-by: Tom Rini <trini@konsulko.com>
Rename the CONFIG_POWER_BD71837_I2C_* symbols to not have the CONFIG
prefix and be local to the file they are used in.
Signed-off-by: Tom Rini <trini@konsulko.com>
Perform simple renames of:
CONFIG_VSC7385_IMAGE to CFG_VSC7385_IMAGE
CONFIG_VSC7385_IMAGE_SIZE to CFG_VSC7385_IMAGE_SIZE
Signed-off-by: Tom Rini <trini@konsulko.com>
Perform simple renames of:
CONFIG_DFU_ALT to CFG_DFU_ALT
CONFIG_DFU_ALT_BOOT_EMMC to CFG_DFU_ALT_BOOT_EMMC
CONFIG_DFU_ALT_BOOT_SD to CFG_DFU_ALT_BOOT_SD
CONFIG_DFU_ALT_SYSTEM to CFG_DFU_ALT_SYSTEM
CONFIG_DFU_ENV_SETTINGS to CFG_DFU_ENV_SETTINGS
Signed-off-by: Tom Rini <trini@konsulko.com>
The way that the timer support is currently done for exynos/nexell
platforms relies on the legacy PWM infrastructure, and that needs to be
updated. However, we really cannot safely undef CONFIG_DM_PWM to build
the timer.c file without warnings. For now, rename the relevant legacy
functions to be prefixed with s5p_ and add prototypes to the arch pwm.h
files.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Stefan Bosch <stefan_b@posteo.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At this point only the TARGET_T1042D4RDB variant of this is supported in
tree, so remove the remaining parts of the other platforms.
Signed-off-by: Tom Rini <trini@konsulko.com>
This is always defined to 16K, so we move this over to
include/fsl_validate.h to start with. Next, we rename this from CONFIG_
to FSL_. Coalesce the various comments around this definition to be in
fsl_validate.h as well to explain the usage.
Signed-off-by: Tom Rini <trini@konsulko.com>
Enable this in the board Kconfig file, but then check for it via
CONFIG_IS_ENABLED so that it will only be true in the non-SPL case, as
is done today. As part of this we move some defines local to where
they are used as it's board specific.
Cc: Samuel Egli <samuel.egli@siemens.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_MONITOR_IS_IN_RAM
As part of this, reword some of the documentation slightly to reflect
that this is in Kconfig and not a define now.
Signed-off-by: Tom Rini <trini@konsulko.com>
Following how g_dnl_bind_fixup is used on other platforms, rename the
unchanging defines used here to be prefixed with EXYNOS rather than
Samsung, and define them here.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_FLASH_SPANSION_S29WS_N
CONFIG_FLASH_VERIFY
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
CONFIG_FSL_ISBC_KEY_EXT
CONFIG_FSL_TRUST_ARCH_v1
CONFIG_FSL_SDHC_V2_3
CONFIG_MAX_DSP_CPUS
CONFIG_MIU_2BIT_INTERLEAVED
CONFIG_SERIAL_BOOT
CONFIG_SPI_BOOTING
CONFIG_X86EMU_RAW_IO
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_DM9000_BYTE_SWAPPED
CONFIG_DM9000_NO_SROM
CONFIG_DM9000_USE_16BIT
CONFIG_DM9000_DEBUG
CONFIG_MXC_GPT_HCLK
CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
Signed-off-by: Tom Rini <trini@konsulko.com>
Add information that will be needed for enabling the UEFI capsule
update feature on the RockPi4 boards. With the feature enabled, it
would be possible to update the idbloader and u-boot.itb images on the
RockPi4B and RockPi4C variants.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The legacy Allwinner code is cluttered with #ifdef's, some of them even
nested, which makes the code hard to read and error prone.
Eventually we will get rid of most of them, but for now let's at least
annotate the #endif lines with the corresponding symbol the bracket
started with.
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Since all callers of mmc_pinmux_setup() are located after the definition
of that function, there is no need for a forward declaration (anymore?).
Remove the prototype along with its #ifdef guards.
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
There is a CONFIG_MMC_SUNXI_SLOT definition in our sunxi_common.h config
header, which was used to note the first MMC controller to initialise.
The definition in that header was always set to 0, with no easy way of
overriding this, and certainly none of the existing boards made any use
of that (non-)feature.
Remove that definition and replace it with a constant 0 in the only
user, in board.c. It turns out that this is safe, as this is only used
in the SPL, and the BROM also unconditionally initialises MMC0.
This also removes the last legacy config symbol with SUN*I in it from
the whitelist.
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Use like the other boards a text file for the environment.
As this is the last user of keymile-common.h we can now remove this
file completely.
Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
Use already present common.env file and add a powerpc specific env
so that we can move all the environment defines to text files.
Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
The functions board_fit_image_post_process() and board_tee_image_process()
are not actually board specific (despite their names). Any board using the
OMAP2 family can use these functions. Move them to boot-common.c.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Default env variables on Espressobin boards are broken since commit c4df0f6f31
("arm: mvebu: Espressobin: Set default value for $fdtfile env variable") as well
as the 'env default -a' command.
The algorithm to find free space in the default_environment[] array returns
after the first env variable instead of the correct position of the last
variable, where there is allocated free space.
This causes that U-Boot board_late_init() function to overwrite a portion of the
default environment with $ethXaddr and $fdtfile variables immediately after the
first env variable and so it is overwriting other variables.
This patch also adds an additional null byte to terminate the environment array.
But U-Boot board_late_init() function do not fill this nul byte explicitly. And
because of that, U-Boot is later trying to interpret remaining buffer as a
continuation of variable list. Normally buffer should be empty but due to the
above issue, it contains garbage from remaining env variables.
For example 'env default -a' command results in damaging variable names. It was
observed that scritaddr variable name was changed to criptaddr (without leading
's').
This bug was reported and discussed on the Armbian forum:
https://forum.armbian.com/topic/19564-making-espressobin-v7-work-in-2022/?do=findComment&comment=138136
Fix these issues in two steps:
1) Change code which finds free space for dynamic env variables in
default_environment[] array by jumping to the end of the variable list instead
of jumping after the first defined variable. [By Derek]
2) Add code which appends terminating nul byte as indication of the end of the
env list, after the last nul term env string. [By Pali]
Fixes: c4df0f6f31 ("arm: mvebu: Espressobin: Set default value for $fdtfile env variable")
Signed-off-by: Derek LaHousse <derek@seaofdirac.org>
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Stefan Roese <sr@denx.de>
ENTRY/ENDPROC macros from linux/linkage.h will make code more readable and
also will properly mark assembly symbol in ELF binary as function symbol.
Signed-off-by: Pali Rohár <pali@kernel.org>
Move this out of board file as this is done by the DM based NAND flash
driver. The EBI chip select configuration, iomux and timings are
handled by the driver
Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code. Doing this removes some board support code
which was also unused. Finally, this removes some CONFIG symbols that
otherwise needed to be migrated to Kconfig, but were unused in code now.
Signed-off-by: Tom Rini <trini@konsulko.com>
We only need to enable DM_ETH if we have a networking driver. All
networking drivers depend on DM_ETH being enabled, and their selection
ensures DM_ETH will be enabled.
Signed-off-by: Tom Rini <trini@konsulko.com>
Move a number of legacy USB UDC options to Kconfig, over from the config
header.
Cc: Pali Rohár <pali@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
This option controls using board/samsung/common/misc.c, so add a Kconfig
file there as well and select it from the boards which use this
functionality.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
This converts the following to Kconfig:
CONFIG_POWER_FSL
CONFIG_POWER_FSL_MC13892
CONFIG_POWER_HI6553
CONFIG_POWER_LTC3676
CONFIG_POWER_PFUZE100
CONFIG_POWER_PFUZE3000
CONFIG_POWER_SPI
CONFIG_POWER_TPS65090_EC
CONFIG_POWER_TPS65218
CONFIG_POWER_TPS65910
Signed-off-by: Tom Rini <trini@konsulko.com>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rest of the unmigrated CONFIG symbols in the SRIO namespace do not
easily transition to Kconfig. In many cases they likely should come from
the device tree instead. Move these out of CONFIG namespace and in to
CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and
CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many
cases they likely should come from the device tree instead. Move these
out of CONFIG namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NOR
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
SPL_FS_LOAD_PAYLOAD_NAME depends on SPL to be enabled.
If SPL is not enabled code still expects SPL_FS_LOAD_PAYLOAD_NAME to be
present. That's why setup proper dependency in the code.
And by doing so also change the logic around dfu_alt_info string
composition to be simpler.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3989c390a4acae13a1b05c040e14fb3d68bced02.1669986373.git.michal.simek@amd.com
The commit ed35de6170 ("Convert CONFIG_ZYNQMP_PSU_INIT_ENABLED to
Kconfig") converted CONFIG_ZYNQMP_PSU_INIT_ENABLED symbol and enabled it by
default which is not correct configuration.
Intention of this config was to have it enabled by default for SPL and
provide an option to users to also do low level initialization directly
from U-Boot.
That's why it is necessary to define second symbol with SPL marking in it
and properly use symbols depends on usage in Makefile.
Also disable ZYNQMP_PSU_INIT_ENABLED from boards which enables it by
default. CONFIG_SPL_ZYNQMP_PSU_INIT_ENABLED is enabled by default when SPL
is enabled.
Reported-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d5fcbd66b05bf0d7ef594e66464ee23b48c5e4cc.1669969083.git.michal.simek@amd.com
My Bootlin address is the preferred one now.
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20221203214939.56608-1-luca@lucaceresoli.net
Signed-off-by: Michal Simek <michal.simek@amd.com>
Peter accpeted to step up as a co-maintainer for the RPis.
Reflect that in the corresponding MAINTAINERS files.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
The sandbox config file is to be removed. Move the GUID declarations
needed for capsule update functionality to the board file where they
are used.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
vck190 system controller low level setup is the same for revB that's why
also create symlink to revA.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Removing the zynq_board_read_rom_ethaddr() function as
xlnx,eeprom is not used anymore. As all board dts to use
nvmem alias instead of xlnx,eeprom.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221017094818.17996-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Due to usage of PREBOOT in Kconfig, macro CONFIG_PREBOOT is always defined
when CONFIG_USE_PREBOOT is enabled. In case CONFIG_PREBOOT is not
explicitly enabled it is set to empty C string and therefore
'#ifdef CONFIG_PREBOOT' guard does not work. Fix this issue by introducing
a new Kconfig symbol PREBOOT_DEFINED which cause to define new C macro
CONFIG_PREBOOT_DEFINED only when CONFIG_PREBOOT is really defined.
Change usage of '#ifdef CONFIG_PREBOOT' by '#ifdef CONFIG_USE_PREBOOT' for
code which checks if preboot code would be called and by
'#ifdef CONFIG_PREBOOT_DEFINED' for defining preboot code.
Signed-off-by: Pali Rohár <pali@kernel.org>
This converts the following to Kconfig:
CONFIG_SYS_I2C_INIT_BOARD
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Switch to use binman to pack images
Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
commit 0543a1ed27 ("imx8m: fixup thermal trips") moved updating the
thermal trip points to all IMX8M so we can remove it from our board
specific dt config.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in conjunction
with the MSC SM2-MB-EP1 Mini-ITX Carrier Board.
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
In order to boot over USB, the device tree needs to enable
a few extra nodes in SPL. Since the USB driver has the
ability to detect host/device, the dr_mode can be removed
from the device tree since it needs to act as a device when
booting and OTG is the default mode. Add USB boot support
to spl_board_boot_device and enable the corresponding config
options.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
There are a few functions which are not essential for use in
SPL, but they take up enough space to make other preferred
features not fit. Remove the extras.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
The DDR is configured for LPDDR4 running at 1.6GHz which requires
the voltage on the PMIC to rise a bit before initializing LPDDR4
or it will be running out of spec.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The RD-AC5X-32G16HVG6HLG-A0 development board main components and
features include:
* Main 12V/54V power supply
* 270 Gbps throughput packet processor on the main board
* DDR4:
* SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
* SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
* PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
* 16GB eMMC (Samsung KLMAG1JETD-B041006)
* 16MB SPI NOR(GD25Q127C)
* 32 x 1000 Base-T interfaces
* 16 x 2500 Base-T interfaces
* SR1: 88E2540*4
* SR2: 88E2580*1+88E2540*2
* Six (6) x 25G Base-R SFP28 interfaces
* One (1) x RJ-45 console connector, interfacing to the on board UART
* One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
* One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
* One (1) x RJ-45 1G Base-T Management port, interfacing to the host
port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
* One (1) x Oculink port, interfacing to the PCIe port for external CPU
connection
* POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
solution)
* POE total power budget 780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham <judge.packham@gmail.com>
File name with pattern u-boot-spl* is used on all places except in kwb
image for binary with SPL-only code. Combined binary with both SPL and
proper U-Boot in other places has file name pattern u-boot-with-spl*.
Make it consistent also for kwb image and rename u-boot-spl.kwb to
u-boot-with-spl.kwb as this image contains both SPL and proper U-Boot code.
Also update documentation about file name changes.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This patch updates Microchip MPFS Icicle Kit support. For now,
add Microchip QSPI driver and a small 4MB reservation is
made at the end of 32-bit DDR to provide some memory for
the HSS to use.
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Resolve all uses of CONFIG_SYS_MHZ with the currently defined value.
Remove code which depends on CONFIG_SYS_MHZ but where no board configs
actually use that code.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The DT used for Calxeda Highbank and Midway systems exposes a "system
registers" block, modeled as a DT subnode.
This includes several clocks, including the two fixed clocks for the
main oscillator and timer.
So far U-Boot was ignorant of this special construct (a "clocks" node
within the "hb-sregs" node), as it didn't need the PLL clocks in there.
But that also meant we lost the fixed clocks, which form the base for
the UART baudrate generator and also the SP804 timer.
To allow the generic PL011 and SP804 driver to read the clock rate,
add a simple bus driver, which triggers the DT node discovery inside this
special node. As we only care about the fixed clocks (we don't have
drivers for the PLLs anyway), just ignore the address translation (for
now).
The binding is described in bindings/arm/calxeda/hb-sregs.yaml, the DT
snippet in question looks like:
=======================
sregs@fff3c000 {
compatible = "calxeda,hb-sregs";
reg = <0xfff3c000 0x1000>;
clocks {
#address-cells = <1>;
#size-cells = <0>;
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <33333000>;
};
....
};
};
=======================
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Add test cases for accessing the FWU Metadata on the sandbox
platform. The sandbox platform also uses the metadata access driver
for GPT partitioned block devices.
The FWU feature will be tested on the sandbox64 variant with a raw
capsule. Remove the FIT capsule testing from sandbox64 defconfig --
the FIT capsule test will be run on the sandbox_flattree variant.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
The FWU Multi Bank Update feature allows the platform to boot the
firmware images from one of the partitions(banks). The first stage
bootloader(fsbl) passes the value of the boot index, i.e. the bank
from which the firmware images were booted from to U-Boot. On the
STM32MP157C-DK2 board, this value is passed through one of the SoC's
backup register. Add a function to read the boot index value from the
backup register.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
